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f563a571 MC |
1 | /* |
2 | * Copyright (C) 2014 STMicroelectronics Limited. | |
3 | * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * publishhed by the Free Software Foundation. | |
8 | */ | |
f563a571 | 9 | #include "stih407-pinctrl.dtsi" |
358764f3 | 10 | #include <dt-bindings/mfd/st-lpc.h> |
b3d37f92 | 11 | #include <dt-bindings/phy/phy.h> |
efdf5aa8 | 12 | #include <dt-bindings/reset/stih407-resets.h> |
107dea0c | 13 | #include <dt-bindings/interrupt-controller/irq-st.h> |
f563a571 MC |
14 | / { |
15 | #address-cells = <1>; | |
16 | #size-cells = <1>; | |
17 | ||
fe135c63 LJ |
18 | reserved-memory { |
19 | #address-cells = <1>; | |
20 | #size-cells = <1>; | |
21 | ranges; | |
22 | ||
23 | gp0_reserved: rproc@40000000 { | |
24 | compatible = "shared-dma-pool"; | |
25 | reg = <0x40000000 0x01000000>; | |
26 | no-map; | |
27 | }; | |
28 | ||
29 | gp1_reserved: rproc@41000000 { | |
30 | compatible = "shared-dma-pool"; | |
31 | reg = <0x41000000 0x01000000>; | |
32 | no-map; | |
33 | }; | |
34 | ||
35 | audio_reserved: rproc@42000000 { | |
36 | compatible = "shared-dma-pool"; | |
37 | reg = <0x42000000 0x01000000>; | |
38 | no-map; | |
39 | }; | |
40 | ||
41 | dmu_reserved: rproc@43000000 { | |
42 | compatible = "shared-dma-pool"; | |
43 | reg = <0x43000000 0x01000000>; | |
44 | no-map; | |
45 | }; | |
46 | }; | |
47 | ||
f563a571 MC |
48 | cpus { |
49 | #address-cells = <1>; | |
50 | #size-cells = <0>; | |
51 | cpu@0 { | |
52 | device_type = "cpu"; | |
53 | compatible = "arm,cortex-a9"; | |
54 | reg = <0>; | |
6fef7953 | 55 | |
c1dc02da PG |
56 | /* u-boot puts hpen in SBC dmem at 0xa4 offset */ |
57 | cpu-release-addr = <0x94100A4>; | |
6fef7953 LJ |
58 | |
59 | /* kHz uV */ | |
60 | operating-points = <1500000 0 | |
61 | 1200000 0 | |
62 | 800000 0 | |
63 | 500000 0>; | |
4ad8f3ac LJ |
64 | |
65 | clocks = <&clk_m_a9>; | |
66 | clock-names = "cpu"; | |
67 | clock-latency = <100000>; | |
fe7de3c3 | 68 | cpu0-supply = <&pwm_regulator>; |
56092630 | 69 | st,syscfg = <&syscfg_core 0x8e0>; |
f563a571 MC |
70 | }; |
71 | cpu@1 { | |
72 | device_type = "cpu"; | |
73 | compatible = "arm,cortex-a9"; | |
74 | reg = <1>; | |
6fef7953 | 75 | |
c1dc02da PG |
76 | /* u-boot puts hpen in SBC dmem at 0xa4 offset */ |
77 | cpu-release-addr = <0x94100A4>; | |
6fef7953 LJ |
78 | |
79 | /* kHz uV */ | |
80 | operating-points = <1500000 0 | |
81 | 1200000 0 | |
82 | 800000 0 | |
83 | 500000 0>; | |
f563a571 MC |
84 | }; |
85 | }; | |
86 | ||
87 | intc: interrupt-controller@08761000 { | |
88 | compatible = "arm,cortex-a9-gic"; | |
89 | #interrupt-cells = <3>; | |
90 | interrupt-controller; | |
91 | reg = <0x08761000 0x1000>, <0x08760100 0x100>; | |
92 | }; | |
93 | ||
94 | scu@08760000 { | |
95 | compatible = "arm,cortex-a9-scu"; | |
96 | reg = <0x08760000 0x1000>; | |
97 | }; | |
98 | ||
99 | timer@08760200 { | |
100 | interrupt-parent = <&intc>; | |
101 | compatible = "arm,cortex-a9-global-timer"; | |
102 | reg = <0x08760200 0x100>; | |
103 | interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
104 | clocks = <&arm_periph_clk>; | |
105 | }; | |
106 | ||
107 | l2: cache-controller { | |
108 | compatible = "arm,pl310-cache"; | |
109 | reg = <0x08762000 0x1000>; | |
110 | arm,data-latency = <3 3 3>; | |
111 | arm,tag-latency = <2 2 2>; | |
112 | cache-unified; | |
113 | cache-level = <2>; | |
114 | }; | |
115 | ||
00133b91 LJ |
116 | arm-pmu { |
117 | interrupt-parent = <&intc>; | |
118 | compatible = "arm,cortex-a9-pmu"; | |
119 | interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; | |
120 | }; | |
121 | ||
23155ffc LJ |
122 | pwm_regulator: pwm-regulator { |
123 | compatible = "pwm-regulator"; | |
124 | pwms = <&pwm1 3 8448>; | |
125 | regulator-name = "CPU_1V0_AVS"; | |
126 | regulator-min-microvolt = <784000>; | |
127 | regulator-max-microvolt = <1299000>; | |
128 | regulator-always-on; | |
129 | max-duty-cycle = <255>; | |
130 | status = "okay"; | |
131 | }; | |
132 | ||
f563a571 MC |
133 | soc { |
134 | #address-cells = <1>; | |
135 | #size-cells = <1>; | |
136 | interrupt-parent = <&intc>; | |
137 | ranges; | |
138 | compatible = "simple-bus"; | |
139 | ||
48f3fe6b LJ |
140 | restart { |
141 | compatible = "st,stih407-restart"; | |
142 | st,syscfg = <&syscfg_sbc_reg>; | |
143 | status = "okay"; | |
144 | }; | |
145 | ||
b864a0b9 PG |
146 | powerdown: powerdown-controller { |
147 | compatible = "st,stih407-powerdown"; | |
148 | #reset-cells = <1>; | |
149 | }; | |
150 | ||
151 | softreset: softreset-controller { | |
152 | compatible = "st,stih407-softreset"; | |
153 | #reset-cells = <1>; | |
154 | }; | |
155 | ||
156 | picophyreset: picophyreset-controller { | |
157 | compatible = "st,stih407-picophyreset"; | |
158 | #reset-cells = <1>; | |
159 | }; | |
160 | ||
f563a571 MC |
161 | syscfg_sbc: sbc-syscfg@9620000 { |
162 | compatible = "st,stih407-sbc-syscfg", "syscon"; | |
163 | reg = <0x9620000 0x1000>; | |
164 | }; | |
165 | ||
166 | syscfg_front: front-syscfg@9280000 { | |
167 | compatible = "st,stih407-front-syscfg", "syscon"; | |
168 | reg = <0x9280000 0x1000>; | |
169 | }; | |
170 | ||
171 | syscfg_rear: rear-syscfg@9290000 { | |
172 | compatible = "st,stih407-rear-syscfg", "syscon"; | |
173 | reg = <0x9290000 0x1000>; | |
174 | }; | |
175 | ||
176 | syscfg_flash: flash-syscfg@92a0000 { | |
177 | compatible = "st,stih407-flash-syscfg", "syscon"; | |
178 | reg = <0x92a0000 0x1000>; | |
179 | }; | |
180 | ||
181 | syscfg_sbc_reg: fvdp-lite-syscfg@9600000 { | |
182 | compatible = "st,stih407-sbc-reg-syscfg", "syscon"; | |
183 | reg = <0x9600000 0x1000>; | |
184 | }; | |
185 | ||
186 | syscfg_core: core-syscfg@92b0000 { | |
187 | compatible = "st,stih407-core-syscfg", "syscon"; | |
188 | reg = <0x92b0000 0x1000>; | |
189 | }; | |
190 | ||
191 | syscfg_lpm: lpm-syscfg@94b5100 { | |
192 | compatible = "st,stih407-lpm-syscfg", "syscon"; | |
193 | reg = <0x94b5100 0x1000>; | |
194 | }; | |
195 | ||
107dea0c LJ |
196 | irq-syscfg { |
197 | compatible = "st,stih407-irq-syscfg"; | |
198 | st,syscfg = <&syscfg_core>; | |
199 | st,irq-device = <ST_IRQ_SYSCFG_PMU_0>, | |
200 | <ST_IRQ_SYSCFG_PMU_1>; | |
201 | st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>, | |
202 | <ST_IRQ_SYSCFG_DISABLED>; | |
203 | }; | |
204 | ||
759742d1 MC |
205 | /* Display */ |
206 | vtg_main: sti-vtg-main@8d02800 { | |
207 | compatible = "st,vtg"; | |
208 | reg = <0x8d02800 0x200>; | |
209 | interrupts = <GIC_SPI 108 IRQ_TYPE_NONE>; | |
210 | }; | |
211 | ||
212 | vtg_aux: sti-vtg-aux@8d00200 { | |
213 | compatible = "st,vtg"; | |
214 | reg = <0x8d00200 0x100>; | |
215 | interrupts = <GIC_SPI 109 IRQ_TYPE_NONE>; | |
216 | }; | |
217 | ||
f563a571 MC |
218 | serial@9830000 { |
219 | compatible = "st,asc"; | |
220 | reg = <0x9830000 0x2c>; | |
221 | interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>; | |
222 | pinctrl-names = "default"; | |
223 | pinctrl-0 = <&pinctrl_serial0>; | |
1befe7e4 | 224 | clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; |
f563a571 MC |
225 | |
226 | status = "disabled"; | |
227 | }; | |
228 | ||
229 | serial@9831000 { | |
230 | compatible = "st,asc"; | |
231 | reg = <0x9831000 0x2c>; | |
232 | interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>; | |
233 | pinctrl-names = "default"; | |
234 | pinctrl-0 = <&pinctrl_serial1>; | |
1befe7e4 | 235 | clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; |
f563a571 MC |
236 | |
237 | status = "disabled"; | |
238 | }; | |
239 | ||
240 | serial@9832000 { | |
241 | compatible = "st,asc"; | |
242 | reg = <0x9832000 0x2c>; | |
243 | interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>; | |
244 | pinctrl-names = "default"; | |
245 | pinctrl-0 = <&pinctrl_serial2>; | |
1befe7e4 | 246 | clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; |
f563a571 MC |
247 | |
248 | status = "disabled"; | |
249 | }; | |
250 | ||
251 | /* SBC_ASC0 - UART10 */ | |
252 | sbc_serial0: serial@9530000 { | |
253 | compatible = "st,asc"; | |
254 | reg = <0x9530000 0x2c>; | |
255 | interrupts = <GIC_SPI 138 IRQ_TYPE_NONE>; | |
256 | pinctrl-names = "default"; | |
257 | pinctrl-0 = <&pinctrl_sbc_serial0>; | |
258 | clocks = <&clk_sysin>; | |
259 | ||
260 | status = "disabled"; | |
261 | }; | |
262 | ||
263 | serial@9531000 { | |
264 | compatible = "st,asc"; | |
265 | reg = <0x9531000 0x2c>; | |
266 | interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>; | |
267 | pinctrl-names = "default"; | |
268 | pinctrl-0 = <&pinctrl_sbc_serial1>; | |
269 | clocks = <&clk_sysin>; | |
270 | ||
271 | status = "disabled"; | |
272 | }; | |
273 | ||
274 | i2c@9840000 { | |
275 | compatible = "st,comms-ssc4-i2c"; | |
276 | interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; | |
277 | reg = <0x9840000 0x110>; | |
1befe7e4 | 278 | clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; |
f563a571 MC |
279 | clock-names = "ssc"; |
280 | clock-frequency = <400000>; | |
281 | pinctrl-names = "default"; | |
282 | pinctrl-0 = <&pinctrl_i2c0_default>; | |
283 | ||
284 | status = "disabled"; | |
285 | }; | |
286 | ||
287 | i2c@9841000 { | |
288 | compatible = "st,comms-ssc4-i2c"; | |
289 | reg = <0x9841000 0x110>; | |
290 | interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; | |
1befe7e4 | 291 | clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; |
f563a571 MC |
292 | clock-names = "ssc"; |
293 | clock-frequency = <400000>; | |
294 | pinctrl-names = "default"; | |
295 | pinctrl-0 = <&pinctrl_i2c1_default>; | |
296 | ||
297 | status = "disabled"; | |
298 | }; | |
299 | ||
300 | i2c@9842000 { | |
301 | compatible = "st,comms-ssc4-i2c"; | |
302 | reg = <0x9842000 0x110>; | |
303 | interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; | |
1befe7e4 | 304 | clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; |
f563a571 MC |
305 | clock-names = "ssc"; |
306 | clock-frequency = <400000>; | |
307 | pinctrl-names = "default"; | |
308 | pinctrl-0 = <&pinctrl_i2c2_default>; | |
309 | ||
310 | status = "disabled"; | |
311 | }; | |
312 | ||
313 | i2c@9843000 { | |
314 | compatible = "st,comms-ssc4-i2c"; | |
315 | reg = <0x9843000 0x110>; | |
316 | interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; | |
1befe7e4 | 317 | clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; |
f563a571 MC |
318 | clock-names = "ssc"; |
319 | clock-frequency = <400000>; | |
320 | pinctrl-names = "default"; | |
321 | pinctrl-0 = <&pinctrl_i2c3_default>; | |
322 | ||
323 | status = "disabled"; | |
324 | }; | |
325 | ||
326 | i2c@9844000 { | |
327 | compatible = "st,comms-ssc4-i2c"; | |
328 | reg = <0x9844000 0x110>; | |
329 | interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; | |
1befe7e4 | 330 | clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; |
f563a571 MC |
331 | clock-names = "ssc"; |
332 | clock-frequency = <400000>; | |
333 | pinctrl-names = "default"; | |
334 | pinctrl-0 = <&pinctrl_i2c4_default>; | |
335 | ||
336 | status = "disabled"; | |
337 | }; | |
338 | ||
339 | i2c@9845000 { | |
340 | compatible = "st,comms-ssc4-i2c"; | |
341 | reg = <0x9845000 0x110>; | |
342 | interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; | |
1befe7e4 | 343 | clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; |
f563a571 MC |
344 | clock-names = "ssc"; |
345 | clock-frequency = <400000>; | |
346 | pinctrl-names = "default"; | |
347 | pinctrl-0 = <&pinctrl_i2c5_default>; | |
348 | ||
349 | status = "disabled"; | |
350 | }; | |
351 | ||
352 | ||
353 | /* SSCs on SBC */ | |
354 | i2c@9540000 { | |
355 | compatible = "st,comms-ssc4-i2c"; | |
356 | reg = <0x9540000 0x110>; | |
357 | interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; | |
358 | clocks = <&clk_sysin>; | |
359 | clock-names = "ssc"; | |
360 | clock-frequency = <400000>; | |
361 | pinctrl-names = "default"; | |
362 | pinctrl-0 = <&pinctrl_i2c10_default>; | |
363 | ||
364 | status = "disabled"; | |
365 | }; | |
366 | ||
367 | i2c@9541000 { | |
368 | compatible = "st,comms-ssc4-i2c"; | |
369 | reg = <0x9541000 0x110>; | |
370 | interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; | |
371 | clocks = <&clk_sysin>; | |
372 | clock-names = "ssc"; | |
373 | clock-frequency = <400000>; | |
374 | pinctrl-names = "default"; | |
375 | pinctrl-0 = <&pinctrl_i2c11_default>; | |
376 | ||
377 | status = "disabled"; | |
378 | }; | |
8facce13 PG |
379 | |
380 | usb2_picophy0: phy1 { | |
381 | compatible = "st,stih407-usb2-phy"; | |
382 | #phy-cells = <0>; | |
383 | st,syscfg = <&syscfg_core 0x100 0xf4>; | |
384 | resets = <&softreset STIH407_PICOPHY_SOFTRESET>, | |
743ac9d2 | 385 | <&picophyreset STIH407_PICOPHY2_RESET>; |
8facce13 PG |
386 | reset-names = "global", "port"; |
387 | }; | |
b26373c0 GF |
388 | |
389 | miphy28lp_phy: miphy28lp@9b22000 { | |
390 | compatible = "st,miphy28lp-phy"; | |
391 | st,syscfg = <&syscfg_core>; | |
392 | #address-cells = <1>; | |
393 | #size-cells = <1>; | |
394 | ranges; | |
395 | ||
396 | phy_port0: port@9b22000 { | |
397 | reg = <0x9b22000 0xff>, | |
398 | <0x9b09000 0xff>, | |
399 | <0x9b04000 0xff>; | |
400 | reg-names = "sata-up", | |
401 | "pcie-up", | |
402 | "pipew"; | |
403 | ||
404 | st,syscfg = <0x114 0x818 0xe0 0xec>; | |
405 | #phy-cells = <1>; | |
406 | ||
407 | reset-names = "miphy-sw-rst"; | |
408 | resets = <&softreset STIH407_MIPHY0_SOFTRESET>; | |
409 | }; | |
410 | ||
411 | phy_port1: port@9b2a000 { | |
412 | reg = <0x9b2a000 0xff>, | |
413 | <0x9b19000 0xff>, | |
414 | <0x9b14000 0xff>; | |
415 | reg-names = "sata-up", | |
416 | "pcie-up", | |
417 | "pipew"; | |
418 | ||
419 | st,syscfg = <0x118 0x81c 0xe4 0xf0>; | |
420 | ||
421 | #phy-cells = <1>; | |
422 | ||
423 | reset-names = "miphy-sw-rst"; | |
424 | resets = <&softreset STIH407_MIPHY1_SOFTRESET>; | |
425 | }; | |
426 | ||
427 | phy_port2: port@8f95000 { | |
428 | reg = <0x8f95000 0xff>, | |
429 | <0x8f90000 0xff>; | |
430 | reg-names = "pipew", | |
431 | "usb3-up"; | |
432 | ||
433 | st,syscfg = <0x11c 0x820>; | |
434 | ||
435 | #phy-cells = <1>; | |
436 | ||
437 | reset-names = "miphy-sw-rst"; | |
438 | resets = <&softreset STIH407_MIPHY2_SOFTRESET>; | |
439 | }; | |
440 | }; | |
2c53c272 LJ |
441 | |
442 | spi@9840000 { | |
443 | compatible = "st,comms-ssc4-spi"; | |
444 | reg = <0x9840000 0x110>; | |
445 | interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; | |
446 | clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; | |
447 | clock-names = "ssc"; | |
448 | pinctrl-0 = <&pinctrl_spi0_default>; | |
449 | pinctrl-names = "default"; | |
450 | #address-cells = <1>; | |
451 | #size-cells = <0>; | |
452 | ||
453 | status = "disabled"; | |
454 | }; | |
455 | ||
456 | spi@9841000 { | |
457 | compatible = "st,comms-ssc4-spi"; | |
458 | reg = <0x9841000 0x110>; | |
459 | interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; | |
460 | clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; | |
461 | clock-names = "ssc"; | |
55fd9b18 PG |
462 | pinctrl-names = "default"; |
463 | pinctrl-0 = <&pinctrl_spi1_default>; | |
2c53c272 LJ |
464 | |
465 | status = "disabled"; | |
466 | }; | |
467 | ||
468 | spi@9842000 { | |
469 | compatible = "st,comms-ssc4-spi"; | |
470 | reg = <0x9842000 0x110>; | |
471 | interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; | |
472 | clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; | |
473 | clock-names = "ssc"; | |
55fd9b18 PG |
474 | pinctrl-names = "default"; |
475 | pinctrl-0 = <&pinctrl_spi2_default>; | |
2c53c272 LJ |
476 | |
477 | status = "disabled"; | |
478 | }; | |
479 | ||
480 | spi@9843000 { | |
481 | compatible = "st,comms-ssc4-spi"; | |
482 | reg = <0x9843000 0x110>; | |
483 | interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; | |
484 | clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; | |
485 | clock-names = "ssc"; | |
55fd9b18 PG |
486 | pinctrl-names = "default"; |
487 | pinctrl-0 = <&pinctrl_spi3_default>; | |
2c53c272 LJ |
488 | |
489 | status = "disabled"; | |
490 | }; | |
491 | ||
492 | spi@9844000 { | |
493 | compatible = "st,comms-ssc4-spi"; | |
494 | reg = <0x9844000 0x110>; | |
495 | interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; | |
496 | clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; | |
497 | clock-names = "ssc"; | |
55fd9b18 PG |
498 | pinctrl-names = "default"; |
499 | pinctrl-0 = <&pinctrl_spi4_default>; | |
2c53c272 LJ |
500 | |
501 | status = "disabled"; | |
502 | }; | |
b0bb2bae LJ |
503 | |
504 | /* SBC SSC */ | |
505 | spi@9540000 { | |
506 | compatible = "st,comms-ssc4-spi"; | |
507 | reg = <0x9540000 0x110>; | |
508 | interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; | |
509 | clocks = <&clk_sysin>; | |
510 | clock-names = "ssc"; | |
55fd9b18 PG |
511 | pinctrl-names = "default"; |
512 | pinctrl-0 = <&pinctrl_spi10_default>; | |
b0bb2bae LJ |
513 | |
514 | status = "disabled"; | |
515 | }; | |
516 | ||
517 | spi@9541000 { | |
518 | compatible = "st,comms-ssc4-spi"; | |
519 | reg = <0x9541000 0x110>; | |
520 | interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; | |
521 | clocks = <&clk_sysin>; | |
522 | clock-names = "ssc"; | |
55fd9b18 PG |
523 | pinctrl-names = "default"; |
524 | pinctrl-0 = <&pinctrl_spi11_default>; | |
b0bb2bae LJ |
525 | |
526 | status = "disabled"; | |
527 | }; | |
528 | ||
529 | spi@9542000 { | |
530 | compatible = "st,comms-ssc4-spi"; | |
531 | reg = <0x9542000 0x110>; | |
532 | interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; | |
533 | clocks = <&clk_sysin>; | |
534 | clock-names = "ssc"; | |
55fd9b18 PG |
535 | pinctrl-names = "default"; |
536 | pinctrl-0 = <&pinctrl_spi12_default>; | |
b0bb2bae LJ |
537 | |
538 | status = "disabled"; | |
539 | }; | |
9286ac48 PG |
540 | |
541 | mmc0: sdhci@09060000 { | |
542 | compatible = "st,sdhci-stih407", "st,sdhci"; | |
543 | status = "disabled"; | |
544 | reg = <0x09060000 0x7ff>, <0x9061008 0x20>; | |
545 | reg-names = "mmc", "top-mmc-delay"; | |
546 | interrupts = <GIC_SPI 92 IRQ_TYPE_NONE>; | |
547 | interrupt-names = "mmcirq"; | |
548 | pinctrl-names = "default"; | |
549 | pinctrl-0 = <&pinctrl_mmc0>; | |
550 | clock-names = "mmc"; | |
551 | clocks = <&clk_s_c0_flexgen CLK_MMC_0>; | |
552 | bus-width = <8>; | |
553 | non-removable; | |
554 | }; | |
555 | ||
556 | mmc1: sdhci@09080000 { | |
557 | compatible = "st,sdhci-stih407", "st,sdhci"; | |
558 | status = "disabled"; | |
559 | reg = <0x09080000 0x7ff>; | |
560 | reg-names = "mmc"; | |
561 | interrupts = <GIC_SPI 90 IRQ_TYPE_NONE>; | |
562 | interrupt-names = "mmcirq"; | |
563 | pinctrl-names = "default"; | |
564 | pinctrl-0 = <&pinctrl_sd1>; | |
565 | clock-names = "mmc"; | |
566 | clocks = <&clk_s_c0_flexgen CLK_MMC_1>; | |
567 | resets = <&softreset STIH407_MMC1_SOFTRESET>; | |
568 | bus-width = <4>; | |
569 | }; | |
358764f3 LJ |
570 | |
571 | /* Watchdog and Real-Time Clock */ | |
572 | lpc@8787000 { | |
573 | compatible = "st,stih407-lpc"; | |
574 | reg = <0x8787000 0x1000>; | |
575 | interrupts = <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>; | |
576 | clocks = <&clk_s_d3_flexgen CLK_LPC_0>; | |
577 | timeout-sec = <120>; | |
578 | st,syscfg = <&syscfg_core>; | |
579 | st,lpc-mode = <ST_LPC_MODE_WDT>; | |
580 | }; | |
581 | ||
582 | lpc@8788000 { | |
583 | compatible = "st,stih407-lpc"; | |
584 | reg = <0x8788000 0x1000>; | |
585 | interrupts = <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>; | |
586 | clocks = <&clk_s_d3_flexgen CLK_LPC_1>; | |
3d90bc05 | 587 | st,lpc-mode = <ST_LPC_MODE_CLKSRC>; |
358764f3 | 588 | }; |
b3d37f92 PG |
589 | |
590 | sata0: sata@9b20000 { | |
591 | compatible = "st,ahci"; | |
592 | reg = <0x9b20000 0x1000>; | |
593 | ||
594 | interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>; | |
595 | interrupt-names = "hostc"; | |
596 | ||
597 | phys = <&phy_port0 PHY_TYPE_SATA>; | |
598 | phy-names = "ahci_phy"; | |
599 | ||
600 | resets = <&powerdown STIH407_SATA0_POWERDOWN>, | |
601 | <&softreset STIH407_SATA0_SOFTRESET>, | |
602 | <&softreset STIH407_SATA0_PWR_SOFTRESET>; | |
603 | reset-names = "pwr-dwn", "sw-rst", "pwr-rst"; | |
604 | ||
605 | clock-names = "ahci_clk"; | |
606 | clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; | |
607 | ||
608 | status = "disabled"; | |
609 | }; | |
610 | ||
611 | sata1: sata@9b28000 { | |
612 | compatible = "st,ahci"; | |
613 | reg = <0x9b28000 0x1000>; | |
614 | ||
615 | interrupts = <GIC_SPI 170 IRQ_TYPE_NONE>; | |
616 | interrupt-names = "hostc"; | |
617 | ||
618 | phys = <&phy_port1 PHY_TYPE_SATA>; | |
619 | phy-names = "ahci_phy"; | |
620 | ||
621 | resets = <&powerdown STIH407_SATA1_POWERDOWN>, | |
622 | <&softreset STIH407_SATA1_SOFTRESET>, | |
623 | <&softreset STIH407_SATA1_PWR_SOFTRESET>; | |
624 | reset-names = "pwr-dwn", | |
625 | "sw-rst", | |
626 | "pwr-rst"; | |
627 | ||
628 | clock-names = "ahci_clk"; | |
629 | clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; | |
630 | ||
631 | status = "disabled"; | |
632 | }; | |
fd555998 | 633 | |
cd9f59ca | 634 | |
fd555998 PG |
635 | st_dwc3: dwc3@8f94000 { |
636 | compatible = "st,stih407-dwc3"; | |
637 | reg = <0x08f94000 0x1000>, <0x110 0x4>; | |
638 | reg-names = "reg-glue", "syscfg-reg"; | |
639 | st,syscfg = <&syscfg_core>; | |
640 | resets = <&powerdown STIH407_USB3_POWERDOWN>, | |
641 | <&softreset STIH407_MIPHY2_SOFTRESET>; | |
642 | reset-names = "powerdown", "softreset"; | |
643 | #address-cells = <1>; | |
644 | #size-cells = <1>; | |
645 | pinctrl-names = "default"; | |
646 | pinctrl-0 = <&pinctrl_usb3>; | |
647 | ranges; | |
648 | ||
649 | status = "disabled"; | |
650 | ||
651 | dwc3: dwc3@9900000 { | |
652 | compatible = "snps,dwc3"; | |
653 | reg = <0x09900000 0x100000>; | |
654 | interrupts = <GIC_SPI 155 IRQ_TYPE_NONE>; | |
655 | dr_mode = "host"; | |
656 | phy-names = "usb2-phy", "usb3-phy"; | |
657 | phys = <&usb2_picophy0>, | |
658 | <&phy_port2 PHY_TYPE_USB3>; | |
659 | }; | |
660 | }; | |
cd9f59ca LJ |
661 | |
662 | /* COMMS PWM Module */ | |
663 | pwm0: pwm@9810000 { | |
664 | compatible = "st,sti-pwm"; | |
cd9f59ca LJ |
665 | #pwm-cells = <2>; |
666 | reg = <0x9810000 0x68>; | |
667 | pinctrl-names = "default"; | |
668 | pinctrl-0 = <&pinctrl_pwm0_chan0_default>; | |
669 | clock-names = "pwm"; | |
670 | clocks = <&clk_sysin>; | |
671 | st,pwm-num-chan = <1>; | |
8aa5f09d MC |
672 | |
673 | status = "disabled"; | |
cd9f59ca LJ |
674 | }; |
675 | ||
676 | /* SBC PWM Module */ | |
677 | pwm1: pwm@9510000 { | |
678 | compatible = "st,sti-pwm"; | |
cd9f59ca LJ |
679 | #pwm-cells = <2>; |
680 | reg = <0x9510000 0x68>; | |
681 | pinctrl-names = "default"; | |
682 | pinctrl-0 = <&pinctrl_pwm1_chan0_default | |
683 | &pinctrl_pwm1_chan1_default | |
684 | &pinctrl_pwm1_chan2_default | |
685 | &pinctrl_pwm1_chan3_default>; | |
686 | clock-names = "pwm"; | |
687 | clocks = <&clk_sysin>; | |
688 | st,pwm-num-chan = <4>; | |
8aa5f09d MC |
689 | |
690 | status = "disabled"; | |
cd9f59ca | 691 | }; |
cae010a1 LJ |
692 | |
693 | rng10: rng@08a89000 { | |
694 | compatible = "st,rng"; | |
695 | reg = <0x08a89000 0x1000>; | |
696 | clocks = <&clk_sysin>; | |
697 | status = "okay"; | |
698 | }; | |
699 | ||
700 | rng11: rng@08a8a000 { | |
701 | compatible = "st,rng"; | |
702 | reg = <0x08a8a000 0x1000>; | |
703 | clocks = <&clk_sysin>; | |
704 | status = "okay"; | |
705 | }; | |
ab511d7d MC |
706 | |
707 | ethernet0: dwmac@9630000 { | |
708 | device_type = "network"; | |
709 | status = "disabled"; | |
710 | compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710"; | |
711 | reg = <0x9630000 0x8000>, <0x80 0x4>; | |
712 | reg-names = "stmmaceth", "sti-ethconf"; | |
713 | ||
714 | st,syscon = <&syscfg_sbc_reg 0x80>; | |
715 | st,gmac_en; | |
716 | resets = <&softreset STIH407_ETH1_SOFTRESET>; | |
717 | reset-names = "stmmaceth"; | |
718 | ||
719 | interrupts = <GIC_SPI 98 IRQ_TYPE_NONE>, | |
720 | <GIC_SPI 99 IRQ_TYPE_NONE>; | |
721 | interrupt-names = "macirq", "eth_wake_irq"; | |
722 | ||
723 | /* DMA Bus Mode */ | |
724 | snps,pbl = <8>; | |
725 | ||
726 | pinctrl-names = "default"; | |
727 | pinctrl-0 = <&pinctrl_rgmii1>; | |
728 | ||
729 | clock-names = "stmmaceth", "sti-ethclk"; | |
730 | clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>, | |
731 | <&clk_s_c0_flexgen CLK_ETH_PHY>; | |
cd9f59ca | 732 | }; |
ba25d8b4 LJ |
733 | |
734 | rng10: rng@08a89000 { | |
735 | compatible = "st,rng"; | |
736 | reg = <0x08a89000 0x1000>; | |
737 | clocks = <&clk_sysin>; | |
738 | status = "okay"; | |
739 | }; | |
740 | ||
741 | rng11: rng@08a8a000 { | |
742 | compatible = "st,rng"; | |
743 | reg = <0x08a8a000 0x1000>; | |
744 | clocks = <&clk_sysin>; | |
745 | status = "okay"; | |
746 | }; | |
6e966f13 LJ |
747 | |
748 | mailbox0: mailbox@8f00000 { | |
749 | compatible = "st,stih407-mailbox"; | |
750 | reg = <0x8f00000 0x1000>; | |
751 | interrupts = <GIC_SPI 1 IRQ_TYPE_NONE>; | |
752 | #mbox-cells = <2>; | |
753 | mbox-name = "a9"; | |
754 | status = "okay"; | |
755 | }; | |
756 | ||
757 | mailbox1: mailbox@8f01000 { | |
758 | compatible = "st,stih407-mailbox"; | |
759 | reg = <0x8f01000 0x1000>; | |
760 | #mbox-cells = <2>; | |
761 | mbox-name = "st231_gp_1"; | |
762 | status = "okay"; | |
763 | }; | |
764 | ||
765 | mailbox2: mailbox@8f02000 { | |
766 | compatible = "st,stih407-mailbox"; | |
767 | reg = <0x8f02000 0x1000>; | |
768 | #mbox-cells = <2>; | |
769 | mbox-name = "st231_gp_0"; | |
770 | status = "okay"; | |
771 | }; | |
772 | ||
773 | mailbox3: mailbox@8f03000 { | |
774 | compatible = "st,stih407-mailbox"; | |
775 | reg = <0x8f03000 0x1000>; | |
776 | #mbox-cells = <2>; | |
777 | mbox-name = "st231_audio_video"; | |
778 | status = "okay"; | |
779 | }; | |
3ff0a019 | 780 | |
fe135c63 | 781 | st231_gp0: remote-processor { |
3ff0a019 | 782 | compatible = "st,st231-rproc"; |
fe135c63 | 783 | memory-region = <&gp0_reserved>; |
3ff0a019 LJ |
784 | resets = <&softreset STIH407_ST231_GP0_SOFTRESET>; |
785 | reset-names = "sw_reset"; | |
786 | clocks = <&clk_s_c0_flexgen CLK_ST231_GP_0>; | |
787 | clock-frequency = <600000000>; | |
788 | st,syscfg = <&syscfg_core 0x22c>; | |
789 | }; | |
790 | ||
fe135c63 LJ |
791 | |
792 | st231_gp1: remote-processor { | |
3ff0a019 | 793 | compatible = "st,st231-rproc"; |
fe135c63 | 794 | memory-region = <&gp1_reserved>; |
3ff0a019 LJ |
795 | resets = <&softreset STIH407_ST231_GP1_SOFTRESET>; |
796 | reset-names = "sw_reset"; | |
797 | clocks = <&clk_s_c0_flexgen CLK_ST231_GP_1>; | |
798 | clock-frequency = <600000000>; | |
799 | st,syscfg = <&syscfg_core 0x220>; | |
800 | }; | |
801 | ||
fe135c63 | 802 | st231_audio: remote-processor { |
3ff0a019 | 803 | compatible = "st,st231-rproc"; |
fe135c63 | 804 | memory-region = <&audio_reserved>; |
3ff0a019 LJ |
805 | resets = <&softreset STIH407_ST231_AUD_SOFTRESET>; |
806 | reset-names = "sw_reset"; | |
807 | clocks = <&clk_s_c0_flexgen CLK_ST231_AUD_0>; | |
808 | clock-frequency = <600000000>; | |
809 | st,syscfg = <&syscfg_core 0x228>; | |
810 | }; | |
811 | ||
fe135c63 | 812 | st231_dmu: remote-processor { |
3ff0a019 | 813 | compatible = "st,st231-rproc"; |
fe135c63 | 814 | memory-region = <&dmu_reserved>; |
3ff0a019 LJ |
815 | resets = <&softreset STIH407_ST231_DMU_SOFTRESET>; |
816 | reset-names = "sw_reset"; | |
817 | clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>; | |
818 | clock-frequency = <600000000>; | |
819 | st,syscfg = <&syscfg_core 0x224>; | |
820 | }; | |
f563a571 MC |
821 | }; |
822 | }; |