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a01a35e0 GF |
1 | /* |
2 | * Copyright (C) 2015 STMicroelectronics Limited. | |
3 | * Author: Gabriel Fernandez <gabriel.fernandez@linaro.org> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * publishhed by the Free Software Foundation. | |
8 | */ | |
9 | #include "stih407-clock.dtsi" | |
10 | #include "stih407-family.dtsi" | |
11 | / { | |
12 | soc { | |
a01a35e0 GF |
13 | sti-display-subsystem { |
14 | compatible = "st,sti-display-subsystem"; | |
15 | #address-cells = <1>; | |
16 | #size-cells = <1>; | |
17 | ||
18 | assigned-clocks = <&clk_s_d2_quadfs 0>, | |
19 | <&clk_s_d2_quadfs 0>, | |
20 | <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, | |
21 | <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, | |
22 | <&clk_s_d2_flexgen CLK_PIX_GDP1>, | |
23 | <&clk_s_d2_flexgen CLK_PIX_GDP2>, | |
24 | <&clk_s_d2_flexgen CLK_PIX_GDP3>, | |
25 | <&clk_s_d2_flexgen CLK_PIX_GDP4>; | |
26 | ||
27 | assigned-clock-parents = <0>, | |
28 | <0>, | |
29 | <&clk_s_d2_quadfs 0>, | |
30 | <&clk_s_d2_quadfs 0>, | |
31 | <&clk_s_d2_quadfs 0>, | |
32 | <&clk_s_d2_quadfs 0>, | |
33 | <&clk_s_d2_quadfs 0>, | |
34 | <&clk_s_d2_quadfs 0>; | |
35 | ||
36 | assigned-clock-rates = <297000000>, <297000000>; | |
37 | ||
38 | ranges; | |
39 | ||
40 | sti-compositor@9d11000 { | |
41 | compatible = "st,stih407-compositor"; | |
42 | reg = <0x9d11000 0x1000>; | |
43 | ||
44 | clock-names = "compo_main", | |
45 | "compo_aux", | |
46 | "pix_main", | |
47 | "pix_aux", | |
48 | "pix_gdp1", | |
49 | "pix_gdp2", | |
50 | "pix_gdp3", | |
51 | "pix_gdp4", | |
52 | "main_parent", | |
53 | "aux_parent"; | |
54 | ||
55 | clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>, | |
56 | <&clk_s_c0_flexgen CLK_COMPO_DVP>, | |
57 | <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, | |
58 | <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, | |
59 | <&clk_s_d2_flexgen CLK_PIX_GDP1>, | |
60 | <&clk_s_d2_flexgen CLK_PIX_GDP2>, | |
61 | <&clk_s_d2_flexgen CLK_PIX_GDP3>, | |
62 | <&clk_s_d2_flexgen CLK_PIX_GDP4>, | |
63 | <&clk_s_d2_quadfs 0>, | |
64 | <&clk_s_d2_quadfs 1>; | |
65 | ||
66 | reset-names = "compo-main", "compo-aux"; | |
67 | resets = <&softreset STIH407_COMPO_SOFTRESET>, | |
68 | <&softreset STIH407_COMPO_SOFTRESET>; | |
69 | st,vtg = <&vtg_main>, <&vtg_aux>; | |
70 | }; | |
71 | ||
72 | sti-tvout@8d08000 { | |
73 | compatible = "st,stih407-tvout"; | |
74 | reg = <0x8d08000 0x1000>; | |
75 | reg-names = "tvout-reg"; | |
76 | reset-names = "tvout"; | |
77 | resets = <&softreset STIH407_HDTVOUT_SOFTRESET>; | |
78 | #address-cells = <1>; | |
79 | #size-cells = <1>; | |
80 | assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>, | |
81 | <&clk_s_d2_flexgen CLK_TMDS_HDMI>, | |
82 | <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, | |
83 | <&clk_s_d0_flexgen CLK_PCM_0>, | |
84 | <&clk_s_d2_flexgen CLK_PIX_HDDAC>, | |
85 | <&clk_s_d2_flexgen CLK_HDDAC>; | |
86 | ||
87 | assigned-clock-parents = <&clk_s_d2_quadfs 0>, | |
88 | <&clk_tmdsout_hdmi>, | |
89 | <&clk_s_d2_quadfs 0>, | |
90 | <&clk_s_d0_quadfs 0>, | |
91 | <&clk_s_d2_quadfs 0>, | |
92 | <&clk_s_d2_quadfs 0>; | |
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93 | }; |
94 | ||
95 | sti-hdmi@8d04000 { | |
96 | compatible = "st,stih407-hdmi"; | |
97 | reg = <0x8d04000 0x1000>; | |
98 | reg-names = "hdmi-reg"; | |
99 | interrupts = <GIC_SPI 106 IRQ_TYPE_NONE>; | |
100 | interrupt-names = "irq"; | |
101 | clock-names = "pix", | |
102 | "tmds", | |
103 | "phy", | |
104 | "audio", | |
105 | "main_parent", | |
106 | "aux_parent"; | |
107 | ||
108 | clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>, | |
109 | <&clk_s_d2_flexgen CLK_TMDS_HDMI>, | |
110 | <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, | |
111 | <&clk_s_d0_flexgen CLK_PCM_0>, | |
112 | <&clk_s_d2_quadfs 0>, | |
113 | <&clk_s_d2_quadfs 1>; | |
114 | ||
115 | hdmi,hpd-gpio = <&pio5 3>; | |
116 | reset-names = "hdmi"; | |
117 | resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>; | |
118 | ddc = <&hdmiddc>; | |
119 | }; | |
120 | ||
121 | sti-hda@8d02000 { | |
122 | compatible = "st,stih407-hda"; | |
123 | reg = <0x8d02000 0x400>, <0x92b0120 0x4>; | |
124 | reg-names = "hda-reg", "video-dacs-ctrl"; | |
125 | clock-names = "pix", | |
126 | "hddac", | |
127 | "main_parent", | |
128 | "aux_parent"; | |
129 | clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>, | |
130 | <&clk_s_d2_flexgen CLK_HDDAC>, | |
131 | <&clk_s_d2_quadfs 0>, | |
132 | <&clk_s_d2_quadfs 1>; | |
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133 | }; |
134 | }; | |
135 | }; | |
136 | }; |