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b16b77a5 PG |
1 | /* |
2 | * Copyright (C) 2014 STMicroelectronics R&D Limited | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | #include <dt-bindings/clock/stih410-clks.h> | |
9 | / { | |
10 | clocks { | |
11 | #address-cells = <1>; | |
12 | #size-cells = <1>; | |
13 | ranges; | |
14 | ||
15 | compatible = "st,stih410-clk", "simple-bus"; | |
16 | ||
17 | /* | |
18 | * Fixed 30MHz oscillator inputs to SoC | |
19 | */ | |
20 | clk_sysin: clk-sysin { | |
21 | #clock-cells = <0>; | |
22 | compatible = "fixed-clock"; | |
23 | clock-frequency = <30000000>; | |
24 | clock-output-names = "CLK_SYSIN"; | |
25 | }; | |
26 | ||
27 | /* | |
28 | * ARM Peripheral clock for timers | |
29 | */ | |
30 | arm_periph_clk: clk-m-a9-periphs { | |
31 | #clock-cells = <0>; | |
32 | compatible = "fixed-factor-clock"; | |
33 | clocks = <&clk_m_a9>; | |
34 | clock-div = <2>; | |
35 | clock-mult = <1>; | |
36 | }; | |
37 | ||
38 | /* | |
39 | * A9 PLL. | |
40 | */ | |
41 | clockgen-a9@92b0000 { | |
42 | compatible = "st,clkgen-c32"; | |
43 | reg = <0x92b0000 0xffff>; | |
44 | ||
45 | clockgen_a9_pll: clockgen-a9-pll { | |
46 | #clock-cells = <1>; | |
47 | compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32"; | |
48 | ||
49 | clocks = <&clk_sysin>; | |
50 | ||
51 | clock-output-names = "clockgen-a9-pll-odf"; | |
52 | }; | |
53 | }; | |
54 | ||
55 | /* | |
56 | * ARM CPU related clocks. | |
57 | */ | |
58 | clk_m_a9: clk-m-a9@92b0000 { | |
59 | #clock-cells = <0>; | |
60 | compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux"; | |
61 | reg = <0x92b0000 0x10000>; | |
62 | ||
63 | clocks = <&clockgen_a9_pll 0>, | |
64 | <&clockgen_a9_pll 0>, | |
65 | <&clk_s_c0_flexgen 13>, | |
66 | <&clk_m_a9_ext2f_div2>; | |
67 | }; | |
68 | ||
69 | /* | |
70 | * ARM Peripheral clock for timers | |
71 | */ | |
72 | clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { | |
73 | #clock-cells = <0>; | |
74 | compatible = "fixed-factor-clock"; | |
75 | ||
76 | clocks = <&clk_s_c0_flexgen 13>; | |
77 | ||
78 | clock-output-names = "clk-m-a9-ext2f-div2"; | |
79 | ||
80 | clock-div = <2>; | |
81 | clock-mult = <1>; | |
82 | }; | |
83 | ||
84 | /* | |
85 | * Bootloader initialized system infrastructure clock for | |
86 | * serial devices. | |
87 | */ | |
88 | clk_ext2f_a9: clockgen-c0@13 { | |
89 | #clock-cells = <0>; | |
90 | compatible = "fixed-clock"; | |
91 | clock-frequency = <200000000>; | |
92 | clock-output-names = "clk-s-icn-reg-0"; | |
93 | }; | |
94 | ||
95 | clockgen-a@090ff000 { | |
96 | compatible = "st,clkgen-c32"; | |
97 | reg = <0x90ff000 0x1000>; | |
98 | ||
99 | clk_s_a0_pll: clk-s-a0-pll { | |
100 | #clock-cells = <1>; | |
101 | compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32"; | |
102 | ||
103 | clocks = <&clk_sysin>; | |
104 | ||
105 | clock-output-names = "clk-s-a0-pll-ofd-0"; | |
106 | }; | |
107 | ||
108 | clk_s_a0_flexgen: clk-s-a0-flexgen { | |
109 | compatible = "st,flexgen"; | |
110 | ||
111 | #clock-cells = <1>; | |
112 | ||
113 | clocks = <&clk_s_a0_pll 0>, | |
114 | <&clk_sysin>; | |
115 | ||
116 | clock-output-names = "clk-ic-lmi0", | |
117 | "clk-ic-lmi1"; | |
118 | }; | |
119 | }; | |
120 | ||
121 | clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 { | |
122 | #clock-cells = <1>; | |
123 | compatible = "st,stih407-quadfs660-C", "st,quadfs"; | |
124 | reg = <0x9103000 0x1000>; | |
125 | ||
126 | clocks = <&clk_sysin>; | |
127 | ||
128 | clock-output-names = "clk-s-c0-fs0-ch0", | |
129 | "clk-s-c0-fs0-ch1", | |
130 | "clk-s-c0-fs0-ch2", | |
131 | "clk-s-c0-fs0-ch3"; | |
132 | }; | |
133 | ||
134 | clk_s_c0: clockgen-c@09103000 { | |
135 | compatible = "st,clkgen-c32"; | |
136 | reg = <0x9103000 0x1000>; | |
137 | ||
138 | clk_s_c0_pll0: clk-s-c0-pll0 { | |
139 | #clock-cells = <1>; | |
140 | compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32"; | |
141 | ||
142 | clocks = <&clk_sysin>; | |
143 | ||
144 | clock-output-names = "clk-s-c0-pll0-odf-0"; | |
145 | }; | |
146 | ||
147 | clk_s_c0_pll1: clk-s-c0-pll1 { | |
148 | #clock-cells = <1>; | |
149 | compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32"; | |
150 | ||
151 | clocks = <&clk_sysin>; | |
152 | ||
153 | clock-output-names = "clk-s-c0-pll1-odf-0"; | |
154 | }; | |
155 | ||
156 | clk_s_c0_flexgen: clk-s-c0-flexgen { | |
157 | #clock-cells = <1>; | |
158 | compatible = "st,flexgen"; | |
159 | ||
160 | clocks = <&clk_s_c0_pll0 0>, | |
161 | <&clk_s_c0_pll1 0>, | |
162 | <&clk_s_c0_quadfs 0>, | |
163 | <&clk_s_c0_quadfs 1>, | |
164 | <&clk_s_c0_quadfs 2>, | |
165 | <&clk_s_c0_quadfs 3>, | |
166 | <&clk_sysin>; | |
167 | ||
168 | clock-output-names = "clk-icn-gpu", | |
169 | "clk-fdma", | |
170 | "clk-nand", | |
171 | "clk-hva", | |
172 | "clk-proc-stfe", | |
173 | "clk-proc-tp", | |
174 | "clk-rx-icn-dmu", | |
175 | "clk-rx-icn-hva", | |
176 | "clk-icn-cpu", | |
177 | "clk-tx-icn-dmu", | |
178 | "clk-mmc-0", | |
179 | "clk-mmc-1", | |
180 | "clk-jpegdec", | |
181 | "clk-ext2fa9", | |
182 | "clk-ic-bdisp-0", | |
183 | "clk-ic-bdisp-1", | |
184 | "clk-pp-dmu", | |
185 | "clk-vid-dmu", | |
186 | "clk-dss-lpc", | |
187 | "clk-st231-aud-0", | |
188 | "clk-st231-gp-1", | |
189 | "clk-st231-dmu", | |
190 | "clk-icn-lmi", | |
191 | "clk-tx-icn-disp-1", | |
192 | "clk-icn-sbc", | |
193 | "clk-stfe-frc2", | |
194 | "clk-eth-phy", | |
195 | "clk-eth-ref-phyclk", | |
196 | "clk-flash-promip", | |
197 | "clk-main-disp", | |
198 | "clk-aux-disp", | |
199 | "clk-compo-dvp", | |
200 | "clk-tx-icn-hades", | |
201 | "clk-rx-icn-hades", | |
202 | "clk-icn-reg-16", | |
203 | "clk-pp-hades", | |
204 | "clk-clust-hades", | |
205 | "clk-hwpe-hades", | |
206 | "clk-fc-hades"; | |
207 | }; | |
208 | }; | |
209 | ||
210 | clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 { | |
211 | #clock-cells = <1>; | |
212 | compatible = "st,stih407-quadfs660-D", "st,quadfs"; | |
213 | reg = <0x9104000 0x1000>; | |
214 | ||
215 | clocks = <&clk_sysin>; | |
216 | ||
217 | clock-output-names = "clk-s-d0-fs0-ch0", | |
218 | "clk-s-d0-fs0-ch1", | |
219 | "clk-s-d0-fs0-ch2", | |
220 | "clk-s-d0-fs0-ch3"; | |
221 | }; | |
222 | ||
223 | clockgen-d0@09104000 { | |
224 | compatible = "st,clkgen-c32"; | |
225 | reg = <0x9104000 0x1000>; | |
226 | ||
227 | clk_s_d0_flexgen: clk-s-d0-flexgen { | |
228 | #clock-cells = <1>; | |
229 | compatible = "st,flexgen"; | |
230 | ||
231 | clocks = <&clk_s_d0_quadfs 0>, | |
232 | <&clk_s_d0_quadfs 1>, | |
233 | <&clk_s_d0_quadfs 2>, | |
234 | <&clk_s_d0_quadfs 3>, | |
235 | <&clk_sysin>; | |
236 | ||
237 | clock-output-names = "clk-pcm-0", | |
238 | "clk-pcm-1", | |
239 | "clk-pcm-2", | |
240 | "clk-spdiff", | |
241 | "clk-pcmr10-master", | |
242 | "clk-usb2-phy"; | |
243 | }; | |
244 | }; | |
245 | ||
246 | clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 { | |
247 | #clock-cells = <1>; | |
248 | compatible = "st,stih407-quadfs660-D", "st,quadfs"; | |
249 | reg = <0x9106000 0x1000>; | |
250 | ||
251 | clocks = <&clk_sysin>; | |
252 | ||
253 | clock-output-names = "clk-s-d2-fs0-ch0", | |
254 | "clk-s-d2-fs0-ch1", | |
255 | "clk-s-d2-fs0-ch2", | |
256 | "clk-s-d2-fs0-ch3"; | |
257 | }; | |
258 | ||
259 | clk_tmdsout_hdmi: clk-tmdsout-hdmi { | |
260 | #clock-cells = <0>; | |
261 | compatible = "fixed-clock"; | |
262 | clock-frequency = <0>; | |
263 | }; | |
264 | ||
265 | clockgen-d2@x9106000 { | |
266 | compatible = "st,clkgen-c32"; | |
267 | reg = <0x9106000 0x1000>; | |
268 | ||
269 | clk_s_d2_flexgen: clk-s-d2-flexgen { | |
270 | #clock-cells = <1>; | |
271 | compatible = "st,flexgen"; | |
272 | ||
273 | clocks = <&clk_s_d2_quadfs 0>, | |
274 | <&clk_s_d2_quadfs 1>, | |
275 | <&clk_s_d2_quadfs 2>, | |
276 | <&clk_s_d2_quadfs 3>, | |
277 | <&clk_sysin>, | |
278 | <&clk_sysin>, | |
279 | <&clk_tmdsout_hdmi>; | |
280 | ||
281 | clock-output-names = "clk-pix-main-disp", | |
282 | "clk-pix-pip", | |
283 | "clk-pix-gdp1", | |
284 | "clk-pix-gdp2", | |
285 | "clk-pix-gdp3", | |
286 | "clk-pix-gdp4", | |
287 | "clk-pix-aux-disp", | |
288 | "clk-denc", | |
289 | "clk-pix-hddac", | |
290 | "clk-hddac", | |
291 | "clk-sddac", | |
292 | "clk-pix-dvo", | |
293 | "clk-dvo", | |
294 | "clk-pix-hdmi", | |
295 | "clk-tmds-hdmi", | |
296 | "clk-ref-hdmiphy"; | |
297 | }; | |
298 | }; | |
299 | ||
300 | clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 { | |
301 | #clock-cells = <1>; | |
302 | compatible = "st,stih407-quadfs660-D", "st,quadfs"; | |
303 | reg = <0x9107000 0x1000>; | |
304 | ||
305 | clocks = <&clk_sysin>; | |
306 | ||
307 | clock-output-names = "clk-s-d3-fs0-ch0", | |
308 | "clk-s-d3-fs0-ch1", | |
309 | "clk-s-d3-fs0-ch2", | |
310 | "clk-s-d3-fs0-ch3"; | |
311 | }; | |
312 | ||
313 | clockgen-d3@9107000 { | |
314 | compatible = "st,clkgen-c32"; | |
315 | reg = <0x9107000 0x1000>; | |
316 | ||
317 | clk_s_d3_flexgen: clk-s-d3-flexgen { | |
318 | #clock-cells = <1>; | |
319 | compatible = "st,flexgen"; | |
320 | ||
321 | clocks = <&clk_s_d3_quadfs 0>, | |
322 | <&clk_s_d3_quadfs 1>, | |
323 | <&clk_s_d3_quadfs 2>, | |
324 | <&clk_s_d3_quadfs 3>, | |
325 | <&clk_sysin>; | |
326 | ||
327 | clock-output-names = "clk-stfe-frc1", | |
328 | "clk-tsout-0", | |
329 | "clk-tsout-1", | |
330 | "clk-mchi", | |
331 | "clk-vsens-compo", | |
332 | "clk-frc1-remote", | |
333 | "clk-lpc-0", | |
334 | "clk-lpc-1"; | |
335 | }; | |
336 | }; | |
337 | }; | |
338 | }; |