Commit | Line | Data |
---|---|---|
65ebcc11 SK |
1 | /* |
2 | * Copyright (C) 2013 STMicroelectronics (R&D) Limited. | |
3 | * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * publishhed by the Free Software Foundation. | |
8 | */ | |
9 | #include "st-pincfg.h" | |
10 | / { | |
11 | ||
12 | aliases { | |
13 | gpio0 = &PIO0; | |
14 | gpio1 = &PIO1; | |
15 | gpio2 = &PIO2; | |
16 | gpio3 = &PIO3; | |
17 | gpio4 = &PIO4; | |
18 | gpio5 = &PIO5; | |
19 | gpio6 = &PIO6; | |
20 | gpio7 = &PIO7; | |
21 | gpio8 = &PIO8; | |
22 | gpio9 = &PIO9; | |
23 | gpio10 = &PIO10; | |
24 | gpio11 = &PIO11; | |
25 | gpio12 = &PIO12; | |
26 | gpio13 = &PIO13; | |
27 | gpio14 = &PIO14; | |
28 | gpio15 = &PIO15; | |
29 | gpio16 = &PIO16; | |
30 | gpio17 = &PIO17; | |
31 | gpio18 = &PIO18; | |
32 | gpio19 = &PIO100; | |
33 | gpio20 = &PIO101; | |
34 | gpio21 = &PIO102; | |
35 | gpio22 = &PIO103; | |
36 | gpio23 = &PIO104; | |
37 | gpio24 = &PIO105; | |
38 | gpio25 = &PIO106; | |
39 | gpio26 = &PIO107; | |
40 | }; | |
41 | ||
42 | soc { | |
43 | pin-controller-sbc { | |
44 | #address-cells = <1>; | |
45 | #size-cells = <1>; | |
46 | compatible = "st,stih415-sbc-pinctrl"; | |
47 | st,syscfg = <&syscfg_sbc>; | |
48 | ranges = <0 0xfe610000 0x5000>; | |
49 | ||
50 | PIO0: gpio@fe610000 { | |
51 | gpio-controller; | |
52 | #gpio-cells = <1>; | |
53 | reg = <0 0x100>; | |
54 | st,bank-name = "PIO0"; | |
55 | }; | |
56 | PIO1: gpio@fe611000 { | |
57 | gpio-controller; | |
58 | #gpio-cells = <1>; | |
59 | reg = <0x1000 0x100>; | |
60 | st,bank-name = "PIO1"; | |
61 | }; | |
62 | PIO2: gpio@fe612000 { | |
63 | gpio-controller; | |
64 | #gpio-cells = <1>; | |
65 | reg = <0x2000 0x100>; | |
66 | st,bank-name = "PIO2"; | |
67 | }; | |
68 | PIO3: gpio@fe613000 { | |
69 | gpio-controller; | |
70 | #gpio-cells = <1>; | |
71 | reg = <0x3000 0x100>; | |
72 | st,bank-name = "PIO3"; | |
73 | }; | |
74 | PIO4: gpio@fe614000 { | |
75 | gpio-controller; | |
76 | #gpio-cells = <1>; | |
77 | reg = <0x4000 0x100>; | |
78 | st,bank-name = "PIO4"; | |
79 | }; | |
80 | ||
81 | sbc_serial1 { | |
82 | pinctrl_sbc_serial1:sbc_serial1 { | |
83 | st,pins { | |
84 | tx = <&PIO2 6 ALT3 OUT>; | |
85 | rx = <&PIO2 7 ALT3 IN>; | |
86 | }; | |
87 | }; | |
88 | }; | |
89 | }; | |
90 | ||
91 | pin-controller-front { | |
92 | #address-cells = <1>; | |
93 | #size-cells = <1>; | |
94 | compatible = "st,stih415-front-pinctrl"; | |
95 | st,syscfg = <&syscfg_front>; | |
96 | ranges = <0 0xfee00000 0x8000>; | |
97 | ||
98 | PIO5: gpio@fee00000 { | |
99 | gpio-controller; | |
100 | #gpio-cells = <1>; | |
101 | reg = <0 0x100>; | |
102 | st,bank-name = "PIO5"; | |
103 | }; | |
104 | PIO6: gpio@fee01000 { | |
105 | gpio-controller; | |
106 | #gpio-cells = <1>; | |
107 | reg = <0x1000 0x100>; | |
108 | st,bank-name = "PIO6"; | |
109 | }; | |
110 | PIO7: gpio@fee02000 { | |
111 | gpio-controller; | |
112 | #gpio-cells = <1>; | |
113 | reg = <0x2000 0x100>; | |
114 | st,bank-name = "PIO7"; | |
115 | }; | |
116 | PIO8: gpio@fee03000 { | |
117 | gpio-controller; | |
118 | #gpio-cells = <1>; | |
119 | reg = <0x3000 0x100>; | |
120 | st,bank-name = "PIO8"; | |
121 | }; | |
122 | PIO9: gpio@fee04000 { | |
123 | gpio-controller; | |
124 | #gpio-cells = <1>; | |
125 | reg = <0x4000 0x100>; | |
126 | st,bank-name = "PIO9"; | |
127 | }; | |
128 | PIO10: gpio@fee05000 { | |
129 | gpio-controller; | |
130 | #gpio-cells = <1>; | |
131 | reg = <0x5000 0x100>; | |
132 | st,bank-name = "PIO10"; | |
133 | }; | |
134 | PIO11: gpio@fee06000 { | |
135 | gpio-controller; | |
136 | #gpio-cells = <1>; | |
137 | reg = <0x6000 0x100>; | |
138 | st,bank-name = "PIO11"; | |
139 | }; | |
140 | PIO12: gpio@fee07000 { | |
141 | gpio-controller; | |
142 | #gpio-cells = <1>; | |
143 | reg = <0x7000 0x100>; | |
144 | st,bank-name = "PIO12"; | |
145 | }; | |
146 | }; | |
147 | ||
148 | pin-controller-rear { | |
149 | #address-cells = <1>; | |
150 | #size-cells = <1>; | |
151 | compatible = "st,stih415-rear-pinctrl"; | |
152 | st,syscfg = <&syscfg_rear>; | |
153 | ranges = <0 0xfe820000 0x8000>; | |
154 | ||
155 | PIO13: gpio@fe820000 { | |
156 | gpio-controller; | |
157 | #gpio-cells = <1>; | |
158 | reg = <0 0x100>; | |
159 | st,bank-name = "PIO13"; | |
160 | }; | |
161 | PIO14: gpio@fe821000 { | |
162 | gpio-controller; | |
163 | #gpio-cells = <1>; | |
164 | reg = <0x1000 0x100>; | |
165 | st,bank-name = "PIO14"; | |
166 | }; | |
167 | PIO15: gpio@fe822000 { | |
168 | gpio-controller; | |
169 | #gpio-cells = <1>; | |
170 | reg = <0x2000 0x100>; | |
171 | st,bank-name = "PIO15"; | |
172 | }; | |
173 | PIO16: gpio@fe823000 { | |
174 | gpio-controller; | |
175 | #gpio-cells = <1>; | |
176 | reg = <0x3000 0x100>; | |
177 | st,bank-name = "PIO16"; | |
178 | }; | |
179 | PIO17: gpio@fe824000 { | |
180 | gpio-controller; | |
181 | #gpio-cells = <1>; | |
182 | reg = <0x4000 0x100>; | |
183 | st,bank-name = "PIO17"; | |
184 | }; | |
185 | PIO18: gpio@fe825000 { | |
186 | gpio-controller; | |
187 | #gpio-cells = <1>; | |
188 | reg = <0x5000 0x100>; | |
189 | st,bank-name = "PIO18"; | |
190 | }; | |
191 | ||
192 | serial2 { | |
193 | pinctrl_serial2: serial2-0 { | |
194 | st,pins { | |
195 | tx = <&PIO17 4 ALT2 OUT>; | |
196 | rx = <&PIO17 5 ALT2 IN>; | |
197 | }; | |
198 | }; | |
199 | }; | |
200 | }; | |
201 | ||
202 | pin-controller-left { | |
203 | #address-cells = <1>; | |
204 | #size-cells = <1>; | |
205 | compatible = "st,stih415-left-pinctrl"; | |
206 | st,syscfg = <&syscfg_left>; | |
207 | ranges = <0 0xfd6b0000 0x3000>; | |
208 | ||
209 | PIO100: gpio@fd6b0000 { | |
210 | gpio-controller; | |
211 | #gpio-cells = <1>; | |
212 | reg = <0 0x100>; | |
213 | st,bank-name = "PIO100"; | |
214 | }; | |
215 | PIO101: gpio@fd6b1000 { | |
216 | gpio-controller; | |
217 | #gpio-cells = <1>; | |
218 | reg = <0x1000 0x100>; | |
219 | st,bank-name = "PIO101"; | |
220 | }; | |
221 | PIO102: gpio@fd6b2000 { | |
222 | gpio-controller; | |
223 | #gpio-cells = <1>; | |
224 | reg = <0x2000 0x100>; | |
225 | st,bank-name = "PIO102"; | |
226 | }; | |
227 | }; | |
228 | ||
229 | pin-controller-right { | |
230 | #address-cells = <1>; | |
231 | #size-cells = <1>; | |
232 | compatible = "st,stih415-right-pinctrl"; | |
233 | st,syscfg = <&syscfg_right>; | |
234 | ranges = <0 0xfd330000 0x5000>; | |
235 | ||
236 | PIO103: gpio@fd330000 { | |
237 | gpio-controller; | |
238 | #gpio-cells = <1>; | |
239 | reg = <0 0x100>; | |
240 | st,bank-name = "PIO103"; | |
241 | }; | |
242 | PIO104: gpio@fd331000 { | |
243 | gpio-controller; | |
244 | #gpio-cells = <1>; | |
245 | reg = <0x1000 0x100>; | |
246 | st,bank-name = "PIO104"; | |
247 | }; | |
248 | PIO105: gpio@fd332000 { | |
249 | gpio-controller; | |
250 | #gpio-cells = <1>; | |
251 | reg = <0x2000 0x100>; | |
252 | st,bank-name = "PIO105"; | |
253 | }; | |
254 | PIO106: gpio@fd333000 { | |
255 | gpio-controller; | |
256 | #gpio-cells = <1>; | |
257 | reg = <0x3000 0x100>; | |
258 | st,bank-name = "PIO106"; | |
259 | }; | |
260 | PIO107: gpio@fd334000 { | |
261 | gpio-controller; | |
262 | #gpio-cells = <1>; | |
263 | reg = <0x4000 0x100>; | |
264 | st,bank-name = "PIO107"; | |
265 | }; | |
266 | }; | |
267 | }; | |
268 | }; |