Commit | Line | Data |
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15969b45 SK |
1 | |
2 | /* | |
3 | * Copyright (C) 2013 STMicroelectronics Limited. | |
4 | * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * publishhed by the Free Software Foundation. | |
9 | */ | |
10 | #include "st-pincfg.h" | |
11 | / { | |
12 | ||
13 | aliases { | |
14 | gpio0 = &PIO0; | |
15 | gpio1 = &PIO1; | |
16 | gpio2 = &PIO2; | |
17 | gpio3 = &PIO3; | |
18 | gpio4 = &PIO4; | |
19 | gpio5 = &PIO40; | |
20 | gpio6 = &PIO5; | |
21 | gpio7 = &PIO6; | |
22 | gpio8 = &PIO7; | |
23 | gpio9 = &PIO8; | |
24 | gpio10 = &PIO9; | |
25 | gpio11 = &PIO10; | |
26 | gpio12 = &PIO11; | |
27 | gpio13 = &PIO12; | |
28 | gpio14 = &PIO30; | |
29 | gpio15 = &PIO31; | |
30 | gpio16 = &PIO13; | |
31 | gpio17 = &PIO14; | |
32 | gpio18 = &PIO15; | |
33 | gpio19 = &PIO16; | |
34 | gpio20 = &PIO17; | |
35 | gpio21 = &PIO18; | |
36 | gpio22 = &PIO100; | |
37 | gpio23 = &PIO101; | |
38 | gpio24 = &PIO102; | |
39 | gpio25 = &PIO103; | |
40 | gpio26 = &PIO104; | |
41 | gpio27 = &PIO105; | |
42 | gpio28 = &PIO106; | |
43 | gpio29 = &PIO107; | |
44 | }; | |
45 | ||
46 | soc { | |
47 | pin-controller-sbc { | |
48 | #address-cells = <1>; | |
49 | #size-cells = <1>; | |
50 | compatible = "st,stih416-sbc-pinctrl"; | |
51 | st,syscfg = <&syscfg_sbc>; | |
52 | ranges = <0 0xfe610000 0x6000>; | |
53 | ||
54 | PIO0: gpio@fe610000 { | |
55 | gpio-controller; | |
56 | #gpio-cells = <1>; | |
57 | reg = <0 0x100>; | |
58 | st,bank-name = "PIO0"; | |
59 | }; | |
60 | PIO1: gpio@fe611000 { | |
61 | gpio-controller; | |
62 | #gpio-cells = <1>; | |
63 | reg = <0x1000 0x100>; | |
64 | st,bank-name = "PIO1"; | |
65 | }; | |
66 | PIO2: gpio@fe612000 { | |
67 | gpio-controller; | |
68 | #gpio-cells = <1>; | |
69 | reg = <0x2000 0x100>; | |
70 | st,bank-name = "PIO2"; | |
71 | }; | |
72 | PIO3: gpio@fe613000 { | |
73 | gpio-controller; | |
74 | #gpio-cells = <1>; | |
75 | reg = <0x3000 0x100>; | |
76 | st,bank-name = "PIO3"; | |
77 | }; | |
78 | PIO4: gpio@fe614000 { | |
79 | gpio-controller; | |
80 | #gpio-cells = <1>; | |
81 | reg = <0x4000 0x100>; | |
82 | st,bank-name = "PIO4"; | |
83 | }; | |
84 | PIO40: gpio@fe615000 { | |
85 | gpio-controller; | |
86 | #gpio-cells = <1>; | |
87 | reg = <0x5000 0x100>; | |
88 | st,bank-name = "PIO40"; | |
89 | st,retime-pin-mask = <0x7f>; | |
90 | }; | |
91 | ||
92 | sbc_serial1 { | |
93 | pinctrl_sbc_serial1: sbc_serial1 { | |
94 | st,pins { | |
95 | tx = <&PIO2 6 ALT3 OUT>; | |
96 | rx = <&PIO2 7 ALT3 IN>; | |
97 | }; | |
98 | }; | |
99 | }; | |
100 | }; | |
101 | ||
102 | pin-controller-front { | |
103 | #address-cells = <1>; | |
104 | #size-cells = <1>; | |
105 | compatible = "st,stih416-front-pinctrl"; | |
106 | st,syscfg = <&syscfg_front>; | |
107 | ranges = <0 0xfee00000 0x10000>; | |
108 | ||
109 | PIO5: gpio@fee00000 { | |
110 | gpio-controller; | |
111 | #gpio-cells = <1>; | |
112 | reg = <0 0x100>; | |
113 | st,bank-name = "PIO5"; | |
114 | }; | |
115 | PIO6: gpio@fee01000 { | |
116 | gpio-controller; | |
117 | #gpio-cells = <1>; | |
118 | reg = <0x1000 0x100>; | |
119 | st,bank-name = "PIO6"; | |
120 | }; | |
121 | PIO7: gpio@fee02000 { | |
122 | gpio-controller; | |
123 | #gpio-cells = <1>; | |
124 | reg = <0x2000 0x100>; | |
125 | st,bank-name = "PIO7"; | |
126 | }; | |
127 | PIO8: gpio@fee03000 { | |
128 | gpio-controller; | |
129 | #gpio-cells = <1>; | |
130 | reg = <0x3000 0x100>; | |
131 | st,bank-name = "PIO8"; | |
132 | }; | |
133 | PIO9: gpio@fee04000 { | |
134 | gpio-controller; | |
135 | #gpio-cells = <1>; | |
136 | reg = <0x4000 0x100>; | |
137 | st,bank-name = "PIO9"; | |
138 | }; | |
139 | PIO10: gpio@fee05000 { | |
140 | gpio-controller; | |
141 | #gpio-cells = <1>; | |
142 | reg = <0x5000 0x100>; | |
143 | st,bank-name = "PIO10"; | |
144 | }; | |
145 | PIO11: gpio@fee06000 { | |
146 | gpio-controller; | |
147 | #gpio-cells = <1>; | |
148 | reg = <0x6000 0x100>; | |
149 | st,bank-name = "PIO11"; | |
150 | }; | |
151 | PIO12: gpio@fee07000 { | |
152 | gpio-controller; | |
153 | #gpio-cells = <1>; | |
154 | reg = <0x7000 0x100>; | |
155 | st,bank-name = "PIO12"; | |
156 | }; | |
157 | PIO30: gpio@fee08000 { | |
158 | gpio-controller; | |
159 | #gpio-cells = <1>; | |
160 | reg = <0x8000 0x100>; | |
161 | st,bank-name = "PIO30"; | |
162 | }; | |
163 | PIO31: gpio@fee09000 { | |
164 | gpio-controller; | |
165 | #gpio-cells = <1>; | |
166 | reg = <0x9000 0x100>; | |
167 | st,bank-name = "PIO31"; | |
168 | }; | |
169 | }; | |
170 | ||
171 | pin-controller-rear { | |
172 | #address-cells = <1>; | |
173 | #size-cells = <1>; | |
174 | compatible = "st,stih416-rear-pinctrl"; | |
175 | st,syscfg = <&syscfg_rear>; | |
176 | ranges = <0 0xfe820000 0x6000>; | |
177 | ||
178 | PIO13: gpio@fe820000 { | |
179 | gpio-controller; | |
180 | #gpio-cells = <1>; | |
181 | reg = <0 0x100>; | |
182 | st,bank-name = "PIO13"; | |
183 | }; | |
184 | PIO14: gpio@fe821000 { | |
185 | gpio-controller; | |
186 | #gpio-cells = <1>; | |
187 | reg = <0x1000 0x100>; | |
188 | st,bank-name = "PIO14"; | |
189 | }; | |
190 | PIO15: gpio@fe822000 { | |
191 | gpio-controller; | |
192 | #gpio-cells = <1>; | |
193 | reg = <0x2000 0x100>; | |
194 | st,bank-name = "PIO15"; | |
195 | }; | |
196 | PIO16: gpio@fe823000 { | |
197 | gpio-controller; | |
198 | #gpio-cells = <1>; | |
199 | reg = <0x3000 0x100>; | |
200 | st,bank-name = "PIO16"; | |
201 | }; | |
202 | PIO17: gpio@fe824000 { | |
203 | gpio-controller; | |
204 | #gpio-cells = <1>; | |
205 | reg = <0x4000 0x100>; | |
206 | st,bank-name = "PIO17"; | |
207 | }; | |
208 | PIO18: gpio@fe825000 { | |
209 | gpio-controller; | |
210 | #gpio-cells = <1>; | |
211 | reg = <0x5000 0x100>; | |
212 | st,bank-name = "PIO18"; | |
213 | st,retime-pin-mask = <0xf>; | |
214 | }; | |
215 | ||
216 | serial2 { | |
217 | pinctrl_serial2: serial2-0 { | |
218 | st,pins { | |
219 | tx = <&PIO17 4 ALT2 OUT>; | |
220 | rx = <&PIO17 5 ALT2 IN>; | |
221 | output-enable = <&PIO11 3 ALT2 OUT>; | |
222 | }; | |
223 | }; | |
224 | }; | |
225 | }; | |
226 | ||
227 | pin-controller-fvdp-fe { | |
228 | #address-cells = <1>; | |
229 | #size-cells = <1>; | |
230 | compatible = "st,stih416-fvdp-fe-pinctrl"; | |
231 | st,syscfg = <&syscfg_fvdp_fe>; | |
232 | ranges = <0 0xfd6b0000 0x3000>; | |
233 | ||
234 | PIO100: gpio@fd6b0000 { | |
235 | gpio-controller; | |
236 | #gpio-cells = <1>; | |
237 | reg = <0 0x100>; | |
238 | st,bank-name = "PIO100"; | |
239 | }; | |
240 | PIO101: gpio@fd6b1000 { | |
241 | gpio-controller; | |
242 | #gpio-cells = <1>; | |
243 | reg = <0x1000 0x100>; | |
244 | st,bank-name = "PIO101"; | |
245 | }; | |
246 | PIO102: gpio@fd6b2000 { | |
247 | gpio-controller; | |
248 | #gpio-cells = <1>; | |
249 | reg = <0x2000 0x100>; | |
250 | st,bank-name = "PIO102"; | |
251 | }; | |
252 | }; | |
253 | ||
254 | pin-controller-fvdp-lite { | |
255 | #address-cells = <1>; | |
256 | #size-cells = <1>; | |
257 | compatible = "st,stih416-fvdp-lite-pinctrl"; | |
258 | st,syscfg = <&syscfg_fvdp_lite>; | |
259 | ranges = <0 0xfd330000 0x5000>; | |
260 | ||
261 | PIO103: gpio@fd330000 { | |
262 | gpio-controller; | |
263 | #gpio-cells = <1>; | |
264 | reg = <0 0x100>; | |
265 | st,bank-name = "PIO103"; | |
266 | }; | |
267 | PIO104: gpio@fd331000 { | |
268 | gpio-controller; | |
269 | #gpio-cells = <1>; | |
270 | reg = <0x1000 0x100>; | |
271 | st,bank-name = "PIO104"; | |
272 | }; | |
273 | PIO105: gpio@fd332000 { | |
274 | gpio-controller; | |
275 | #gpio-cells = <1>; | |
276 | reg = <0x2000 0x100>; | |
277 | st,bank-name = "PIO105"; | |
278 | }; | |
279 | PIO106: gpio@fd333000 { | |
280 | gpio-controller; | |
281 | #gpio-cells = <1>; | |
282 | reg = <0x3000 0x100>; | |
283 | st,bank-name = "PIO106"; | |
284 | }; | |
285 | ||
286 | PIO107: gpio@fd334000 { | |
287 | gpio-controller; | |
288 | #gpio-cells = <1>; | |
289 | reg = <0x4000 0x100>; | |
290 | st,bank-name = "PIO107"; | |
291 | st,retime-pin-mask = <0xf>; | |
292 | }; | |
293 | }; | |
294 | }; | |
295 | }; |