[deliverable/linux.git] / arch / arm / boot / dts / stm32f429.dtsi

/*
 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 *     You should have received a copy of the GNU General Public
 *     License along with this file; if not, write to the Free
 *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
 *     MA 02110-1301 USA
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include "armv7-m.dtsi"
#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>

/ {
	clocks {
		clk_hse: clk-hse {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <0>;
		};
	};

	soc {
		dma-ranges = <0xc0000000 0x0 0x10000000>;

		timer2: timer@40000000 {
			compatible = "st,stm32-timer";
			reg = <0x40000000 0x400>;
			interrupts = <28>;
			clocks = <&rcc 0 128>;
			status = "disabled";
		};

		timer3: timer@40000400 {
			compatible = "st,stm32-timer";
			reg = <0x40000400 0x400>;
			interrupts = <29>;
			clocks = <&rcc 0 129>;
			status = "disabled";
		};

		timer4: timer@40000800 {
			compatible = "st,stm32-timer";
			reg = <0x40000800 0x400>;
			interrupts = <30>;
			clocks = <&rcc 0 130>;
			status = "disabled";
		};

		timer5: timer@40000c00 {
			compatible = "st,stm32-timer";
			reg = <0x40000c00 0x400>;
			interrupts = <50>;
			clocks = <&rcc 0 131>;
		};

		timer6: timer@40001000 {
			compatible = "st,stm32-timer";
			reg = <0x40001000 0x400>;
			interrupts = <54>;
			clocks = <&rcc 0 132>;
			status = "disabled";
		};

		timer7: timer@40001400 {
			compatible = "st,stm32-timer";
			reg = <0x40001400 0x400>;
			interrupts = <55>;
			clocks = <&rcc 0 133>;
			status = "disabled";
		};

		usart2: serial@40004400 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40004400 0x400>;
			interrupts = <38>;
			clocks =  <&rcc 0 145>;
			status = "disabled";
		};

		usart3: serial@40004800 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40004800 0x400>;
			interrupts = <39>;
			clocks = <&rcc 0 146>;
			status = "disabled";
		};

		usart4: serial@40004c00 {
			compatible = "st,stm32-uart";
			reg = <0x40004c00 0x400>;
			interrupts = <52>;
			clocks = <&rcc 0 147>;
			status = "disabled";
		};

		usart5: serial@40005000 {
			compatible = "st,stm32-uart";
			reg = <0x40005000 0x400>;
			interrupts = <53>;
			clocks = <&rcc 0 148>;
			status = "disabled";
		};

		usart7: serial@40007800 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40007800 0x400>;
			interrupts = <82>;
			clocks = <&rcc 0 158>;
			status = "disabled";
		};

		usart8: serial@40007c00 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40007c00 0x400>;
			interrupts = <83>;
			clocks = <&rcc 0 159>;
			status = "disabled";
		};

		usart1: serial@40011000 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40011000 0x400>;
			interrupts = <37>;
			clocks = <&rcc 0 164>;
			status = "disabled";
		};

		usart6: serial@40011400 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40011400 0x400>;
			interrupts = <71>;
			clocks = <&rcc 0 165>;
			status = "disabled";
		};

		pin-controller {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "st,stm32f429-pinctrl";
			ranges = <0 0x40020000 0x3000>;
			pins-are-numbered;

			gpioa: gpio@40020000 {
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x0 0x400>;
				clocks = <&rcc 0 0>;
				st,bank-name = "GPIOA";
			};

			gpiob: gpio@40020400 {
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x400 0x400>;
				clocks = <&rcc 0 1>;
				st,bank-name = "GPIOB";
			};

			gpioc: gpio@40020800 {
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x800 0x400>;
				clocks = <&rcc 0 2>;
				st,bank-name = "GPIOC";
			};

			gpiod: gpio@40020c00 {
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0xc00 0x400>;
				clocks = <&rcc 0 3>;
				st,bank-name = "GPIOD";
			};

			gpioe: gpio@40021000 {
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x1000 0x400>;
				clocks = <&rcc 0 4>;
				st,bank-name = "GPIOE";
			};

			gpiof: gpio@40021400 {
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x1400 0x400>;
				clocks = <&rcc 0 5>;
				st,bank-name = "GPIOF";
			};

			gpiog: gpio@40021800 {
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x1800 0x400>;
				clocks = <&rcc 0 6>;
				st,bank-name = "GPIOG";
			};

			gpioh: gpio@40021c00 {
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x1c00 0x400>;
				clocks = <&rcc 0 7>;
				st,bank-name = "GPIOH";
			};

			gpioi: gpio@40022000 {
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x2000 0x400>;
				clocks = <&rcc 0 8>;
				st,bank-name = "GPIOI";
			};

			gpioj: gpio@40022400 {
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x2400 0x400>;
				clocks = <&rcc 0 9>;
				st,bank-name = "GPIOJ";
			};

			gpiok: gpio@40022800 {
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x2800 0x400>;
				clocks = <&rcc 0 10>;
				st,bank-name = "GPIOK";
			};

			usart1_pins_a: usart1@0 {
				pins1 {
					pinmux = <STM32F429_PA9_FUNC_USART1_TX>;
					bias-disable;
					drive-push-pull;
					slew-rate = <0>;
				};
				pins2 {
					pinmux = <STM32F429_PA10_FUNC_USART1_RX>;
					bias-disable;
				};
			};

			usbotg_hs_pins_a: usbotg_hs@0 {
				pins {
					pinmux = <STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT>,
						 <STM32F429_PI11_FUNC_OTG_HS_ULPI_DIR>,
						 <STM32F429_PC0_FUNC_OTG_HS_ULPI_STP>,
						 <STM32F429_PA5_FUNC_OTG_HS_ULPI_CK>,
						 <STM32F429_PA3_FUNC_OTG_HS_ULPI_D0>,
						 <STM32F429_PB0_FUNC_OTG_HS_ULPI_D1>,
						 <STM32F429_PB1_FUNC_OTG_HS_ULPI_D2>,
						 <STM32F429_PB10_FUNC_OTG_HS_ULPI_D3>,
						 <STM32F429_PB11_FUNC_OTG_HS_ULPI_D4>,
						 <STM32F429_PB12_FUNC_OTG_HS_ULPI_D5>,
						 <STM32F429_PB13_FUNC_OTG_HS_ULPI_D6>,
						 <STM32F429_PB5_FUNC_OTG_HS_ULPI_D7>;
					bias-disable;
					drive-push-pull;
					slew-rate = <2>;
				};
			};
		};

		rcc: rcc@40023810 {
			#clock-cells = <2>;
			compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
			reg = <0x40023800 0x400>;
			clocks = <&clk_hse>;
		};

		dma1: dma-controller@40026000 {
			compatible = "st,stm32-dma";
			reg = <0x40026000 0x400>;
			interrupts = <11>,
				     <12>,
				     <13>,
				     <14>,
				     <15>,
				     <16>,
				     <17>,
				     <47>;
			clocks = <&rcc 0 21>;
			#dma-cells = <4>;
		};

		dma2: dma-controller@40026400 {
			compatible = "st,stm32-dma";
			reg = <0x40026400 0x400>;
			interrupts = <56>,
				     <57>,
				     <58>,
				     <59>,
				     <60>,
				     <68>,
				     <69>,
				     <70>;
			clocks = <&rcc 0 22>;
			#dma-cells = <4>;
			st,mem2mem;
		};

		usbotg_hs: usb@40040000 {
			compatible = "snps,dwc2";
			dma-ranges;
			reg = <0x40040000 0x40000>;
			interrupts = <77>;
			clocks = <&rcc 0 29>;
			clock-names = "otg";
			status = "disabled";
		};

		rng: rng@50060800 {
			compatible = "st,stm32-rng";
			reg = <0x50060800 0x400>;
			interrupts = <80>;
			clocks = <&rcc 0 38>;
		};
	};
};

&systick {
	clocks = <&rcc 1 0>;
	status = "okay";
};
Commit	Line	Data
338a6aaa MC	1	/*
	2	* Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
	3	*
	4	* This file is dual-licensed: you can use it either under the terms
	5	* of the GPL or the X11 license, at your option. Note that this dual
	6	* licensing only applies to this file, and not this project as a
	7	* whole.
	8	*
	9	* a) This file is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of the
	12	* License, or (at your option) any later version.
	13	*
	14	* This file is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public
	20	* License along with this file; if not, write to the Free
	21	* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
	22	* MA 02110-1301 USA
	23	*
	24	* Or, alternatively,
	25	*
	26	* b) Permission is hereby granted, free of charge, to any person
	27	* obtaining a copy of this software and associated documentation
	28	* files (the "Software"), to deal in the Software without
	29	* restriction, including without limitation the rights to use,
	30	* copy, modify, merge, publish, distribute, sublicense, and/or
	31	* sell copies of the Software, and to permit persons to whom the
	32	* Software is furnished to do so, subject to the following
	33	* conditions:
	34	*
	35	* The above copyright notice and this permission notice shall be
	36	* included in all copies or substantial portions of the Software.
	37	*
	38	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	39	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	40	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	41	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	42	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	43	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	44	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	45	* OTHER DEALINGS IN THE SOFTWARE.
	46	*/
	47
	48	#include "armv7-m.dtsi"
2dbd0593	49	#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
338a6aaa MC	50
	51	/ {
	52	clocks {
9dc24a2d	53	clk_hse: clk-hse {
338a6aaa MC	54	#clock-cells = <0>;
338a6aaa MC	55	compatible = "fixed-clock";
9dc24a2d	56	clock-frequency = <0>;
338a6aaa MC	57	};
	58	};
	59
	60	soc {
b2aa7f77 MC	61	dma-ranges = <0xc0000000 0x0 0x10000000>;
b2aa7f77 MC	62
338a6aaa MC	63	timer2: timer@40000000 {
	64	compatible = "st,stm32-timer";
	65	reg = <0x40000000 0x400>;
	66	interrupts = <28>;
9dc24a2d	67	clocks = <&rcc 0 128>;
338a6aaa MC	68	status = "disabled";
	69	};
	70
	71	timer3: timer@40000400 {
	72	compatible = "st,stm32-timer";
	73	reg = <0x40000400 0x400>;
	74	interrupts = <29>;
9dc24a2d	75	clocks = <&rcc 0 129>;
338a6aaa MC	76	status = "disabled";
	77	};
	78
	79	timer4: timer@40000800 {
	80	compatible = "st,stm32-timer";
	81	reg = <0x40000800 0x400>;
	82	interrupts = <30>;
9dc24a2d	83	clocks = <&rcc 0 130>;
338a6aaa MC	84	status = "disabled";
	85	};
	86
	87	timer5: timer@40000c00 {
	88	compatible = "st,stm32-timer";
	89	reg = <0x40000c00 0x400>;
	90	interrupts = <50>;
9dc24a2d	91	clocks = <&rcc 0 131>;
338a6aaa MC	92	};
	93
	94	timer6: timer@40001000 {
	95	compatible = "st,stm32-timer";
	96	reg = <0x40001000 0x400>;
	97	interrupts = <54>;
9dc24a2d	98	clocks = <&rcc 0 132>;
338a6aaa MC	99	status = "disabled";
	100	};
	101
	102	timer7: timer@40001400 {
	103	compatible = "st,stm32-timer";
	104	reg = <0x40001400 0x400>;
	105	interrupts = <55>;
9dc24a2d	106	clocks = <&rcc 0 133>;
338a6aaa MC	107	status = "disabled";
	108	};
	109
	110	usart2: serial@40004400 {
	111	compatible = "st,stm32-usart", "st,stm32-uart";
	112	reg = <0x40004400 0x400>;
	113	interrupts = <38>;
9dc24a2d	114	clocks = <&rcc 0 145>;
338a6aaa MC	115	status = "disabled";
	116	};
	117
	118	usart3: serial@40004800 {
	119	compatible = "st,stm32-usart", "st,stm32-uart";
	120	reg = <0x40004800 0x400>;
	121	interrupts = <39>;
9dc24a2d	122	clocks = <&rcc 0 146>;
338a6aaa MC	123	status = "disabled";
	124	};
	125
	126	usart4: serial@40004c00 {
	127	compatible = "st,stm32-uart";
	128	reg = <0x40004c00 0x400>;
	129	interrupts = <52>;
9dc24a2d	130	clocks = <&rcc 0 147>;
338a6aaa MC	131	status = "disabled";
	132	};
	133
	134	usart5: serial@40005000 {
	135	compatible = "st,stm32-uart";
	136	reg = <0x40005000 0x400>;
	137	interrupts = <53>;
9dc24a2d	138	clocks = <&rcc 0 148>;
338a6aaa MC	139	status = "disabled";
	140	};
	141
	142	usart7: serial@40007800 {
	143	compatible = "st,stm32-usart", "st,stm32-uart";
	144	reg = <0x40007800 0x400>;
	145	interrupts = <82>;
9dc24a2d	146	clocks = <&rcc 0 158>;
338a6aaa MC	147	status = "disabled";
	148	};
	149
	150	usart8: serial@40007c00 {
	151	compatible = "st,stm32-usart", "st,stm32-uart";
	152	reg = <0x40007c00 0x400>;
	153	interrupts = <83>;
9dc24a2d	154	clocks = <&rcc 0 159>;
338a6aaa MC	155	status = "disabled";
	156	};
	157
	158	usart1: serial@40011000 {
	159	compatible = "st,stm32-usart", "st,stm32-uart";
	160	reg = <0x40011000 0x400>;
	161	interrupts = <37>;
9dc24a2d	162	clocks = <&rcc 0 164>;
338a6aaa MC	163	status = "disabled";
	164	};
	165
	166	usart6: serial@40011400 {
	167	compatible = "st,stm32-usart", "st,stm32-uart";
	168	reg = <0x40011400 0x400>;
	169	interrupts = <71>;
9dc24a2d	170	clocks = <&rcc 0 165>;
338a6aaa MC	171	status = "disabled";
338a6aaa MC	172	};
9dc24a2d	173
2dbd0593 MC	174	pin-controller {
	175	#address-cells = <1>;
	176	#size-cells = <1>;
	177	compatible = "st,stm32f429-pinctrl";
	178	ranges = <0 0x40020000 0x3000>;
	179	pins-are-numbered;
	180
	181	gpioa: gpio@40020000 {
	182	gpio-controller;
	183	#gpio-cells = <2>;
	184	reg = <0x0 0x400>;
a985b66a	185	clocks = <&rcc 0 0>;
2dbd0593 MC	186	st,bank-name = "GPIOA";
	187	};
	188
	189	gpiob: gpio@40020400 {
	190	gpio-controller;
	191	#gpio-cells = <2>;
	192	reg = <0x400 0x400>;
a985b66a	193	clocks = <&rcc 0 1>;
2dbd0593 MC	194	st,bank-name = "GPIOB";
	195	};
	196
	197	gpioc: gpio@40020800 {
	198	gpio-controller;
	199	#gpio-cells = <2>;
	200	reg = <0x800 0x400>;
a985b66a	201	clocks = <&rcc 0 2>;
2dbd0593 MC	202	st,bank-name = "GPIOC";
	203	};
	204
	205	gpiod: gpio@40020c00 {
	206	gpio-controller;
	207	#gpio-cells = <2>;
	208	reg = <0xc00 0x400>;
a985b66a	209	clocks = <&rcc 0 3>;
2dbd0593 MC	210	st,bank-name = "GPIOD";
	211	};
	212
	213	gpioe: gpio@40021000 {
	214	gpio-controller;
	215	#gpio-cells = <2>;
	216	reg = <0x1000 0x400>;
a985b66a	217	clocks = <&rcc 0 4>;
2dbd0593 MC	218	st,bank-name = "GPIOE";
	219	};
	220
	221	gpiof: gpio@40021400 {
	222	gpio-controller;
	223	#gpio-cells = <2>;
	224	reg = <0x1400 0x400>;
a985b66a	225	clocks = <&rcc 0 5>;
2dbd0593 MC	226	st,bank-name = "GPIOF";
	227	};
	228
	229	gpiog: gpio@40021800 {
	230	gpio-controller;
	231	#gpio-cells = <2>;
	232	reg = <0x1800 0x400>;
a985b66a	233	clocks = <&rcc 0 6>;
2dbd0593 MC	234	st,bank-name = "GPIOG";
	235	};
	236
	237	gpioh: gpio@40021c00 {
	238	gpio-controller;
	239	#gpio-cells = <2>;
	240	reg = <0x1c00 0x400>;
a985b66a	241	clocks = <&rcc 0 7>;
2dbd0593 MC	242	st,bank-name = "GPIOH";
	243	};
	244
	245	gpioi: gpio@40022000 {
	246	gpio-controller;
	247	#gpio-cells = <2>;
	248	reg = <0x2000 0x400>;
a985b66a	249	clocks = <&rcc 0 8>;
2dbd0593 MC	250	st,bank-name = "GPIOI";
	251	};
	252
	253	gpioj: gpio@40022400 {
	254	gpio-controller;
	255	#gpio-cells = <2>;
	256	reg = <0x2400 0x400>;
a985b66a	257	clocks = <&rcc 0 9>;
2dbd0593 MC	258	st,bank-name = "GPIOJ";
	259	};
	260
	261	gpiok: gpio@40022800 {
	262	gpio-controller;
	263	#gpio-cells = <2>;
	264	reg = <0x2800 0x400>;
a985b66a	265	clocks = <&rcc 0 10>;
2dbd0593 MC	266	st,bank-name = "GPIOK";
2dbd0593 MC	267	};
521df6f5 MC	268
	269	usart1_pins_a: usart1@0 {
	270	pins1 {
	271	pinmux = <STM32F429_PA9_FUNC_USART1_TX>;
	272	bias-disable;
	273	drive-push-pull;
	274	slew-rate = <0>;
	275	};
	276	pins2 {
	277	pinmux = <STM32F429_PA10_FUNC_USART1_RX>;
	278	bias-disable;
	279	};
	280	};
c8cc1b72 MC	281
	282	usbotg_hs_pins_a: usbotg_hs@0 {
	283	pins {
	284	pinmux = <STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT>,
	285	<STM32F429_PI11_FUNC_OTG_HS_ULPI_DIR>,
	286	<STM32F429_PC0_FUNC_OTG_HS_ULPI_STP>,
	287	<STM32F429_PA5_FUNC_OTG_HS_ULPI_CK>,
	288	<STM32F429_PA3_FUNC_OTG_HS_ULPI_D0>,
	289	<STM32F429_PB0_FUNC_OTG_HS_ULPI_D1>,
	290	<STM32F429_PB1_FUNC_OTG_HS_ULPI_D2>,
	291	<STM32F429_PB10_FUNC_OTG_HS_ULPI_D3>,
	292	<STM32F429_PB11_FUNC_OTG_HS_ULPI_D4>,
	293	<STM32F429_PB12_FUNC_OTG_HS_ULPI_D5>,
	294	<STM32F429_PB13_FUNC_OTG_HS_ULPI_D6>,
	295	<STM32F429_PB5_FUNC_OTG_HS_ULPI_D7>;
	296	bias-disable;
	297	drive-push-pull;
	298	slew-rate = <2>;
	299	};
	300	};
2dbd0593 MC	301	};
2dbd0593 MC	302
9dc24a2d DT	303	rcc: rcc@40023810 {
	304	#clock-cells = <2>;
	305	compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
	306	reg = <0x40023800 0x400>;
	307	clocks = <&clk_hse>;
	308	};
b47c9fab	309
9ee9e281 CM	310	dma1: dma-controller@40026000 {
	311	compatible = "st,stm32-dma";
	312	reg = <0x40026000 0x400>;
	313	interrupts = <11>,
	314	<12>,
	315	<13>,
	316	<14>,
	317	<15>,
	318	<16>,
	319	<17>,
	320	<47>;
	321	clocks = <&rcc 0 21>;
	322	#dma-cells = <4>;
	323	};
	324
	325	dma2: dma-controller@40026400 {
	326	compatible = "st,stm32-dma";
	327	reg = <0x40026400 0x400>;
	328	interrupts = <56>,
	329	<57>,
	330	<58>,
	331	<59>,
	332	<60>,
	333	<68>,
	334	<69>,
	335	<70>;
	336	clocks = <&rcc 0 22>;
	337	#dma-cells = <4>;
	338	st,mem2mem;
	339	};
	340
c8cc1b72 MC	341	usbotg_hs: usb@40040000 {
	342	compatible = "snps,dwc2";
	343	dma-ranges;
	344	reg = <0x40040000 0x40000>;
	345	interrupts = <77>;
	346	clocks = <&rcc 0 29>;
	347	clock-names = "otg";
	348	status = "disabled";
	349	};
	350
b47c9fab DT	351	rng: rng@50060800 {
	352	compatible = "st,stm32-rng";
	353	reg = <0x50060800 0x400>;
	354	interrupts = <80>;
	355	clocks = <&rcc 0 38>;
	356	};
338a6aaa MC	357	};
	358	};
	359
	360	&systick {
9dc24a2d	361	clocks = <&rcc 1 0>;
338a6aaa MC	362	status = "okay";
338a6aaa MC	363	};