projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 7423d2d8 SR |
1 | /* |
| 2 | * Copyright 2012 Stefan Roese | |
| 3 | * Stefan Roese <sr@denx.de> | |
| 4 | * | |
| 033ba3d7 MR |
5 | * This file is dual-licensed: you can use it either under the terms |
| 6 | * of the GPL or the X11 license, at your option. Note that this dual | |
| 7 | * licensing only applies to this file, and not this project as a | |
| 8 | * whole. | |
| 7423d2d8 | 9 | * |
| 033ba3d7 MR |
10 | * a) This library is free software; you can redistribute it and/or |
| 11 | * modify it under the terms of the GNU General Public License as | |
| 12 | * published by the Free Software Foundation; either version 2 of the | |
| 13 | * License, or (at your option) any later version. | |
| 14 | * | |
| 15 | * This library is distributed in the hope that it will be useful, | |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 18 | * GNU General Public License for more details. | |
| 19 | * | |
| 033ba3d7 MR |
20 | * Or, alternatively, |
| 21 | * | |
| 22 | * b) Permission is hereby granted, free of charge, to any person | |
| 23 | * obtaining a copy of this software and associated documentation | |
| 24 | * files (the "Software"), to deal in the Software without | |
| 25 | * restriction, including without limitation the rights to use, | |
| 26 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
| 27 | * sell copies of the Software, and to permit persons to whom the | |
| 28 | * Software is furnished to do so, subject to the following | |
| 29 | * conditions: | |
| 30 | * | |
| 31 | * The above copyright notice and this permission notice shall be | |
| 32 | * included in all copies or substantial portions of the Software. | |
| 33 | * | |
| 34 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
| 35 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
| 36 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
| 37 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
| 38 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
| 39 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
| 40 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 41 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 7423d2d8 SR |
42 | */ |
| 43 | ||
| 71455701 | 44 | #include "skeleton.dtsi" |
| 7423d2d8 | 45 | |
| 541ce2ca CYT |
46 | #include <dt-bindings/thermal/thermal.h> |
| 47 | ||
| b516fa5d | 48 | #include <dt-bindings/clock/sun4i-a10-pll2.h> |
| 1f9f6a78 | 49 | #include <dt-bindings/dma/sun4i-a10.h> |
| 092a0c3b | 50 | #include <dt-bindings/pinctrl/sun4i-a10.h> |
| 7423d2d8 SR |
51 | |
| 52 | / { | |
| 69144e3b MR |
53 | interrupt-parent = <&intc>; |
| 54 | ||
| e751cce9 EL |
55 | aliases { |
| 56 | ethernet0 = &emac; | |
| 57 | }; | |
| 58 | ||
| 5790d4ee HG |
59 | chosen { |
| 60 | #address-cells = <1>; | |
| 61 | #size-cells = <1>; | |
| 62 | ranges; | |
| 63 | ||
| a9f8cda3 | 64 | framebuffer@0 { |
| d8cacaa3 MR |
65 | compatible = "allwinner,simple-framebuffer", |
| 66 | "simple-framebuffer"; | |
| a9f8cda3 | 67 | allwinner,pipeline = "de_be0-lcd0-hdmi"; |
| 678e75d3 | 68 | clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, |
| 82f8582f | 69 | <&ahb_gates 44>, <&dram_gates 26>; |
| 5790d4ee HG |
70 | status = "disabled"; |
| 71 | }; | |
| 8cedd662 HG |
72 | |
| 73 | framebuffer@1 { | |
| d8cacaa3 MR |
74 | compatible = "allwinner,simple-framebuffer", |
| 75 | "simple-framebuffer"; | |
| 8cedd662 HG |
76 | allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi"; |
| 77 | clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, | |
| 82f8582f CYT |
78 | <&ahb_gates 44>, <&ahb_gates 46>, |
| 79 | <&dram_gates 25>, <&dram_gates 26>; | |
| 8cedd662 HG |
80 | status = "disabled"; |
| 81 | }; | |
| fd18c7ea HG |
82 | |
| 83 | framebuffer@2 { | |
| 84 | compatible = "allwinner,simple-framebuffer", | |
| 85 | "simple-framebuffer"; | |
| 86 | allwinner,pipeline = "de_fe0-de_be0-lcd0"; | |
| 87 | clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>, | |
| 82f8582f CYT |
88 | <&ahb_gates 46>, <&dram_gates 25>, |
| 89 | <&dram_gates 26>; | |
| fd18c7ea HG |
90 | status = "disabled"; |
| 91 | }; | |
| 92 | ||
| 93 | framebuffer@3 { | |
| 94 | compatible = "allwinner,simple-framebuffer", | |
| 95 | "simple-framebuffer"; | |
| 96 | allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0"; | |
| 97 | clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>, | |
| 82f8582f | 98 | <&ahb_gates 44>, <&ahb_gates 46>, |
| bec38aaa | 99 | <&dram_gates 5>, <&dram_gates 25>, <&dram_gates 26>; |
| fd18c7ea HG |
100 | status = "disabled"; |
| 101 | }; | |
| 5790d4ee HG |
102 | }; |
| 103 | ||
| 69144e3b | 104 | cpus { |
| 8b2efa89 AB |
105 | #address-cells = <1>; |
| 106 | #size-cells = <0>; | |
| 7294be5d | 107 | cpu0: cpu@0 { |
| 14c44aa5 | 108 | device_type = "cpu"; |
| 69144e3b | 109 | compatible = "arm,cortex-a8"; |
| 14c44aa5 | 110 | reg = <0x0>; |
| 7294be5d CYT |
111 | clocks = <&cpu>; |
| 112 | clock-latency = <244144>; /* 8 32k periods */ | |
| 113 | operating-points = < | |
| 8358aada | 114 | /* kHz uV */ |
| 7294be5d | 115 | 1008000 1400000 |
| 8358aada MR |
116 | 912000 1350000 |
| 117 | 864000 1300000 | |
| 118 | 624000 1250000 | |
| 7294be5d CYT |
119 | >; |
| 120 | #cooling-cells = <2>; | |
| 121 | cooling-min-level = <0>; | |
| 370a9b5f | 122 | cooling-max-level = <3>; |
| 69144e3b MR |
123 | }; |
| 124 | }; | |
| 125 | ||
| 541ce2ca CYT |
126 | thermal-zones { |
| 127 | cpu_thermal { | |
| 128 | /* milliseconds */ | |
| 129 | polling-delay-passive = <250>; | |
| 130 | polling-delay = <1000>; | |
| 131 | thermal-sensors = <&rtp>; | |
| 132 | ||
| 133 | cooling-maps { | |
| 134 | map0 { | |
| 135 | trip = <&cpu_alert0>; | |
| 136 | cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 137 | }; | |
| 138 | }; | |
| 139 | ||
| 140 | trips { | |
| 141 | cpu_alert0: cpu_alert0 { | |
| 142 | /* milliCelsius */ | |
| 143 | temperature = <850000>; | |
| 144 | hysteresis = <2000>; | |
| 145 | type = "passive"; | |
| 146 | }; | |
| 147 | ||
| 148 | cpu_crit: cpu_crit { | |
| 149 | /* milliCelsius */ | |
| 150 | temperature = <100000>; | |
| 151 | hysteresis = <2000>; | |
| 152 | type = "critical"; | |
| 153 | }; | |
| 154 | }; | |
| 69144e3b MR |
155 | }; |
| 156 | }; | |
| 157 | ||
| 7423d2d8 SR |
158 | memory { |
| 159 | reg = <0x40000000 0x80000000>; | |
| 160 | }; | |
| 874b4e45 | 161 | |
| 69144e3b MR |
162 | clocks { |
| 163 | #address-cells = <1>; | |
| 164 | #size-cells = <1>; | |
| 165 | ranges; | |
| 166 | ||
| 167 | /* | |
| 168 | * This is a dummy clock, to be used as placeholder on | |
| 169 | * other mux clocks when a specific parent clock is not | |
| 170 | * yet implemented. It should be dropped when the driver | |
| 171 | * is complete. | |
| 172 | */ | |
| 173 | dummy: dummy { | |
| 174 | #clock-cells = <0>; | |
| 175 | compatible = "fixed-clock"; | |
| 176 | clock-frequency = <0>; | |
| 177 | }; | |
| 178 | ||
| dfb12c0c | 179 | osc24M: clk@01c20050 { |
| 69144e3b | 180 | #clock-cells = <0>; |
| bf6534a1 | 181 | compatible = "allwinner,sun4i-a10-osc-clk"; |
| 69144e3b | 182 | reg = <0x01c20050 0x4>; |
| 92fd6e06 | 183 | clock-frequency = <24000000>; |
| dfb12c0c | 184 | clock-output-names = "osc24M"; |
| 69144e3b MR |
185 | }; |
| 186 | ||
| be5f83ff PL |
187 | osc3M: osc3M_clk { |
| 188 | compatible = "fixed-factor-clock"; | |
| 189 | #clock-cells = <0>; | |
| 190 | clock-div = <8>; | |
| 191 | clock-mult = <1>; | |
| 192 | clocks = <&osc24M>; | |
| 193 | clock-output-names = "osc3M"; | |
| 194 | }; | |
| 195 | ||
| dfb12c0c | 196 | osc32k: clk@0 { |
| 69144e3b MR |
197 | #clock-cells = <0>; |
| 198 | compatible = "fixed-clock"; | |
| 199 | clock-frequency = <32768>; | |
| dfb12c0c | 200 | clock-output-names = "osc32k"; |
| 69144e3b MR |
201 | }; |
| 202 | ||
| dfb12c0c | 203 | pll1: clk@01c20000 { |
| 69144e3b | 204 | #clock-cells = <0>; |
| bf6534a1 | 205 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
| 69144e3b MR |
206 | reg = <0x01c20000 0x4>; |
| 207 | clocks = <&osc24M>; | |
| dfb12c0c | 208 | clock-output-names = "pll1"; |
| 69144e3b MR |
209 | }; |
| 210 | ||
| 6ee93e12 MR |
211 | pll2: clk@01c20008 { |
| 212 | #clock-cells = <1>; | |
| 213 | compatible = "allwinner,sun4i-a10-pll2-clk"; | |
| 214 | reg = <0x01c20008 0x8>; | |
| 215 | clocks = <&osc24M>; | |
| 216 | clock-output-names = "pll2-1x", "pll2-2x", | |
| 217 | "pll2-4x", "pll2-8x"; | |
| 218 | }; | |
| 219 | ||
| be5f83ff PL |
220 | pll3: clk@01c20010 { |
| 221 | #clock-cells = <0>; | |
| 222 | compatible = "allwinner,sun4i-a10-pll3-clk"; | |
| 223 | reg = <0x01c20010 0x4>; | |
| 224 | clocks = <&osc3M>; | |
| 225 | clock-output-names = "pll3"; | |
| 226 | }; | |
| 227 | ||
| 228 | pll3x2: pll3x2_clk { | |
| 229 | compatible = "fixed-factor-clock"; | |
| 230 | #clock-cells = <0>; | |
| 231 | clock-div = <1>; | |
| 232 | clock-mult = <2>; | |
| 233 | clocks = <&pll3>; | |
| 234 | clock-output-names = "pll3-2x"; | |
| 235 | }; | |
| 236 | ||
| dfb12c0c | 237 | pll4: clk@01c20018 { |
| ec5589f7 | 238 | #clock-cells = <0>; |
| bf6534a1 | 239 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
| ec5589f7 EL |
240 | reg = <0x01c20018 0x4>; |
| 241 | clocks = <&osc24M>; | |
| dfb12c0c | 242 | clock-output-names = "pll4"; |
| ec5589f7 EL |
243 | }; |
| 244 | ||
| dfb12c0c | 245 | pll5: clk@01c20020 { |
| c3e5e66b | 246 | #clock-cells = <1>; |
| bf6534a1 | 247 | compatible = "allwinner,sun4i-a10-pll5-clk"; |
| c3e5e66b EL |
248 | reg = <0x01c20020 0x4>; |
| 249 | clocks = <&osc24M>; | |
| 250 | clock-output-names = "pll5_ddr", "pll5_other"; | |
| 251 | }; | |
| 252 | ||
| dfb12c0c | 253 | pll6: clk@01c20028 { |
| c3e5e66b | 254 | #clock-cells = <1>; |
| bf6534a1 | 255 | compatible = "allwinner,sun4i-a10-pll6-clk"; |
| c3e5e66b EL |
256 | reg = <0x01c20028 0x4>; |
| 257 | clocks = <&osc24M>; | |
| 258 | clock-output-names = "pll6_sata", "pll6_other", "pll6"; | |
| 259 | }; | |
| 260 | ||
| be5f83ff PL |
261 | pll7: clk@01c20030 { |
| 262 | #clock-cells = <0>; | |
| 263 | compatible = "allwinner,sun4i-a10-pll3-clk"; | |
| 264 | reg = <0x01c20030 0x4>; | |
| 265 | clocks = <&osc3M>; | |
| 266 | clock-output-names = "pll7"; | |
| 267 | }; | |
| 268 | ||
| 269 | pll7x2: pll7x2_clk { | |
| 270 | compatible = "fixed-factor-clock"; | |
| 271 | #clock-cells = <0>; | |
| 272 | clock-div = <1>; | |
| 273 | clock-mult = <2>; | |
| 274 | clocks = <&pll7>; | |
| 275 | clock-output-names = "pll7-2x"; | |
| 276 | }; | |
| 277 | ||
| 69144e3b MR |
278 | /* dummy is 200M */ |
| 279 | cpu: cpu@01c20054 { | |
| 280 | #clock-cells = <0>; | |
| bf6534a1 | 281 | compatible = "allwinner,sun4i-a10-cpu-clk"; |
| 69144e3b MR |
282 | reg = <0x01c20054 0x4>; |
| 283 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; | |
| dfb12c0c | 284 | clock-output-names = "cpu"; |
| 69144e3b MR |
285 | }; |
| 286 | ||
| 287 | axi: axi@01c20054 { | |
| 288 | #clock-cells = <0>; | |
| bf6534a1 | 289 | compatible = "allwinner,sun4i-a10-axi-clk"; |
| 69144e3b MR |
290 | reg = <0x01c20054 0x4>; |
| 291 | clocks = <&cpu>; | |
| dfb12c0c | 292 | clock-output-names = "axi"; |
| 69144e3b MR |
293 | }; |
| 294 | ||
| dfb12c0c | 295 | axi_gates: clk@01c2005c { |
| 69144e3b | 296 | #clock-cells = <1>; |
| bf6534a1 | 297 | compatible = "allwinner,sun4i-a10-axi-gates-clk"; |
| 69144e3b MR |
298 | reg = <0x01c2005c 0x4>; |
| 299 | clocks = <&axi>; | |
| a3854006 | 300 | clock-indices = <0>; |
| 69144e3b MR |
301 | clock-output-names = "axi_dram"; |
| 302 | }; | |
| 303 | ||
| 304 | ahb: ahb@01c20054 { | |
| 305 | #clock-cells = <0>; | |
| bf6534a1 | 306 | compatible = "allwinner,sun4i-a10-ahb-clk"; |
| 69144e3b MR |
307 | reg = <0x01c20054 0x4>; |
| 308 | clocks = <&axi>; | |
| dfb12c0c | 309 | clock-output-names = "ahb"; |
| 69144e3b MR |
310 | }; |
| 311 | ||
| dfb12c0c | 312 | ahb_gates: clk@01c20060 { |
| 69144e3b | 313 | #clock-cells = <1>; |
| bf6534a1 | 314 | compatible = "allwinner,sun4i-a10-ahb-gates-clk"; |
| 69144e3b MR |
315 | reg = <0x01c20060 0x8>; |
| 316 | clocks = <&ahb>; | |
| a3854006 MR |
317 | clock-indices = <0>, <1>, |
| 318 | <2>, <3>, | |
| 319 | <4>, <5>, <6>, | |
| 320 | <7>, <8>, <9>, | |
| 321 | <10>, <11>, <12>, | |
| 322 | <13>, <14>, <16>, | |
| 323 | <17>, <18>, <20>, | |
| 324 | <21>, <22>, <23>, | |
| 325 | <24>, <25>, <26>, | |
| 326 | <32>, <33>, <34>, | |
| 327 | <35>, <36>, <37>, | |
| 328 | <40>, <41>, <43>, | |
| 329 | <44>, <45>, | |
| 330 | <46>, <47>, | |
| 331 | <50>, <52>; | |
| 69144e3b | 332 | clock-output-names = "ahb_usb0", "ahb_ehci0", |
| a3854006 MR |
333 | "ahb_ohci0", "ahb_ehci1", |
| 334 | "ahb_ohci1", "ahb_ss", "ahb_dma", | |
| 335 | "ahb_bist", "ahb_mmc0", "ahb_mmc1", | |
| 336 | "ahb_mmc2", "ahb_mmc3", "ahb_ms", | |
| 337 | "ahb_nand", "ahb_sdram", "ahb_ace", | |
| 338 | "ahb_emac", "ahb_ts", "ahb_spi0", | |
| 339 | "ahb_spi1", "ahb_spi2", "ahb_spi3", | |
| 340 | "ahb_pata", "ahb_sata", "ahb_gps", | |
| 341 | "ahb_ve", "ahb_tvd", "ahb_tve0", | |
| 342 | "ahb_tve1", "ahb_lcd0", "ahb_lcd1", | |
| 343 | "ahb_csi0", "ahb_csi1", "ahb_hdmi", | |
| 344 | "ahb_de_be0", "ahb_de_be1", | |
| 345 | "ahb_de_fe0", "ahb_de_fe1", | |
| 346 | "ahb_mp", "ahb_mali400"; | |
| 69144e3b MR |
347 | }; |
| 348 | ||
| 349 | apb0: apb0@01c20054 { | |
| 350 | #clock-cells = <0>; | |
| bf6534a1 | 351 | compatible = "allwinner,sun4i-a10-apb0-clk"; |
| 69144e3b MR |
352 | reg = <0x01c20054 0x4>; |
| 353 | clocks = <&ahb>; | |
| dfb12c0c | 354 | clock-output-names = "apb0"; |
| 69144e3b MR |
355 | }; |
| 356 | ||
| dfb12c0c | 357 | apb0_gates: clk@01c20068 { |
| 69144e3b | 358 | #clock-cells = <1>; |
| bf6534a1 | 359 | compatible = "allwinner,sun4i-a10-apb0-gates-clk"; |
| 69144e3b MR |
360 | reg = <0x01c20068 0x4>; |
| 361 | clocks = <&apb0>; | |
| a3854006 MR |
362 | clock-indices = <0>, <1>, |
| 363 | <2>, <3>, | |
| 364 | <5>, <6>, | |
| 365 | <7>, <10>; | |
| 69144e3b | 366 | clock-output-names = "apb0_codec", "apb0_spdif", |
| a3854006 MR |
367 | "apb0_ac97", "apb0_iis", |
| 368 | "apb0_pio", "apb0_ir0", | |
| 369 | "apb0_ir1", "apb0_keypad"; | |
| 69144e3b MR |
370 | }; |
| 371 | ||
| acbcc0f0 | 372 | apb1: clk@01c20058 { |
| 69144e3b | 373 | #clock-cells = <0>; |
| bf6534a1 | 374 | compatible = "allwinner,sun4i-a10-apb1-clk"; |
| 69144e3b | 375 | reg = <0x01c20058 0x4>; |
| acbcc0f0 | 376 | clocks = <&osc24M>, <&pll6 1>, <&osc32k>; |
| dfb12c0c | 377 | clock-output-names = "apb1"; |
| 69144e3b MR |
378 | }; |
| 379 | ||
| dfb12c0c | 380 | apb1_gates: clk@01c2006c { |
| 69144e3b | 381 | #clock-cells = <1>; |
| bf6534a1 | 382 | compatible = "allwinner,sun4i-a10-apb1-gates-clk"; |
| 69144e3b MR |
383 | reg = <0x01c2006c 0x4>; |
| 384 | clocks = <&apb1>; | |
| a3854006 MR |
385 | clock-indices = <0>, <1>, |
| 386 | <2>, <4>, | |
| 387 | <5>, <6>, | |
| 388 | <7>, <16>, | |
| 389 | <17>, <18>, | |
| 390 | <19>, <20>, | |
| 391 | <21>, <22>, | |
| 392 | <23>; | |
| 69144e3b | 393 | clock-output-names = "apb1_i2c0", "apb1_i2c1", |
| a3854006 MR |
394 | "apb1_i2c2", "apb1_can", |
| 395 | "apb1_scr", "apb1_ps20", | |
| 396 | "apb1_ps21", "apb1_uart0", | |
| 397 | "apb1_uart1", "apb1_uart2", | |
| 398 | "apb1_uart3", "apb1_uart4", | |
| 399 | "apb1_uart5", "apb1_uart6", | |
| 400 | "apb1_uart7"; | |
| 69144e3b | 401 | }; |
| 4b756ffb EL |
402 | |
| 403 | nand_clk: clk@01c20080 { | |
| 404 | #clock-cells = <0>; | |
| bf6534a1 | 405 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 4b756ffb EL |
406 | reg = <0x01c20080 0x4>; |
| 407 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 408 | clock-output-names = "nand"; | |
| 409 | }; | |
| 410 | ||
| 411 | ms_clk: clk@01c20084 { | |
| 412 | #clock-cells = <0>; | |
| bf6534a1 | 413 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 4b756ffb EL |
414 | reg = <0x01c20084 0x4>; |
| 415 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 416 | clock-output-names = "ms"; | |
| 417 | }; | |
| 418 | ||
| 419 | mmc0_clk: clk@01c20088 { | |
| d8c3a392 MR |
420 | #clock-cells = <1>; |
| 421 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
| 4b756ffb EL |
422 | reg = <0x01c20088 0x4>; |
| 423 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| d8c3a392 MR |
424 | clock-output-names = "mmc0", |
| 425 | "mmc0_output", | |
| 426 | "mmc0_sample"; | |
| 4b756ffb EL |
427 | }; |
| 428 | ||
| 429 | mmc1_clk: clk@01c2008c { | |
| d8c3a392 MR |
430 | #clock-cells = <1>; |
| 431 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
| 4b756ffb EL |
432 | reg = <0x01c2008c 0x4>; |
| 433 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| d8c3a392 MR |
434 | clock-output-names = "mmc1", |
| 435 | "mmc1_output", | |
| 436 | "mmc1_sample"; | |
| 4b756ffb EL |
437 | }; |
| 438 | ||
| 439 | mmc2_clk: clk@01c20090 { | |
| d8c3a392 MR |
440 | #clock-cells = <1>; |
| 441 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
| 4b756ffb EL |
442 | reg = <0x01c20090 0x4>; |
| 443 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| d8c3a392 MR |
444 | clock-output-names = "mmc2", |
| 445 | "mmc2_output", | |
| 446 | "mmc2_sample"; | |
| 4b756ffb EL |
447 | }; |
| 448 | ||
| 449 | mmc3_clk: clk@01c20094 { | |
| d8c3a392 MR |
450 | #clock-cells = <1>; |
| 451 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
| 4b756ffb EL |
452 | reg = <0x01c20094 0x4>; |
| 453 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| d8c3a392 MR |
454 | clock-output-names = "mmc3", |
| 455 | "mmc3_output", | |
| 456 | "mmc3_sample"; | |
| 4b756ffb EL |
457 | }; |
| 458 | ||
| 459 | ts_clk: clk@01c20098 { | |
| 460 | #clock-cells = <0>; | |
| bf6534a1 | 461 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 4b756ffb EL |
462 | reg = <0x01c20098 0x4>; |
| 463 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 464 | clock-output-names = "ts"; | |
| 465 | }; | |
| 466 | ||
| 467 | ss_clk: clk@01c2009c { | |
| 468 | #clock-cells = <0>; | |
| bf6534a1 | 469 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 4b756ffb EL |
470 | reg = <0x01c2009c 0x4>; |
| 471 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 472 | clock-output-names = "ss"; | |
| 473 | }; | |
| 474 | ||
| 475 | spi0_clk: clk@01c200a0 { | |
| 476 | #clock-cells = <0>; | |
| bf6534a1 | 477 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 4b756ffb EL |
478 | reg = <0x01c200a0 0x4>; |
| 479 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 480 | clock-output-names = "spi0"; | |
| 481 | }; | |
| 482 | ||
| 483 | spi1_clk: clk@01c200a4 { | |
| 484 | #clock-cells = <0>; | |
| bf6534a1 | 485 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 4b756ffb EL |
486 | reg = <0x01c200a4 0x4>; |
| 487 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 488 | clock-output-names = "spi1"; | |
| 489 | }; | |
| 490 | ||
| 491 | spi2_clk: clk@01c200a8 { | |
| 492 | #clock-cells = <0>; | |
| bf6534a1 | 493 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 4b756ffb EL |
494 | reg = <0x01c200a8 0x4>; |
| 495 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 496 | clock-output-names = "spi2"; | |
| 497 | }; | |
| 498 | ||
| 499 | pata_clk: clk@01c200ac { | |
| 500 | #clock-cells = <0>; | |
| bf6534a1 | 501 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 4b756ffb EL |
502 | reg = <0x01c200ac 0x4>; |
| 503 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 504 | clock-output-names = "pata"; | |
| 505 | }; | |
| 506 | ||
| 507 | ir0_clk: clk@01c200b0 { | |
| 508 | #clock-cells = <0>; | |
| bf6534a1 | 509 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 4b756ffb EL |
510 | reg = <0x01c200b0 0x4>; |
| 511 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 512 | clock-output-names = "ir0"; | |
| 513 | }; | |
| 514 | ||
| 515 | ir1_clk: clk@01c200b4 { | |
| 516 | #clock-cells = <0>; | |
| bf6534a1 | 517 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 4b756ffb EL |
518 | reg = <0x01c200b4 0x4>; |
| 519 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 520 | clock-output-names = "ir1"; | |
| 521 | }; | |
| 522 | ||
| 1010cd54 MC |
523 | spdif_clk: clk@01c200c0 { |
| 524 | #clock-cells = <0>; | |
| 525 | compatible = "allwinner,sun4i-a10-mod1-clk"; | |
| 526 | reg = <0x01c200c0 0x4>; | |
| 527 | clocks = <&pll2 SUN4I_A10_PLL2_8X>, | |
| 528 | <&pll2 SUN4I_A10_PLL2_4X>, | |
| 529 | <&pll2 SUN4I_A10_PLL2_2X>, | |
| 530 | <&pll2 SUN4I_A10_PLL2_1X>; | |
| 531 | clock-output-names = "spdif"; | |
| 532 | }; | |
| 533 | ||
| 0076c8bd RB |
534 | usb_clk: clk@01c200cc { |
| 535 | #clock-cells = <1>; | |
| 8358aada | 536 | #reset-cells = <1>; |
| 0076c8bd RB |
537 | compatible = "allwinner,sun4i-a10-usb-clk"; |
| 538 | reg = <0x01c200cc 0x4>; | |
| 539 | clocks = <&pll6 1>; | |
| d8cacaa3 MR |
540 | clock-output-names = "usb_ohci0", "usb_ohci1", |
| 541 | "usb_phy"; | |
| 0076c8bd RB |
542 | }; |
| 543 | ||
| 4b756ffb EL |
544 | spi3_clk: clk@01c200d4 { |
| 545 | #clock-cells = <0>; | |
| bf6534a1 | 546 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 4b756ffb EL |
547 | reg = <0x01c200d4 0x4>; |
| 548 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 549 | clock-output-names = "spi3"; | |
| 550 | }; | |
| b516fa5d | 551 | |
| 82f8582f CYT |
552 | dram_gates: clk@01c20100 { |
| 553 | #clock-cells = <1>; | |
| 554 | compatible = "allwinner,sun4i-a10-dram-gates-clk"; | |
| 555 | reg = <0x01c20100 0x4>; | |
| 556 | clocks = <&pll5 0>; | |
| 557 | clock-indices = <0>, | |
| 558 | <1>, <2>, | |
| 559 | <3>, | |
| 560 | <4>, | |
| 561 | <5>, <6>, | |
| 562 | <15>, | |
| 563 | <24>, <25>, | |
| 564 | <26>, <27>, | |
| 565 | <28>, <29>; | |
| 566 | clock-output-names = "dram_ve", | |
| 567 | "dram_csi0", "dram_csi1", | |
| 568 | "dram_ts", | |
| 569 | "dram_tvd", | |
| 570 | "dram_tve0", "dram_tve1", | |
| 571 | "dram_output", | |
| 572 | "dram_de_fe1", "dram_de_fe0", | |
| 573 | "dram_de_be0", "dram_de_be1", | |
| 574 | "dram_de_mp", "dram_ace"; | |
| 575 | }; | |
| 576 | ||
| 1ccc4939 CYT |
577 | ve_clk: clk@01c2013c { |
| 578 | #clock-cells = <0>; | |
| 579 | #reset-cells = <0>; | |
| 580 | compatible = "allwinner,sun4i-a10-ve-clk"; | |
| 581 | reg = <0x01c2013c 0x4>; | |
| 582 | clocks = <&pll4>; | |
| 583 | clock-output-names = "ve"; | |
| 584 | }; | |
| 585 | ||
| b516fa5d MR |
586 | codec_clk: clk@01c20140 { |
| 587 | #clock-cells = <0>; | |
| 588 | compatible = "allwinner,sun4i-a10-codec-clk"; | |
| 589 | reg = <0x01c20140 0x4>; | |
| 590 | clocks = <&pll2 SUN4I_A10_PLL2_1X>; | |
| 591 | clock-output-names = "codec"; | |
| 592 | }; | |
| 69144e3b MR |
593 | }; |
| 594 | ||
| b74aec1a | 595 | soc@01c00000 { |
| 69144e3b MR |
596 | compatible = "simple-bus"; |
| 597 | #address-cells = <1>; | |
| 598 | #size-cells = <1>; | |
| 69144e3b MR |
599 | ranges; |
| 600 | ||
| 1fbc1517 MR |
601 | sram-controller@01c00000 { |
| 602 | compatible = "allwinner,sun4i-a10-sram-controller"; | |
| 603 | reg = <0x01c00000 0x30>; | |
| 604 | #address-cells = <1>; | |
| 605 | #size-cells = <1>; | |
| 606 | ranges; | |
| 607 | ||
| 608 | sram_a: sram@00000000 { | |
| 609 | compatible = "mmio-sram"; | |
| 610 | reg = <0x00000000 0xc000>; | |
| 611 | #address-cells = <1>; | |
| 612 | #size-cells = <1>; | |
| 613 | ranges = <0 0x00000000 0xc000>; | |
| 614 | ||
| 615 | emac_sram: sram-section@8000 { | |
| 616 | compatible = "allwinner,sun4i-a10-sram-a3-a4"; | |
| 617 | reg = <0x8000 0x4000>; | |
| 618 | status = "disabled"; | |
| 619 | }; | |
| 620 | }; | |
| 621 | ||
| 622 | sram_d: sram@00010000 { | |
| 623 | compatible = "mmio-sram"; | |
| 624 | reg = <0x00010000 0x1000>; | |
| 625 | #address-cells = <1>; | |
| 626 | #size-cells = <1>; | |
| 627 | ranges = <0 0x00010000 0x1000>; | |
| 628 | ||
| 629 | otg_sram: sram-section@0000 { | |
| 630 | compatible = "allwinner,sun4i-a10-sram-d"; | |
| 631 | reg = <0x0000 0x1000>; | |
| 632 | status = "disabled"; | |
| 633 | }; | |
| 634 | }; | |
| 635 | }; | |
| 636 | ||
| 1324f532 EL |
637 | dma: dma-controller@01c02000 { |
| 638 | compatible = "allwinner,sun4i-a10-dma"; | |
| 639 | reg = <0x01c02000 0x1000>; | |
| 640 | interrupts = <27>; | |
| 641 | clocks = <&ahb_gates 6>; | |
| 642 | #dma-cells = <2>; | |
| 643 | }; | |
| 644 | ||
| 65918e26 MR |
645 | spi0: spi@01c05000 { |
| 646 | compatible = "allwinner,sun4i-a10-spi"; | |
| 647 | reg = <0x01c05000 0x1000>; | |
| 648 | interrupts = <10>; | |
| 649 | clocks = <&ahb_gates 20>, <&spi0_clk>; | |
| 650 | clock-names = "ahb", "mod"; | |
| 1f9f6a78 MR |
651 | dmas = <&dma SUN4I_DMA_DEDICATED 27>, |
| 652 | <&dma SUN4I_DMA_DEDICATED 26>; | |
| 4192ff81 | 653 | dma-names = "rx", "tx"; |
| 65918e26 MR |
654 | status = "disabled"; |
| 655 | #address-cells = <1>; | |
| 656 | #size-cells = <0>; | |
| 657 | }; | |
| 658 | ||
| 659 | spi1: spi@01c06000 { | |
| 660 | compatible = "allwinner,sun4i-a10-spi"; | |
| 661 | reg = <0x01c06000 0x1000>; | |
| 662 | interrupts = <11>; | |
| 663 | clocks = <&ahb_gates 21>, <&spi1_clk>; | |
| 664 | clock-names = "ahb", "mod"; | |
| 1f9f6a78 MR |
665 | dmas = <&dma SUN4I_DMA_DEDICATED 9>, |
| 666 | <&dma SUN4I_DMA_DEDICATED 8>; | |
| 4192ff81 | 667 | dma-names = "rx", "tx"; |
| 65918e26 MR |
668 | status = "disabled"; |
| 669 | #address-cells = <1>; | |
| 670 | #size-cells = <0>; | |
| 671 | }; | |
| 672 | ||
| e38afcb3 | 673 | emac: ethernet@01c0b000 { |
| 1c70e099 | 674 | compatible = "allwinner,sun4i-a10-emac"; |
| e38afcb3 MR |
675 | reg = <0x01c0b000 0x1000>; |
| 676 | interrupts = <55>; | |
| 677 | clocks = <&ahb_gates 17>; | |
| 1fbc1517 | 678 | allwinner,sram = <&emac_sram 1>; |
| e38afcb3 MR |
679 | status = "disabled"; |
| 680 | }; | |
| 681 | ||
| 92395f56 | 682 | mdio: mdio@01c0b080 { |
| 1c70e099 | 683 | compatible = "allwinner,sun4i-a10-mdio"; |
| e38afcb3 MR |
684 | reg = <0x01c0b080 0x14>; |
| 685 | status = "disabled"; | |
| 686 | #address-cells = <1>; | |
| 687 | #size-cells = <0>; | |
| 688 | }; | |
| 689 | ||
| b258b369 DL |
690 | mmc0: mmc@01c0f000 { |
| 691 | compatible = "allwinner,sun4i-a10-mmc"; | |
| 692 | reg = <0x01c0f000 0x1000>; | |
| d8c3a392 MR |
693 | clocks = <&ahb_gates 8>, |
| 694 | <&mmc0_clk 0>, | |
| 695 | <&mmc0_clk 1>, | |
| 696 | <&mmc0_clk 2>; | |
| 697 | clock-names = "ahb", | |
| 698 | "mmc", | |
| 699 | "output", | |
| 700 | "sample"; | |
| b258b369 DL |
701 | interrupts = <32>; |
| 702 | status = "disabled"; | |
| 4c1bb9c3 HG |
703 | #address-cells = <1>; |
| 704 | #size-cells = <0>; | |
| b258b369 DL |
705 | }; |
| 706 | ||
| 707 | mmc1: mmc@01c10000 { | |
| 708 | compatible = "allwinner,sun4i-a10-mmc"; | |
| 709 | reg = <0x01c10000 0x1000>; | |
| d8c3a392 MR |
710 | clocks = <&ahb_gates 9>, |
| 711 | <&mmc1_clk 0>, | |
| 712 | <&mmc1_clk 1>, | |
| 713 | <&mmc1_clk 2>; | |
| 714 | clock-names = "ahb", | |
| 715 | "mmc", | |
| 716 | "output", | |
| 717 | "sample"; | |
| b258b369 DL |
718 | interrupts = <33>; |
| 719 | status = "disabled"; | |
| 4c1bb9c3 HG |
720 | #address-cells = <1>; |
| 721 | #size-cells = <0>; | |
| b258b369 DL |
722 | }; |
| 723 | ||
| 724 | mmc2: mmc@01c11000 { | |
| 725 | compatible = "allwinner,sun4i-a10-mmc"; | |
| 726 | reg = <0x01c11000 0x1000>; | |
| d8c3a392 MR |
727 | clocks = <&ahb_gates 10>, |
| 728 | <&mmc2_clk 0>, | |
| 729 | <&mmc2_clk 1>, | |
| 730 | <&mmc2_clk 2>; | |
| 731 | clock-names = "ahb", | |
| 732 | "mmc", | |
| 733 | "output", | |
| 734 | "sample"; | |
| b258b369 DL |
735 | interrupts = <34>; |
| 736 | status = "disabled"; | |
| 4c1bb9c3 HG |
737 | #address-cells = <1>; |
| 738 | #size-cells = <0>; | |
| b258b369 DL |
739 | }; |
| 740 | ||
| 741 | mmc3: mmc@01c12000 { | |
| 742 | compatible = "allwinner,sun4i-a10-mmc"; | |
| 743 | reg = <0x01c12000 0x1000>; | |
| d8c3a392 MR |
744 | clocks = <&ahb_gates 11>, |
| 745 | <&mmc3_clk 0>, | |
| 746 | <&mmc3_clk 1>, | |
| 747 | <&mmc3_clk 2>; | |
| 748 | clock-names = "ahb", | |
| 749 | "mmc", | |
| 750 | "output", | |
| 751 | "sample"; | |
| b258b369 DL |
752 | interrupts = <35>; |
| 753 | status = "disabled"; | |
| 4c1bb9c3 HG |
754 | #address-cells = <1>; |
| 755 | #size-cells = <0>; | |
| b258b369 DL |
756 | }; |
| 757 | ||
| ce65037f HG |
758 | usb_otg: usb@01c13000 { |
| 759 | compatible = "allwinner,sun4i-a10-musb"; | |
| 760 | reg = <0x01c13000 0x0400>; | |
| 761 | clocks = <&ahb_gates 0>; | |
| 762 | interrupts = <38>; | |
| 763 | interrupt-names = "mc"; | |
| 764 | phys = <&usbphy 0>; | |
| 765 | phy-names = "usb"; | |
| 766 | extcon = <&usbphy 0>; | |
| 767 | allwinner,sram = <&otg_sram 1>; | |
| 768 | status = "disabled"; | |
| 769 | }; | |
| 770 | ||
| 6ab1ce24 RB |
771 | usbphy: phy@01c13400 { |
| 772 | #phy-cells = <1>; | |
| 773 | compatible = "allwinner,sun4i-a10-usb-phy"; | |
| 774 | reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; | |
| 775 | reg-names = "phy_ctrl", "pmu1", "pmu2"; | |
| 776 | clocks = <&usb_clk 8>; | |
| 777 | clock-names = "usb_phy"; | |
| 4dba4185 CYT |
778 | resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>; |
| 779 | reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; | |
| 6ab1ce24 RB |
780 | status = "disabled"; |
| 781 | }; | |
| 782 | ||
| 783 | ehci0: usb@01c14000 { | |
| 784 | compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; | |
| 785 | reg = <0x01c14000 0x100>; | |
| 786 | interrupts = <39>; | |
| 787 | clocks = <&ahb_gates 1>; | |
| 788 | phys = <&usbphy 1>; | |
| 789 | phy-names = "usb"; | |
| 790 | status = "disabled"; | |
| 791 | }; | |
| 792 | ||
| 793 | ohci0: usb@01c14400 { | |
| 794 | compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; | |
| 795 | reg = <0x01c14400 0x100>; | |
| 796 | interrupts = <64>; | |
| 797 | clocks = <&usb_clk 6>, <&ahb_gates 2>; | |
| 798 | phys = <&usbphy 1>; | |
| 799 | phy-names = "usb"; | |
| 800 | status = "disabled"; | |
| 801 | }; | |
| 802 | ||
| 56ba8c58 LC |
803 | crypto: crypto-engine@01c15000 { |
| 804 | compatible = "allwinner,sun4i-a10-crypto"; | |
| 805 | reg = <0x01c15000 0x1000>; | |
| 806 | interrupts = <86>; | |
| 807 | clocks = <&ahb_gates 5>, <&ss_clk>; | |
| 808 | clock-names = "ahb", "mod"; | |
| 809 | }; | |
| 810 | ||
| 65918e26 MR |
811 | spi2: spi@01c17000 { |
| 812 | compatible = "allwinner,sun4i-a10-spi"; | |
| 813 | reg = <0x01c17000 0x1000>; | |
| 814 | interrupts = <12>; | |
| 815 | clocks = <&ahb_gates 22>, <&spi2_clk>; | |
| 816 | clock-names = "ahb", "mod"; | |
| 1f9f6a78 MR |
817 | dmas = <&dma SUN4I_DMA_DEDICATED 29>, |
| 818 | <&dma SUN4I_DMA_DEDICATED 28>; | |
| 4192ff81 | 819 | dma-names = "rx", "tx"; |
| 65918e26 MR |
820 | status = "disabled"; |
| 821 | #address-cells = <1>; | |
| 822 | #size-cells = <0>; | |
| 823 | }; | |
| 824 | ||
| 248bd1e2 OS |
825 | ahci: sata@01c18000 { |
| 826 | compatible = "allwinner,sun4i-a10-ahci"; | |
| 827 | reg = <0x01c18000 0x1000>; | |
| 828 | interrupts = <56>; | |
| 829 | clocks = <&pll6 0>, <&ahb_gates 25>; | |
| 830 | status = "disabled"; | |
| 831 | }; | |
| 832 | ||
| 6ab1ce24 RB |
833 | ehci1: usb@01c1c000 { |
| 834 | compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; | |
| 835 | reg = <0x01c1c000 0x100>; | |
| 836 | interrupts = <40>; | |
| 837 | clocks = <&ahb_gates 3>; | |
| 838 | phys = <&usbphy 2>; | |
| 839 | phy-names = "usb"; | |
| 840 | status = "disabled"; | |
| 841 | }; | |
| 842 | ||
| 843 | ohci1: usb@01c1c400 { | |
| 844 | compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; | |
| 845 | reg = <0x01c1c400 0x100>; | |
| 846 | interrupts = <65>; | |
| 847 | clocks = <&usb_clk 7>, <&ahb_gates 4>; | |
| 848 | phys = <&usbphy 2>; | |
| 849 | phy-names = "usb"; | |
| 850 | status = "disabled"; | |
| 851 | }; | |
| 852 | ||
| 65918e26 MR |
853 | spi3: spi@01c1f000 { |
| 854 | compatible = "allwinner,sun4i-a10-spi"; | |
| 855 | reg = <0x01c1f000 0x1000>; | |
| 856 | interrupts = <50>; | |
| 857 | clocks = <&ahb_gates 23>, <&spi3_clk>; | |
| 858 | clock-names = "ahb", "mod"; | |
| 1f9f6a78 MR |
859 | dmas = <&dma SUN4I_DMA_DEDICATED 31>, |
| 860 | <&dma SUN4I_DMA_DEDICATED 30>; | |
| 4192ff81 | 861 | dma-names = "rx", "tx"; |
| 65918e26 MR |
862 | status = "disabled"; |
| 863 | #address-cells = <1>; | |
| 864 | #size-cells = <0>; | |
| 865 | }; | |
| 866 | ||
| 69144e3b | 867 | intc: interrupt-controller@01c20400 { |
| 09504a7d | 868 | compatible = "allwinner,sun4i-a10-ic"; |
| 69144e3b MR |
869 | reg = <0x01c20400 0x400>; |
| 870 | interrupt-controller; | |
| 871 | #interrupt-cells = <1>; | |
| 872 | }; | |
| 873 | ||
| e10911e1 | 874 | pio: pinctrl@01c20800 { |
| 874b4e45 MR |
875 | compatible = "allwinner,sun4i-a10-pinctrl"; |
| 876 | reg = <0x01c20800 0x400>; | |
| 39138bc6 | 877 | interrupts = <28>; |
| 36386d6e | 878 | clocks = <&apb0_gates 5>; |
| e10911e1 | 879 | gpio-controller; |
| 39138bc6 | 880 | interrupt-controller; |
| b03e0816 | 881 | #interrupt-cells = <3>; |
| e10911e1 | 882 | #gpio-cells = <3>; |
| 581981be | 883 | |
| 1d5726e9 AB |
884 | pwm0_pins_a: pwm0@0 { |
| 885 | allwinner,pins = "PB2"; | |
| 886 | allwinner,function = "pwm"; | |
| 092a0c3b MR |
887 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 888 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 1d5726e9 AB |
889 | }; |
| 890 | ||
| 891 | pwm1_pins_a: pwm1@0 { | |
| 892 | allwinner,pins = "PI3"; | |
| 893 | allwinner,function = "pwm"; | |
| 092a0c3b MR |
894 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 895 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 1d5726e9 AB |
896 | }; |
| 897 | ||
| 581981be MR |
898 | uart0_pins_a: uart0@0 { |
| 899 | allwinner,pins = "PB22", "PB23"; | |
| 900 | allwinner,function = "uart0"; | |
| 092a0c3b MR |
901 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 902 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 581981be MR |
903 | }; |
| 904 | ||
| 905 | uart0_pins_b: uart0@1 { | |
| 906 | allwinner,pins = "PF2", "PF4"; | |
| 907 | allwinner,function = "uart0"; | |
| 092a0c3b MR |
908 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 909 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 581981be MR |
910 | }; |
| 911 | ||
| 912 | uart1_pins_a: uart1@0 { | |
| 913 | allwinner,pins = "PA10", "PA11"; | |
| 914 | allwinner,function = "uart1"; | |
| 092a0c3b MR |
915 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 916 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 581981be | 917 | }; |
| 27cce4ff MR |
918 | |
| 919 | i2c0_pins_a: i2c0@0 { | |
| 920 | allwinner,pins = "PB0", "PB1"; | |
| 921 | allwinner,function = "i2c0"; | |
| 092a0c3b MR |
922 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 923 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 27cce4ff MR |
924 | }; |
| 925 | ||
| 926 | i2c1_pins_a: i2c1@0 { | |
| 927 | allwinner,pins = "PB18", "PB19"; | |
| 928 | allwinner,function = "i2c1"; | |
| 092a0c3b MR |
929 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 930 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 27cce4ff MR |
931 | }; |
| 932 | ||
| 933 | i2c2_pins_a: i2c2@0 { | |
| 934 | allwinner,pins = "PB20", "PB21"; | |
| 935 | allwinner,function = "i2c2"; | |
| 092a0c3b MR |
936 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 937 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 27cce4ff | 938 | }; |
| 496322bc | 939 | |
| b21da664 MR |
940 | emac_pins_a: emac0@0 { |
| 941 | allwinner,pins = "PA0", "PA1", "PA2", | |
| 942 | "PA3", "PA4", "PA5", "PA6", | |
| 943 | "PA7", "PA8", "PA9", "PA10", | |
| 944 | "PA11", "PA12", "PA13", "PA14", | |
| 945 | "PA15", "PA16"; | |
| 946 | allwinner,function = "emac"; | |
| 092a0c3b MR |
947 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 948 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| b21da664 | 949 | }; |
| b5f86a3a HG |
950 | |
| 951 | mmc0_pins_a: mmc0@0 { | |
| d8cacaa3 MR |
952 | allwinner,pins = "PF0", "PF1", "PF2", |
| 953 | "PF3", "PF4", "PF5"; | |
| b5f86a3a | 954 | allwinner,function = "mmc0"; |
| 092a0c3b MR |
955 | allwinner,drive = <SUN4I_PINCTRL_30_MA>; |
| 956 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| b5f86a3a HG |
957 | }; |
| 958 | ||
| 959 | mmc0_cd_pin_reference_design: mmc0_cd_pin@0 { | |
| 960 | allwinner,pins = "PH1"; | |
| 961 | allwinner,function = "gpio_in"; | |
| 092a0c3b MR |
962 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 963 | allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; | |
| b5f86a3a | 964 | }; |
| a4e1099a | 965 | |
| 469a22e6 MC |
966 | ir0_rx_pins_a: ir0@0 { |
| 967 | allwinner,pins = "PB4"; | |
| a4e1099a | 968 | allwinner,function = "ir0"; |
| 092a0c3b MR |
969 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 970 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| a4e1099a HG |
971 | }; |
| 972 | ||
| 469a22e6 MC |
973 | ir0_tx_pins_a: ir0@1 { |
| 974 | allwinner,pins = "PB3"; | |
| 975 | allwinner,function = "ir0"; | |
| 976 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 977 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 978 | }; | |
| 979 | ||
| 980 | ir1_rx_pins_a: ir1@0 { | |
| 981 | allwinner,pins = "PB23"; | |
| 982 | allwinner,function = "ir1"; | |
| 983 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 984 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 985 | }; | |
| 986 | ||
| 987 | ir1_tx_pins_a: ir1@1 { | |
| 988 | allwinner,pins = "PB22"; | |
| a4e1099a | 989 | allwinner,function = "ir1"; |
| 092a0c3b MR |
990 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 991 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| a4e1099a | 992 | }; |
| ec66d0bb AG |
993 | |
| 994 | spi0_pins_a: spi0@0 { | |
| f3022c6c MR |
995 | allwinner,pins = "PI11", "PI12", "PI13"; |
| 996 | allwinner,function = "spi0"; | |
| 997 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 998 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 999 | }; | |
| 1000 | ||
| 1001 | spi0_cs0_pins_a: spi0_cs0@0 { | |
| 1002 | allwinner,pins = "PI10"; | |
| ec66d0bb | 1003 | allwinner,function = "spi0"; |
| 092a0c3b MR |
1004 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 1005 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| ec66d0bb AG |
1006 | }; |
| 1007 | ||
| 1008 | spi1_pins_a: spi1@0 { | |
| f3022c6c MR |
1009 | allwinner,pins = "PI17", "PI18", "PI19"; |
| 1010 | allwinner,function = "spi1"; | |
| 1011 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 1012 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 1013 | }; | |
| 1014 | ||
| 1015 | spi1_cs0_pins_a: spi1_cs0@0 { | |
| 1016 | allwinner,pins = "PI16"; | |
| ec66d0bb | 1017 | allwinner,function = "spi1"; |
| 092a0c3b MR |
1018 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 1019 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| ec66d0bb AG |
1020 | }; |
| 1021 | ||
| 1022 | spi2_pins_a: spi2@0 { | |
| f3022c6c | 1023 | allwinner,pins = "PC20", "PC21", "PC22"; |
| ec66d0bb | 1024 | allwinner,function = "spi2"; |
| 092a0c3b MR |
1025 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 1026 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| ec66d0bb AG |
1027 | }; |
| 1028 | ||
| 1029 | spi2_pins_b: spi2@1 { | |
| f3022c6c MR |
1030 | allwinner,pins = "PB15", "PB16", "PB17"; |
| 1031 | allwinner,function = "spi2"; | |
| 1032 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 1033 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 1034 | }; | |
| 1035 | ||
| 1036 | spi2_cs0_pins_a: spi2_cs0@0 { | |
| 1037 | allwinner,pins = "PC19"; | |
| 1038 | allwinner,function = "spi2"; | |
| 1039 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 1040 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 1041 | }; | |
| 1042 | ||
| 1043 | spi2_cs0_pins_b: spi2_cs0@1 { | |
| 1044 | allwinner,pins = "PB14"; | |
| ec66d0bb | 1045 | allwinner,function = "spi2"; |
| 092a0c3b MR |
1046 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 1047 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| ec66d0bb | 1048 | }; |
| 1e8d1567 VP |
1049 | |
| 1050 | ps20_pins_a: ps20@0 { | |
| 1051 | allwinner,pins = "PI20", "PI21"; | |
| 1052 | allwinner,function = "ps2"; | |
| 1053 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 1054 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 1055 | }; | |
| 1056 | ||
| 1057 | ps21_pins_a: ps21@0 { | |
| 1058 | allwinner,pins = "PH12", "PH13"; | |
| 1059 | allwinner,function = "ps2"; | |
| 1060 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 1061 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| a4e1099a | 1062 | }; |
| 79f969f0 MC |
1063 | |
| 1064 | spdif_tx_pins_a: spdif@0 { | |
| 1065 | allwinner,pins = "PB13"; | |
| 1066 | allwinner,function = "spdif"; | |
| 1067 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 1068 | allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; | |
| 1069 | }; | |
| 874b4e45 | 1070 | }; |
| 89b3c99f | 1071 | |
| 69144e3b | 1072 | timer@01c20c00 { |
| b4f26440 | 1073 | compatible = "allwinner,sun4i-a10-timer"; |
| 69144e3b MR |
1074 | reg = <0x01c20c00 0x90>; |
| 1075 | interrupts = <22>; | |
| 1076 | clocks = <&osc24M>; | |
| 1077 | }; | |
| 1078 | ||
| 1079 | wdt: watchdog@01c20c90 { | |
| ca5d04d9 | 1080 | compatible = "allwinner,sun4i-a10-wdt"; |
| 69144e3b MR |
1081 | reg = <0x01c20c90 0x10>; |
| 1082 | }; | |
| 1083 | ||
| b5d905c7 | 1084 | rtc: rtc@01c20d00 { |
| 5fc4bc89 | 1085 | compatible = "allwinner,sun4i-a10-rtc"; |
| b5d905c7 CC |
1086 | reg = <0x01c20d00 0x20>; |
| 1087 | interrupts = <24>; | |
| 1088 | }; | |
| 1089 | ||
| 4b57a395 AB |
1090 | pwm: pwm@01c20e00 { |
| 1091 | compatible = "allwinner,sun4i-a10-pwm"; | |
| 1092 | reg = <0x01c20e00 0xc>; | |
| 1093 | clocks = <&osc24M>; | |
| 1094 | #pwm-cells = <3>; | |
| 1095 | status = "disabled"; | |
| 1096 | }; | |
| 1097 | ||
| 166db83e MC |
1098 | spdif: spdif@01c21000 { |
| 1099 | #sound-dai-cells = <0>; | |
| 1100 | compatible = "allwinner,sun4i-a10-spdif"; | |
| 1101 | reg = <0x01c21000 0x400>; | |
| 1102 | interrupts = <13>; | |
| 1103 | clocks = <&apb0_gates 1>, <&spdif_clk>; | |
| 1104 | clock-names = "apb", "spdif"; | |
| 1105 | dmas = <&dma SUN4I_DMA_NORMAL 2>, | |
| 1106 | <&dma SUN4I_DMA_NORMAL 2>; | |
| 1107 | dma-names = "rx", "tx"; | |
| 1108 | status = "disabled"; | |
| 1109 | }; | |
| 1110 | ||
| a4e1099a HG |
1111 | ir0: ir@01c21800 { |
| 1112 | compatible = "allwinner,sun4i-a10-ir"; | |
| 1113 | clocks = <&apb0_gates 6>, <&ir0_clk>; | |
| 1114 | clock-names = "apb", "ir"; | |
| 1115 | interrupts = <5>; | |
| 1116 | reg = <0x01c21800 0x40>; | |
| 1117 | status = "disabled"; | |
| 1118 | }; | |
| 1119 | ||
| 1120 | ir1: ir@01c21c00 { | |
| 1121 | compatible = "allwinner,sun4i-a10-ir"; | |
| 1122 | clocks = <&apb0_gates 7>, <&ir1_clk>; | |
| 1123 | clock-names = "apb", "ir"; | |
| 1124 | interrupts = <6>; | |
| 1125 | reg = <0x01c21c00 0x40>; | |
| 1126 | status = "disabled"; | |
| 1127 | }; | |
| 1128 | ||
| b0512e15 HG |
1129 | lradc: lradc@01c22800 { |
| 1130 | compatible = "allwinner,sun4i-a10-lradc-keys"; | |
| 1131 | reg = <0x01c22800 0x100>; | |
| 1132 | interrupts = <31>; | |
| 1133 | status = "disabled"; | |
| 1134 | }; | |
| 1135 | ||
| bcf88450 MC |
1136 | codec: codec@01c22c00 { |
| 1137 | #sound-dai-cells = <0>; | |
| 1138 | compatible = "allwinner,sun4i-a10-codec"; | |
| 1139 | reg = <0x01c22c00 0x40>; | |
| 1140 | interrupts = <30>; | |
| 1141 | clocks = <&apb0_gates 0>, <&codec_clk>; | |
| 1142 | clock-names = "apb", "codec"; | |
| 1143 | dmas = <&dma SUN4I_DMA_NORMAL 19>, | |
| 1144 | <&dma SUN4I_DMA_NORMAL 19>; | |
| 1145 | dma-names = "rx", "tx"; | |
| 1146 | status = "disabled"; | |
| 1147 | }; | |
| 1148 | ||
| 2bad969f | 1149 | sid: eeprom@01c23800 { |
| 043d56ee | 1150 | compatible = "allwinner,sun4i-a10-sid"; |
| 2bad969f OS |
1151 | reg = <0x01c23800 0x10>; |
| 1152 | }; | |
| 1153 | ||
| 57c8839c | 1154 | rtp: rtp@01c25000 { |
| 40dd8f3b | 1155 | compatible = "allwinner,sun4i-a10-ts"; |
| 57c8839c HG |
1156 | reg = <0x01c25000 0x100>; |
| 1157 | interrupts = <29>; | |
| 41e7afb1 | 1158 | #thermal-sensor-cells = <0>; |
| 57c8839c HG |
1159 | }; |
| 1160 | ||
| 89b3c99f MR |
1161 | uart0: serial@01c28000 { |
| 1162 | compatible = "snps,dw-apb-uart"; | |
| 1163 | reg = <0x01c28000 0x400>; | |
| 1164 | interrupts = <1>; | |
| 1165 | reg-shift = <2>; | |
| 1166 | reg-io-width = <4>; | |
| 9ff49ec7 | 1167 | clocks = <&apb1_gates 16>; |
| 89b3c99f MR |
1168 | status = "disabled"; |
| 1169 | }; | |
| 76f14d0a | 1170 | |
| 69144e3b MR |
1171 | uart1: serial@01c28400 { |
| 1172 | compatible = "snps,dw-apb-uart"; | |
| 1173 | reg = <0x01c28400 0x400>; | |
| 1174 | interrupts = <2>; | |
| 1175 | reg-shift = <2>; | |
| 1176 | reg-io-width = <4>; | |
| 1177 | clocks = <&apb1_gates 17>; | |
| 1178 | status = "disabled"; | |
| 1179 | }; | |
| 1180 | ||
| 76f14d0a MR |
1181 | uart2: serial@01c28800 { |
| 1182 | compatible = "snps,dw-apb-uart"; | |
| 1183 | reg = <0x01c28800 0x400>; | |
| 1184 | interrupts = <3>; | |
| 1185 | reg-shift = <2>; | |
| 1186 | reg-io-width = <4>; | |
| 9ff49ec7 | 1187 | clocks = <&apb1_gates 18>; |
| 76f14d0a MR |
1188 | status = "disabled"; |
| 1189 | }; | |
| 1190 | ||
| 69144e3b MR |
1191 | uart3: serial@01c28c00 { |
| 1192 | compatible = "snps,dw-apb-uart"; | |
| 1193 | reg = <0x01c28c00 0x400>; | |
| 1194 | interrupts = <4>; | |
| 1195 | reg-shift = <2>; | |
| 1196 | reg-io-width = <4>; | |
| 1197 | clocks = <&apb1_gates 19>; | |
| 1198 | status = "disabled"; | |
| 1199 | }; | |
| 1200 | ||
| 76f14d0a MR |
1201 | uart4: serial@01c29000 { |
| 1202 | compatible = "snps,dw-apb-uart"; | |
| 1203 | reg = <0x01c29000 0x400>; | |
| 1204 | interrupts = <17>; | |
| 1205 | reg-shift = <2>; | |
| 1206 | reg-io-width = <4>; | |
| 9ff49ec7 | 1207 | clocks = <&apb1_gates 20>; |
| 76f14d0a MR |
1208 | status = "disabled"; |
| 1209 | }; | |
| 1210 | ||
| 1211 | uart5: serial@01c29400 { | |
| 1212 | compatible = "snps,dw-apb-uart"; | |
| 1213 | reg = <0x01c29400 0x400>; | |
| 1214 | interrupts = <18>; | |
| 1215 | reg-shift = <2>; | |
| 1216 | reg-io-width = <4>; | |
| 9ff49ec7 | 1217 | clocks = <&apb1_gates 21>; |
| 76f14d0a MR |
1218 | status = "disabled"; |
| 1219 | }; | |
| 1220 | ||
| 1221 | uart6: serial@01c29800 { | |
| 1222 | compatible = "snps,dw-apb-uart"; | |
| 1223 | reg = <0x01c29800 0x400>; | |
| 1224 | interrupts = <19>; | |
| 1225 | reg-shift = <2>; | |
| 1226 | reg-io-width = <4>; | |
| 9ff49ec7 | 1227 | clocks = <&apb1_gates 22>; |
| 76f14d0a MR |
1228 | status = "disabled"; |
| 1229 | }; | |
| 1230 | ||
| 1231 | uart7: serial@01c29c00 { | |
| 1232 | compatible = "snps,dw-apb-uart"; | |
| 1233 | reg = <0x01c29c00 0x400>; | |
| 1234 | interrupts = <20>; | |
| 1235 | reg-shift = <2>; | |
| 1236 | reg-io-width = <4>; | |
| 9ff49ec7 | 1237 | clocks = <&apb1_gates 23>; |
| 76f14d0a MR |
1238 | status = "disabled"; |
| 1239 | }; | |
| f1741fda MR |
1240 | |
| 1241 | i2c0: i2c@01c2ac00 { | |
| d275545e | 1242 | compatible = "allwinner,sun4i-a10-i2c"; |
| f1741fda MR |
1243 | reg = <0x01c2ac00 0x400>; |
| 1244 | interrupts = <7>; | |
| 1245 | clocks = <&apb1_gates 0>; | |
| f1741fda | 1246 | status = "disabled"; |
| 60bbe316 HG |
1247 | #address-cells = <1>; |
| 1248 | #size-cells = <0>; | |
| f1741fda MR |
1249 | }; |
| 1250 | ||
| 1251 | i2c1: i2c@01c2b000 { | |
| d275545e | 1252 | compatible = "allwinner,sun4i-a10-i2c"; |
| f1741fda MR |
1253 | reg = <0x01c2b000 0x400>; |
| 1254 | interrupts = <8>; | |
| 1255 | clocks = <&apb1_gates 1>; | |
| f1741fda | 1256 | status = "disabled"; |
| 60bbe316 HG |
1257 | #address-cells = <1>; |
| 1258 | #size-cells = <0>; | |
| f1741fda MR |
1259 | }; |
| 1260 | ||
| 1261 | i2c2: i2c@01c2b400 { | |
| d275545e | 1262 | compatible = "allwinner,sun4i-a10-i2c"; |
| f1741fda MR |
1263 | reg = <0x01c2b400 0x400>; |
| 1264 | interrupts = <9>; | |
| 1265 | clocks = <&apb1_gates 2>; | |
| f1741fda | 1266 | status = "disabled"; |
| 60bbe316 HG |
1267 | #address-cells = <1>; |
| 1268 | #size-cells = <0>; | |
| f1741fda | 1269 | }; |
| 196654ae VP |
1270 | |
| 1271 | ps20: ps2@01c2a000 { | |
| 1272 | compatible = "allwinner,sun4i-a10-ps2"; | |
| 1273 | reg = <0x01c2a000 0x400>; | |
| 1274 | interrupts = <62>; | |
| 1275 | clocks = <&apb1_gates 6>; | |
| 1276 | status = "disabled"; | |
| 1277 | }; | |
| 1278 | ||
| 1279 | ps21: ps2@01c2a400 { | |
| 1280 | compatible = "allwinner,sun4i-a10-ps2"; | |
| 1281 | reg = <0x01c2a400 0x400>; | |
| 1282 | interrupts = <63>; | |
| 1283 | clocks = <&apb1_gates 7>; | |
| 1284 | status = "disabled"; | |
| 1285 | }; | |
| 874b4e45 | 1286 | }; |
| 7423d2d8 | 1287 | }; |