Commit | Line | Data |
---|---|---|
7423d2d8 SR |
1 | /* |
2 | * Copyright 2012 Stefan Roese | |
3 | * Stefan Roese <sr@denx.de> | |
4 | * | |
033ba3d7 MR |
5 | * This file is dual-licensed: you can use it either under the terms |
6 | * of the GPL or the X11 license, at your option. Note that this dual | |
7 | * licensing only applies to this file, and not this project as a | |
8 | * whole. | |
7423d2d8 | 9 | * |
033ba3d7 MR |
10 | * a) This library is free software; you can redistribute it and/or |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of the | |
13 | * License, or (at your option) any later version. | |
14 | * | |
15 | * This library is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
033ba3d7 MR |
20 | * Or, alternatively, |
21 | * | |
22 | * b) Permission is hereby granted, free of charge, to any person | |
23 | * obtaining a copy of this software and associated documentation | |
24 | * files (the "Software"), to deal in the Software without | |
25 | * restriction, including without limitation the rights to use, | |
26 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
27 | * sell copies of the Software, and to permit persons to whom the | |
28 | * Software is furnished to do so, subject to the following | |
29 | * conditions: | |
30 | * | |
31 | * The above copyright notice and this permission notice shall be | |
32 | * included in all copies or substantial portions of the Software. | |
33 | * | |
34 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
35 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
36 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
37 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
38 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
39 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
40 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
41 | * OTHER DEALINGS IN THE SOFTWARE. | |
7423d2d8 SR |
42 | */ |
43 | ||
71455701 | 44 | #include "skeleton.dtsi" |
7423d2d8 | 45 | |
541ce2ca CYT |
46 | #include <dt-bindings/thermal/thermal.h> |
47 | ||
b516fa5d | 48 | #include <dt-bindings/clock/sun4i-a10-pll2.h> |
1f9f6a78 | 49 | #include <dt-bindings/dma/sun4i-a10.h> |
092a0c3b | 50 | #include <dt-bindings/pinctrl/sun4i-a10.h> |
7423d2d8 SR |
51 | |
52 | / { | |
69144e3b MR |
53 | interrupt-parent = <&intc>; |
54 | ||
e751cce9 EL |
55 | aliases { |
56 | ethernet0 = &emac; | |
57 | }; | |
58 | ||
5790d4ee HG |
59 | chosen { |
60 | #address-cells = <1>; | |
61 | #size-cells = <1>; | |
62 | ranges; | |
63 | ||
a9f8cda3 | 64 | framebuffer@0 { |
d8cacaa3 MR |
65 | compatible = "allwinner,simple-framebuffer", |
66 | "simple-framebuffer"; | |
a9f8cda3 | 67 | allwinner,pipeline = "de_be0-lcd0-hdmi"; |
678e75d3 HG |
68 | clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, |
69 | <&ahb_gates 44>; | |
5790d4ee HG |
70 | status = "disabled"; |
71 | }; | |
8cedd662 HG |
72 | |
73 | framebuffer@1 { | |
d8cacaa3 MR |
74 | compatible = "allwinner,simple-framebuffer", |
75 | "simple-framebuffer"; | |
8cedd662 HG |
76 | allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi"; |
77 | clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, | |
78 | <&ahb_gates 44>, <&ahb_gates 46>; | |
79 | status = "disabled"; | |
80 | }; | |
fd18c7ea HG |
81 | |
82 | framebuffer@2 { | |
83 | compatible = "allwinner,simple-framebuffer", | |
84 | "simple-framebuffer"; | |
85 | allwinner,pipeline = "de_fe0-de_be0-lcd0"; | |
86 | clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>, | |
87 | <&ahb_gates 46>; | |
88 | status = "disabled"; | |
89 | }; | |
90 | ||
91 | framebuffer@3 { | |
92 | compatible = "allwinner,simple-framebuffer", | |
93 | "simple-framebuffer"; | |
94 | allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0"; | |
95 | clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>, | |
96 | <&ahb_gates 44>, <&ahb_gates 46>; | |
97 | status = "disabled"; | |
98 | }; | |
5790d4ee HG |
99 | }; |
100 | ||
69144e3b | 101 | cpus { |
8b2efa89 AB |
102 | #address-cells = <1>; |
103 | #size-cells = <0>; | |
7294be5d | 104 | cpu0: cpu@0 { |
14c44aa5 | 105 | device_type = "cpu"; |
69144e3b | 106 | compatible = "arm,cortex-a8"; |
14c44aa5 | 107 | reg = <0x0>; |
7294be5d CYT |
108 | clocks = <&cpu>; |
109 | clock-latency = <244144>; /* 8 32k periods */ | |
110 | operating-points = < | |
8358aada | 111 | /* kHz uV */ |
7294be5d | 112 | 1008000 1400000 |
8358aada MR |
113 | 912000 1350000 |
114 | 864000 1300000 | |
115 | 624000 1250000 | |
7294be5d CYT |
116 | >; |
117 | #cooling-cells = <2>; | |
118 | cooling-min-level = <0>; | |
370a9b5f | 119 | cooling-max-level = <3>; |
69144e3b MR |
120 | }; |
121 | }; | |
122 | ||
541ce2ca CYT |
123 | thermal-zones { |
124 | cpu_thermal { | |
125 | /* milliseconds */ | |
126 | polling-delay-passive = <250>; | |
127 | polling-delay = <1000>; | |
128 | thermal-sensors = <&rtp>; | |
129 | ||
130 | cooling-maps { | |
131 | map0 { | |
132 | trip = <&cpu_alert0>; | |
133 | cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
134 | }; | |
135 | }; | |
136 | ||
137 | trips { | |
138 | cpu_alert0: cpu_alert0 { | |
139 | /* milliCelsius */ | |
140 | temperature = <850000>; | |
141 | hysteresis = <2000>; | |
142 | type = "passive"; | |
143 | }; | |
144 | ||
145 | cpu_crit: cpu_crit { | |
146 | /* milliCelsius */ | |
147 | temperature = <100000>; | |
148 | hysteresis = <2000>; | |
149 | type = "critical"; | |
150 | }; | |
151 | }; | |
69144e3b MR |
152 | }; |
153 | }; | |
154 | ||
7423d2d8 SR |
155 | memory { |
156 | reg = <0x40000000 0x80000000>; | |
157 | }; | |
874b4e45 | 158 | |
69144e3b MR |
159 | clocks { |
160 | #address-cells = <1>; | |
161 | #size-cells = <1>; | |
162 | ranges; | |
163 | ||
164 | /* | |
165 | * This is a dummy clock, to be used as placeholder on | |
166 | * other mux clocks when a specific parent clock is not | |
167 | * yet implemented. It should be dropped when the driver | |
168 | * is complete. | |
169 | */ | |
170 | dummy: dummy { | |
171 | #clock-cells = <0>; | |
172 | compatible = "fixed-clock"; | |
173 | clock-frequency = <0>; | |
174 | }; | |
175 | ||
dfb12c0c | 176 | osc24M: clk@01c20050 { |
69144e3b | 177 | #clock-cells = <0>; |
bf6534a1 | 178 | compatible = "allwinner,sun4i-a10-osc-clk"; |
69144e3b | 179 | reg = <0x01c20050 0x4>; |
92fd6e06 | 180 | clock-frequency = <24000000>; |
dfb12c0c | 181 | clock-output-names = "osc24M"; |
69144e3b MR |
182 | }; |
183 | ||
dfb12c0c | 184 | osc32k: clk@0 { |
69144e3b MR |
185 | #clock-cells = <0>; |
186 | compatible = "fixed-clock"; | |
187 | clock-frequency = <32768>; | |
dfb12c0c | 188 | clock-output-names = "osc32k"; |
69144e3b MR |
189 | }; |
190 | ||
dfb12c0c | 191 | pll1: clk@01c20000 { |
69144e3b | 192 | #clock-cells = <0>; |
bf6534a1 | 193 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
69144e3b MR |
194 | reg = <0x01c20000 0x4>; |
195 | clocks = <&osc24M>; | |
dfb12c0c | 196 | clock-output-names = "pll1"; |
69144e3b MR |
197 | }; |
198 | ||
6ee93e12 MR |
199 | pll2: clk@01c20008 { |
200 | #clock-cells = <1>; | |
201 | compatible = "allwinner,sun4i-a10-pll2-clk"; | |
202 | reg = <0x01c20008 0x8>; | |
203 | clocks = <&osc24M>; | |
204 | clock-output-names = "pll2-1x", "pll2-2x", | |
205 | "pll2-4x", "pll2-8x"; | |
206 | }; | |
207 | ||
dfb12c0c | 208 | pll4: clk@01c20018 { |
ec5589f7 | 209 | #clock-cells = <0>; |
bf6534a1 | 210 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
ec5589f7 EL |
211 | reg = <0x01c20018 0x4>; |
212 | clocks = <&osc24M>; | |
dfb12c0c | 213 | clock-output-names = "pll4"; |
ec5589f7 EL |
214 | }; |
215 | ||
dfb12c0c | 216 | pll5: clk@01c20020 { |
c3e5e66b | 217 | #clock-cells = <1>; |
bf6534a1 | 218 | compatible = "allwinner,sun4i-a10-pll5-clk"; |
c3e5e66b EL |
219 | reg = <0x01c20020 0x4>; |
220 | clocks = <&osc24M>; | |
221 | clock-output-names = "pll5_ddr", "pll5_other"; | |
222 | }; | |
223 | ||
dfb12c0c | 224 | pll6: clk@01c20028 { |
c3e5e66b | 225 | #clock-cells = <1>; |
bf6534a1 | 226 | compatible = "allwinner,sun4i-a10-pll6-clk"; |
c3e5e66b EL |
227 | reg = <0x01c20028 0x4>; |
228 | clocks = <&osc24M>; | |
229 | clock-output-names = "pll6_sata", "pll6_other", "pll6"; | |
230 | }; | |
231 | ||
69144e3b MR |
232 | /* dummy is 200M */ |
233 | cpu: cpu@01c20054 { | |
234 | #clock-cells = <0>; | |
bf6534a1 | 235 | compatible = "allwinner,sun4i-a10-cpu-clk"; |
69144e3b MR |
236 | reg = <0x01c20054 0x4>; |
237 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; | |
dfb12c0c | 238 | clock-output-names = "cpu"; |
69144e3b MR |
239 | }; |
240 | ||
241 | axi: axi@01c20054 { | |
242 | #clock-cells = <0>; | |
bf6534a1 | 243 | compatible = "allwinner,sun4i-a10-axi-clk"; |
69144e3b MR |
244 | reg = <0x01c20054 0x4>; |
245 | clocks = <&cpu>; | |
dfb12c0c | 246 | clock-output-names = "axi"; |
69144e3b MR |
247 | }; |
248 | ||
dfb12c0c | 249 | axi_gates: clk@01c2005c { |
69144e3b | 250 | #clock-cells = <1>; |
bf6534a1 | 251 | compatible = "allwinner,sun4i-a10-axi-gates-clk"; |
69144e3b MR |
252 | reg = <0x01c2005c 0x4>; |
253 | clocks = <&axi>; | |
a3854006 | 254 | clock-indices = <0>; |
69144e3b MR |
255 | clock-output-names = "axi_dram"; |
256 | }; | |
257 | ||
258 | ahb: ahb@01c20054 { | |
259 | #clock-cells = <0>; | |
bf6534a1 | 260 | compatible = "allwinner,sun4i-a10-ahb-clk"; |
69144e3b MR |
261 | reg = <0x01c20054 0x4>; |
262 | clocks = <&axi>; | |
dfb12c0c | 263 | clock-output-names = "ahb"; |
69144e3b MR |
264 | }; |
265 | ||
dfb12c0c | 266 | ahb_gates: clk@01c20060 { |
69144e3b | 267 | #clock-cells = <1>; |
bf6534a1 | 268 | compatible = "allwinner,sun4i-a10-ahb-gates-clk"; |
69144e3b MR |
269 | reg = <0x01c20060 0x8>; |
270 | clocks = <&ahb>; | |
a3854006 MR |
271 | clock-indices = <0>, <1>, |
272 | <2>, <3>, | |
273 | <4>, <5>, <6>, | |
274 | <7>, <8>, <9>, | |
275 | <10>, <11>, <12>, | |
276 | <13>, <14>, <16>, | |
277 | <17>, <18>, <20>, | |
278 | <21>, <22>, <23>, | |
279 | <24>, <25>, <26>, | |
280 | <32>, <33>, <34>, | |
281 | <35>, <36>, <37>, | |
282 | <40>, <41>, <43>, | |
283 | <44>, <45>, | |
284 | <46>, <47>, | |
285 | <50>, <52>; | |
69144e3b | 286 | clock-output-names = "ahb_usb0", "ahb_ehci0", |
a3854006 MR |
287 | "ahb_ohci0", "ahb_ehci1", |
288 | "ahb_ohci1", "ahb_ss", "ahb_dma", | |
289 | "ahb_bist", "ahb_mmc0", "ahb_mmc1", | |
290 | "ahb_mmc2", "ahb_mmc3", "ahb_ms", | |
291 | "ahb_nand", "ahb_sdram", "ahb_ace", | |
292 | "ahb_emac", "ahb_ts", "ahb_spi0", | |
293 | "ahb_spi1", "ahb_spi2", "ahb_spi3", | |
294 | "ahb_pata", "ahb_sata", "ahb_gps", | |
295 | "ahb_ve", "ahb_tvd", "ahb_tve0", | |
296 | "ahb_tve1", "ahb_lcd0", "ahb_lcd1", | |
297 | "ahb_csi0", "ahb_csi1", "ahb_hdmi", | |
298 | "ahb_de_be0", "ahb_de_be1", | |
299 | "ahb_de_fe0", "ahb_de_fe1", | |
300 | "ahb_mp", "ahb_mali400"; | |
69144e3b MR |
301 | }; |
302 | ||
303 | apb0: apb0@01c20054 { | |
304 | #clock-cells = <0>; | |
bf6534a1 | 305 | compatible = "allwinner,sun4i-a10-apb0-clk"; |
69144e3b MR |
306 | reg = <0x01c20054 0x4>; |
307 | clocks = <&ahb>; | |
dfb12c0c | 308 | clock-output-names = "apb0"; |
69144e3b MR |
309 | }; |
310 | ||
dfb12c0c | 311 | apb0_gates: clk@01c20068 { |
69144e3b | 312 | #clock-cells = <1>; |
bf6534a1 | 313 | compatible = "allwinner,sun4i-a10-apb0-gates-clk"; |
69144e3b MR |
314 | reg = <0x01c20068 0x4>; |
315 | clocks = <&apb0>; | |
a3854006 MR |
316 | clock-indices = <0>, <1>, |
317 | <2>, <3>, | |
318 | <5>, <6>, | |
319 | <7>, <10>; | |
69144e3b | 320 | clock-output-names = "apb0_codec", "apb0_spdif", |
a3854006 MR |
321 | "apb0_ac97", "apb0_iis", |
322 | "apb0_pio", "apb0_ir0", | |
323 | "apb0_ir1", "apb0_keypad"; | |
69144e3b MR |
324 | }; |
325 | ||
acbcc0f0 | 326 | apb1: clk@01c20058 { |
69144e3b | 327 | #clock-cells = <0>; |
bf6534a1 | 328 | compatible = "allwinner,sun4i-a10-apb1-clk"; |
69144e3b | 329 | reg = <0x01c20058 0x4>; |
acbcc0f0 | 330 | clocks = <&osc24M>, <&pll6 1>, <&osc32k>; |
dfb12c0c | 331 | clock-output-names = "apb1"; |
69144e3b MR |
332 | }; |
333 | ||
dfb12c0c | 334 | apb1_gates: clk@01c2006c { |
69144e3b | 335 | #clock-cells = <1>; |
bf6534a1 | 336 | compatible = "allwinner,sun4i-a10-apb1-gates-clk"; |
69144e3b MR |
337 | reg = <0x01c2006c 0x4>; |
338 | clocks = <&apb1>; | |
a3854006 MR |
339 | clock-indices = <0>, <1>, |
340 | <2>, <4>, | |
341 | <5>, <6>, | |
342 | <7>, <16>, | |
343 | <17>, <18>, | |
344 | <19>, <20>, | |
345 | <21>, <22>, | |
346 | <23>; | |
69144e3b | 347 | clock-output-names = "apb1_i2c0", "apb1_i2c1", |
a3854006 MR |
348 | "apb1_i2c2", "apb1_can", |
349 | "apb1_scr", "apb1_ps20", | |
350 | "apb1_ps21", "apb1_uart0", | |
351 | "apb1_uart1", "apb1_uart2", | |
352 | "apb1_uart3", "apb1_uart4", | |
353 | "apb1_uart5", "apb1_uart6", | |
354 | "apb1_uart7"; | |
69144e3b | 355 | }; |
4b756ffb EL |
356 | |
357 | nand_clk: clk@01c20080 { | |
358 | #clock-cells = <0>; | |
bf6534a1 | 359 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
360 | reg = <0x01c20080 0x4>; |
361 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
362 | clock-output-names = "nand"; | |
363 | }; | |
364 | ||
365 | ms_clk: clk@01c20084 { | |
366 | #clock-cells = <0>; | |
bf6534a1 | 367 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
368 | reg = <0x01c20084 0x4>; |
369 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
370 | clock-output-names = "ms"; | |
371 | }; | |
372 | ||
373 | mmc0_clk: clk@01c20088 { | |
d8c3a392 MR |
374 | #clock-cells = <1>; |
375 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
4b756ffb EL |
376 | reg = <0x01c20088 0x4>; |
377 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
d8c3a392 MR |
378 | clock-output-names = "mmc0", |
379 | "mmc0_output", | |
380 | "mmc0_sample"; | |
4b756ffb EL |
381 | }; |
382 | ||
383 | mmc1_clk: clk@01c2008c { | |
d8c3a392 MR |
384 | #clock-cells = <1>; |
385 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
4b756ffb EL |
386 | reg = <0x01c2008c 0x4>; |
387 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
d8c3a392 MR |
388 | clock-output-names = "mmc1", |
389 | "mmc1_output", | |
390 | "mmc1_sample"; | |
4b756ffb EL |
391 | }; |
392 | ||
393 | mmc2_clk: clk@01c20090 { | |
d8c3a392 MR |
394 | #clock-cells = <1>; |
395 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
4b756ffb EL |
396 | reg = <0x01c20090 0x4>; |
397 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
d8c3a392 MR |
398 | clock-output-names = "mmc2", |
399 | "mmc2_output", | |
400 | "mmc2_sample"; | |
4b756ffb EL |
401 | }; |
402 | ||
403 | mmc3_clk: clk@01c20094 { | |
d8c3a392 MR |
404 | #clock-cells = <1>; |
405 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
4b756ffb EL |
406 | reg = <0x01c20094 0x4>; |
407 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
d8c3a392 MR |
408 | clock-output-names = "mmc3", |
409 | "mmc3_output", | |
410 | "mmc3_sample"; | |
4b756ffb EL |
411 | }; |
412 | ||
413 | ts_clk: clk@01c20098 { | |
414 | #clock-cells = <0>; | |
bf6534a1 | 415 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
416 | reg = <0x01c20098 0x4>; |
417 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
418 | clock-output-names = "ts"; | |
419 | }; | |
420 | ||
421 | ss_clk: clk@01c2009c { | |
422 | #clock-cells = <0>; | |
bf6534a1 | 423 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
424 | reg = <0x01c2009c 0x4>; |
425 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
426 | clock-output-names = "ss"; | |
427 | }; | |
428 | ||
429 | spi0_clk: clk@01c200a0 { | |
430 | #clock-cells = <0>; | |
bf6534a1 | 431 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
432 | reg = <0x01c200a0 0x4>; |
433 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
434 | clock-output-names = "spi0"; | |
435 | }; | |
436 | ||
437 | spi1_clk: clk@01c200a4 { | |
438 | #clock-cells = <0>; | |
bf6534a1 | 439 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
440 | reg = <0x01c200a4 0x4>; |
441 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
442 | clock-output-names = "spi1"; | |
443 | }; | |
444 | ||
445 | spi2_clk: clk@01c200a8 { | |
446 | #clock-cells = <0>; | |
bf6534a1 | 447 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
448 | reg = <0x01c200a8 0x4>; |
449 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
450 | clock-output-names = "spi2"; | |
451 | }; | |
452 | ||
453 | pata_clk: clk@01c200ac { | |
454 | #clock-cells = <0>; | |
bf6534a1 | 455 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
456 | reg = <0x01c200ac 0x4>; |
457 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
458 | clock-output-names = "pata"; | |
459 | }; | |
460 | ||
461 | ir0_clk: clk@01c200b0 { | |
462 | #clock-cells = <0>; | |
bf6534a1 | 463 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
464 | reg = <0x01c200b0 0x4>; |
465 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
466 | clock-output-names = "ir0"; | |
467 | }; | |
468 | ||
469 | ir1_clk: clk@01c200b4 { | |
470 | #clock-cells = <0>; | |
bf6534a1 | 471 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
472 | reg = <0x01c200b4 0x4>; |
473 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
474 | clock-output-names = "ir1"; | |
475 | }; | |
476 | ||
0076c8bd RB |
477 | usb_clk: clk@01c200cc { |
478 | #clock-cells = <1>; | |
8358aada | 479 | #reset-cells = <1>; |
0076c8bd RB |
480 | compatible = "allwinner,sun4i-a10-usb-clk"; |
481 | reg = <0x01c200cc 0x4>; | |
482 | clocks = <&pll6 1>; | |
d8cacaa3 MR |
483 | clock-output-names = "usb_ohci0", "usb_ohci1", |
484 | "usb_phy"; | |
0076c8bd RB |
485 | }; |
486 | ||
4b756ffb EL |
487 | spi3_clk: clk@01c200d4 { |
488 | #clock-cells = <0>; | |
bf6534a1 | 489 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
490 | reg = <0x01c200d4 0x4>; |
491 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
492 | clock-output-names = "spi3"; | |
493 | }; | |
b516fa5d MR |
494 | |
495 | codec_clk: clk@01c20140 { | |
496 | #clock-cells = <0>; | |
497 | compatible = "allwinner,sun4i-a10-codec-clk"; | |
498 | reg = <0x01c20140 0x4>; | |
499 | clocks = <&pll2 SUN4I_A10_PLL2_1X>; | |
500 | clock-output-names = "codec"; | |
501 | }; | |
69144e3b MR |
502 | }; |
503 | ||
b74aec1a | 504 | soc@01c00000 { |
69144e3b MR |
505 | compatible = "simple-bus"; |
506 | #address-cells = <1>; | |
507 | #size-cells = <1>; | |
69144e3b MR |
508 | ranges; |
509 | ||
1fbc1517 MR |
510 | sram-controller@01c00000 { |
511 | compatible = "allwinner,sun4i-a10-sram-controller"; | |
512 | reg = <0x01c00000 0x30>; | |
513 | #address-cells = <1>; | |
514 | #size-cells = <1>; | |
515 | ranges; | |
516 | ||
517 | sram_a: sram@00000000 { | |
518 | compatible = "mmio-sram"; | |
519 | reg = <0x00000000 0xc000>; | |
520 | #address-cells = <1>; | |
521 | #size-cells = <1>; | |
522 | ranges = <0 0x00000000 0xc000>; | |
523 | ||
524 | emac_sram: sram-section@8000 { | |
525 | compatible = "allwinner,sun4i-a10-sram-a3-a4"; | |
526 | reg = <0x8000 0x4000>; | |
527 | status = "disabled"; | |
528 | }; | |
529 | }; | |
530 | ||
531 | sram_d: sram@00010000 { | |
532 | compatible = "mmio-sram"; | |
533 | reg = <0x00010000 0x1000>; | |
534 | #address-cells = <1>; | |
535 | #size-cells = <1>; | |
536 | ranges = <0 0x00010000 0x1000>; | |
537 | ||
538 | otg_sram: sram-section@0000 { | |
539 | compatible = "allwinner,sun4i-a10-sram-d"; | |
540 | reg = <0x0000 0x1000>; | |
541 | status = "disabled"; | |
542 | }; | |
543 | }; | |
544 | }; | |
545 | ||
1324f532 EL |
546 | dma: dma-controller@01c02000 { |
547 | compatible = "allwinner,sun4i-a10-dma"; | |
548 | reg = <0x01c02000 0x1000>; | |
549 | interrupts = <27>; | |
550 | clocks = <&ahb_gates 6>; | |
551 | #dma-cells = <2>; | |
552 | }; | |
553 | ||
65918e26 MR |
554 | spi0: spi@01c05000 { |
555 | compatible = "allwinner,sun4i-a10-spi"; | |
556 | reg = <0x01c05000 0x1000>; | |
557 | interrupts = <10>; | |
558 | clocks = <&ahb_gates 20>, <&spi0_clk>; | |
559 | clock-names = "ahb", "mod"; | |
1f9f6a78 MR |
560 | dmas = <&dma SUN4I_DMA_DEDICATED 27>, |
561 | <&dma SUN4I_DMA_DEDICATED 26>; | |
4192ff81 | 562 | dma-names = "rx", "tx"; |
65918e26 MR |
563 | status = "disabled"; |
564 | #address-cells = <1>; | |
565 | #size-cells = <0>; | |
566 | }; | |
567 | ||
568 | spi1: spi@01c06000 { | |
569 | compatible = "allwinner,sun4i-a10-spi"; | |
570 | reg = <0x01c06000 0x1000>; | |
571 | interrupts = <11>; | |
572 | clocks = <&ahb_gates 21>, <&spi1_clk>; | |
573 | clock-names = "ahb", "mod"; | |
1f9f6a78 MR |
574 | dmas = <&dma SUN4I_DMA_DEDICATED 9>, |
575 | <&dma SUN4I_DMA_DEDICATED 8>; | |
4192ff81 | 576 | dma-names = "rx", "tx"; |
65918e26 MR |
577 | status = "disabled"; |
578 | #address-cells = <1>; | |
579 | #size-cells = <0>; | |
580 | }; | |
581 | ||
e38afcb3 | 582 | emac: ethernet@01c0b000 { |
1c70e099 | 583 | compatible = "allwinner,sun4i-a10-emac"; |
e38afcb3 MR |
584 | reg = <0x01c0b000 0x1000>; |
585 | interrupts = <55>; | |
586 | clocks = <&ahb_gates 17>; | |
1fbc1517 | 587 | allwinner,sram = <&emac_sram 1>; |
e38afcb3 MR |
588 | status = "disabled"; |
589 | }; | |
590 | ||
92395f56 | 591 | mdio: mdio@01c0b080 { |
1c70e099 | 592 | compatible = "allwinner,sun4i-a10-mdio"; |
e38afcb3 MR |
593 | reg = <0x01c0b080 0x14>; |
594 | status = "disabled"; | |
595 | #address-cells = <1>; | |
596 | #size-cells = <0>; | |
597 | }; | |
598 | ||
b258b369 DL |
599 | mmc0: mmc@01c0f000 { |
600 | compatible = "allwinner,sun4i-a10-mmc"; | |
601 | reg = <0x01c0f000 0x1000>; | |
d8c3a392 MR |
602 | clocks = <&ahb_gates 8>, |
603 | <&mmc0_clk 0>, | |
604 | <&mmc0_clk 1>, | |
605 | <&mmc0_clk 2>; | |
606 | clock-names = "ahb", | |
607 | "mmc", | |
608 | "output", | |
609 | "sample"; | |
b258b369 DL |
610 | interrupts = <32>; |
611 | status = "disabled"; | |
4c1bb9c3 HG |
612 | #address-cells = <1>; |
613 | #size-cells = <0>; | |
b258b369 DL |
614 | }; |
615 | ||
616 | mmc1: mmc@01c10000 { | |
617 | compatible = "allwinner,sun4i-a10-mmc"; | |
618 | reg = <0x01c10000 0x1000>; | |
d8c3a392 MR |
619 | clocks = <&ahb_gates 9>, |
620 | <&mmc1_clk 0>, | |
621 | <&mmc1_clk 1>, | |
622 | <&mmc1_clk 2>; | |
623 | clock-names = "ahb", | |
624 | "mmc", | |
625 | "output", | |
626 | "sample"; | |
b258b369 DL |
627 | interrupts = <33>; |
628 | status = "disabled"; | |
4c1bb9c3 HG |
629 | #address-cells = <1>; |
630 | #size-cells = <0>; | |
b258b369 DL |
631 | }; |
632 | ||
633 | mmc2: mmc@01c11000 { | |
634 | compatible = "allwinner,sun4i-a10-mmc"; | |
635 | reg = <0x01c11000 0x1000>; | |
d8c3a392 MR |
636 | clocks = <&ahb_gates 10>, |
637 | <&mmc2_clk 0>, | |
638 | <&mmc2_clk 1>, | |
639 | <&mmc2_clk 2>; | |
640 | clock-names = "ahb", | |
641 | "mmc", | |
642 | "output", | |
643 | "sample"; | |
b258b369 DL |
644 | interrupts = <34>; |
645 | status = "disabled"; | |
4c1bb9c3 HG |
646 | #address-cells = <1>; |
647 | #size-cells = <0>; | |
b258b369 DL |
648 | }; |
649 | ||
650 | mmc3: mmc@01c12000 { | |
651 | compatible = "allwinner,sun4i-a10-mmc"; | |
652 | reg = <0x01c12000 0x1000>; | |
d8c3a392 MR |
653 | clocks = <&ahb_gates 11>, |
654 | <&mmc3_clk 0>, | |
655 | <&mmc3_clk 1>, | |
656 | <&mmc3_clk 2>; | |
657 | clock-names = "ahb", | |
658 | "mmc", | |
659 | "output", | |
660 | "sample"; | |
b258b369 DL |
661 | interrupts = <35>; |
662 | status = "disabled"; | |
4c1bb9c3 HG |
663 | #address-cells = <1>; |
664 | #size-cells = <0>; | |
b258b369 DL |
665 | }; |
666 | ||
ce65037f HG |
667 | usb_otg: usb@01c13000 { |
668 | compatible = "allwinner,sun4i-a10-musb"; | |
669 | reg = <0x01c13000 0x0400>; | |
670 | clocks = <&ahb_gates 0>; | |
671 | interrupts = <38>; | |
672 | interrupt-names = "mc"; | |
673 | phys = <&usbphy 0>; | |
674 | phy-names = "usb"; | |
675 | extcon = <&usbphy 0>; | |
676 | allwinner,sram = <&otg_sram 1>; | |
677 | status = "disabled"; | |
678 | }; | |
679 | ||
6ab1ce24 RB |
680 | usbphy: phy@01c13400 { |
681 | #phy-cells = <1>; | |
682 | compatible = "allwinner,sun4i-a10-usb-phy"; | |
683 | reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; | |
684 | reg-names = "phy_ctrl", "pmu1", "pmu2"; | |
685 | clocks = <&usb_clk 8>; | |
686 | clock-names = "usb_phy"; | |
4dba4185 CYT |
687 | resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>; |
688 | reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; | |
6ab1ce24 RB |
689 | status = "disabled"; |
690 | }; | |
691 | ||
692 | ehci0: usb@01c14000 { | |
693 | compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; | |
694 | reg = <0x01c14000 0x100>; | |
695 | interrupts = <39>; | |
696 | clocks = <&ahb_gates 1>; | |
697 | phys = <&usbphy 1>; | |
698 | phy-names = "usb"; | |
699 | status = "disabled"; | |
700 | }; | |
701 | ||
702 | ohci0: usb@01c14400 { | |
703 | compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; | |
704 | reg = <0x01c14400 0x100>; | |
705 | interrupts = <64>; | |
706 | clocks = <&usb_clk 6>, <&ahb_gates 2>; | |
707 | phys = <&usbphy 1>; | |
708 | phy-names = "usb"; | |
709 | status = "disabled"; | |
710 | }; | |
711 | ||
56ba8c58 LC |
712 | crypto: crypto-engine@01c15000 { |
713 | compatible = "allwinner,sun4i-a10-crypto"; | |
714 | reg = <0x01c15000 0x1000>; | |
715 | interrupts = <86>; | |
716 | clocks = <&ahb_gates 5>, <&ss_clk>; | |
717 | clock-names = "ahb", "mod"; | |
718 | }; | |
719 | ||
65918e26 MR |
720 | spi2: spi@01c17000 { |
721 | compatible = "allwinner,sun4i-a10-spi"; | |
722 | reg = <0x01c17000 0x1000>; | |
723 | interrupts = <12>; | |
724 | clocks = <&ahb_gates 22>, <&spi2_clk>; | |
725 | clock-names = "ahb", "mod"; | |
1f9f6a78 MR |
726 | dmas = <&dma SUN4I_DMA_DEDICATED 29>, |
727 | <&dma SUN4I_DMA_DEDICATED 28>; | |
4192ff81 | 728 | dma-names = "rx", "tx"; |
65918e26 MR |
729 | status = "disabled"; |
730 | #address-cells = <1>; | |
731 | #size-cells = <0>; | |
732 | }; | |
733 | ||
248bd1e2 OS |
734 | ahci: sata@01c18000 { |
735 | compatible = "allwinner,sun4i-a10-ahci"; | |
736 | reg = <0x01c18000 0x1000>; | |
737 | interrupts = <56>; | |
738 | clocks = <&pll6 0>, <&ahb_gates 25>; | |
739 | status = "disabled"; | |
740 | }; | |
741 | ||
6ab1ce24 RB |
742 | ehci1: usb@01c1c000 { |
743 | compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; | |
744 | reg = <0x01c1c000 0x100>; | |
745 | interrupts = <40>; | |
746 | clocks = <&ahb_gates 3>; | |
747 | phys = <&usbphy 2>; | |
748 | phy-names = "usb"; | |
749 | status = "disabled"; | |
750 | }; | |
751 | ||
752 | ohci1: usb@01c1c400 { | |
753 | compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; | |
754 | reg = <0x01c1c400 0x100>; | |
755 | interrupts = <65>; | |
756 | clocks = <&usb_clk 7>, <&ahb_gates 4>; | |
757 | phys = <&usbphy 2>; | |
758 | phy-names = "usb"; | |
759 | status = "disabled"; | |
760 | }; | |
761 | ||
65918e26 MR |
762 | spi3: spi@01c1f000 { |
763 | compatible = "allwinner,sun4i-a10-spi"; | |
764 | reg = <0x01c1f000 0x1000>; | |
765 | interrupts = <50>; | |
766 | clocks = <&ahb_gates 23>, <&spi3_clk>; | |
767 | clock-names = "ahb", "mod"; | |
1f9f6a78 MR |
768 | dmas = <&dma SUN4I_DMA_DEDICATED 31>, |
769 | <&dma SUN4I_DMA_DEDICATED 30>; | |
4192ff81 | 770 | dma-names = "rx", "tx"; |
65918e26 MR |
771 | status = "disabled"; |
772 | #address-cells = <1>; | |
773 | #size-cells = <0>; | |
774 | }; | |
775 | ||
69144e3b | 776 | intc: interrupt-controller@01c20400 { |
09504a7d | 777 | compatible = "allwinner,sun4i-a10-ic"; |
69144e3b MR |
778 | reg = <0x01c20400 0x400>; |
779 | interrupt-controller; | |
780 | #interrupt-cells = <1>; | |
781 | }; | |
782 | ||
e10911e1 | 783 | pio: pinctrl@01c20800 { |
874b4e45 MR |
784 | compatible = "allwinner,sun4i-a10-pinctrl"; |
785 | reg = <0x01c20800 0x400>; | |
39138bc6 | 786 | interrupts = <28>; |
36386d6e | 787 | clocks = <&apb0_gates 5>; |
e10911e1 | 788 | gpio-controller; |
39138bc6 | 789 | interrupt-controller; |
b03e0816 | 790 | #interrupt-cells = <3>; |
e10911e1 | 791 | #gpio-cells = <3>; |
581981be | 792 | |
1d5726e9 AB |
793 | pwm0_pins_a: pwm0@0 { |
794 | allwinner,pins = "PB2"; | |
795 | allwinner,function = "pwm"; | |
092a0c3b MR |
796 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
797 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
1d5726e9 AB |
798 | }; |
799 | ||
800 | pwm1_pins_a: pwm1@0 { | |
801 | allwinner,pins = "PI3"; | |
802 | allwinner,function = "pwm"; | |
092a0c3b MR |
803 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
804 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
1d5726e9 AB |
805 | }; |
806 | ||
581981be MR |
807 | uart0_pins_a: uart0@0 { |
808 | allwinner,pins = "PB22", "PB23"; | |
809 | allwinner,function = "uart0"; | |
092a0c3b MR |
810 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
811 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
581981be MR |
812 | }; |
813 | ||
814 | uart0_pins_b: uart0@1 { | |
815 | allwinner,pins = "PF2", "PF4"; | |
816 | allwinner,function = "uart0"; | |
092a0c3b MR |
817 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
818 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
581981be MR |
819 | }; |
820 | ||
821 | uart1_pins_a: uart1@0 { | |
822 | allwinner,pins = "PA10", "PA11"; | |
823 | allwinner,function = "uart1"; | |
092a0c3b MR |
824 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
825 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
581981be | 826 | }; |
27cce4ff MR |
827 | |
828 | i2c0_pins_a: i2c0@0 { | |
829 | allwinner,pins = "PB0", "PB1"; | |
830 | allwinner,function = "i2c0"; | |
092a0c3b MR |
831 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
832 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
27cce4ff MR |
833 | }; |
834 | ||
835 | i2c1_pins_a: i2c1@0 { | |
836 | allwinner,pins = "PB18", "PB19"; | |
837 | allwinner,function = "i2c1"; | |
092a0c3b MR |
838 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
839 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
27cce4ff MR |
840 | }; |
841 | ||
842 | i2c2_pins_a: i2c2@0 { | |
843 | allwinner,pins = "PB20", "PB21"; | |
844 | allwinner,function = "i2c2"; | |
092a0c3b MR |
845 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
846 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
27cce4ff | 847 | }; |
496322bc | 848 | |
b21da664 MR |
849 | emac_pins_a: emac0@0 { |
850 | allwinner,pins = "PA0", "PA1", "PA2", | |
851 | "PA3", "PA4", "PA5", "PA6", | |
852 | "PA7", "PA8", "PA9", "PA10", | |
853 | "PA11", "PA12", "PA13", "PA14", | |
854 | "PA15", "PA16"; | |
855 | allwinner,function = "emac"; | |
092a0c3b MR |
856 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
857 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
b21da664 | 858 | }; |
b5f86a3a HG |
859 | |
860 | mmc0_pins_a: mmc0@0 { | |
d8cacaa3 MR |
861 | allwinner,pins = "PF0", "PF1", "PF2", |
862 | "PF3", "PF4", "PF5"; | |
b5f86a3a | 863 | allwinner,function = "mmc0"; |
092a0c3b MR |
864 | allwinner,drive = <SUN4I_PINCTRL_30_MA>; |
865 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
b5f86a3a HG |
866 | }; |
867 | ||
868 | mmc0_cd_pin_reference_design: mmc0_cd_pin@0 { | |
869 | allwinner,pins = "PH1"; | |
870 | allwinner,function = "gpio_in"; | |
092a0c3b MR |
871 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
872 | allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; | |
b5f86a3a | 873 | }; |
a4e1099a | 874 | |
469a22e6 MC |
875 | ir0_rx_pins_a: ir0@0 { |
876 | allwinner,pins = "PB4"; | |
a4e1099a | 877 | allwinner,function = "ir0"; |
092a0c3b MR |
878 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
879 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
a4e1099a HG |
880 | }; |
881 | ||
469a22e6 MC |
882 | ir0_tx_pins_a: ir0@1 { |
883 | allwinner,pins = "PB3"; | |
884 | allwinner,function = "ir0"; | |
885 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
886 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
887 | }; | |
888 | ||
889 | ir1_rx_pins_a: ir1@0 { | |
890 | allwinner,pins = "PB23"; | |
891 | allwinner,function = "ir1"; | |
892 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
893 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
894 | }; | |
895 | ||
896 | ir1_tx_pins_a: ir1@1 { | |
897 | allwinner,pins = "PB22"; | |
a4e1099a | 898 | allwinner,function = "ir1"; |
092a0c3b MR |
899 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
900 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
a4e1099a | 901 | }; |
ec66d0bb AG |
902 | |
903 | spi0_pins_a: spi0@0 { | |
f3022c6c MR |
904 | allwinner,pins = "PI11", "PI12", "PI13"; |
905 | allwinner,function = "spi0"; | |
906 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
907 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
908 | }; | |
909 | ||
910 | spi0_cs0_pins_a: spi0_cs0@0 { | |
911 | allwinner,pins = "PI10"; | |
ec66d0bb | 912 | allwinner,function = "spi0"; |
092a0c3b MR |
913 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
914 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
ec66d0bb AG |
915 | }; |
916 | ||
917 | spi1_pins_a: spi1@0 { | |
f3022c6c MR |
918 | allwinner,pins = "PI17", "PI18", "PI19"; |
919 | allwinner,function = "spi1"; | |
920 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
921 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
922 | }; | |
923 | ||
924 | spi1_cs0_pins_a: spi1_cs0@0 { | |
925 | allwinner,pins = "PI16"; | |
ec66d0bb | 926 | allwinner,function = "spi1"; |
092a0c3b MR |
927 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
928 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
ec66d0bb AG |
929 | }; |
930 | ||
931 | spi2_pins_a: spi2@0 { | |
f3022c6c | 932 | allwinner,pins = "PC20", "PC21", "PC22"; |
ec66d0bb | 933 | allwinner,function = "spi2"; |
092a0c3b MR |
934 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
935 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
ec66d0bb AG |
936 | }; |
937 | ||
938 | spi2_pins_b: spi2@1 { | |
f3022c6c MR |
939 | allwinner,pins = "PB15", "PB16", "PB17"; |
940 | allwinner,function = "spi2"; | |
941 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
942 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
943 | }; | |
944 | ||
945 | spi2_cs0_pins_a: spi2_cs0@0 { | |
946 | allwinner,pins = "PC19"; | |
947 | allwinner,function = "spi2"; | |
948 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
949 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
950 | }; | |
951 | ||
952 | spi2_cs0_pins_b: spi2_cs0@1 { | |
953 | allwinner,pins = "PB14"; | |
ec66d0bb | 954 | allwinner,function = "spi2"; |
092a0c3b MR |
955 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
956 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
ec66d0bb | 957 | }; |
1e8d1567 VP |
958 | |
959 | ps20_pins_a: ps20@0 { | |
960 | allwinner,pins = "PI20", "PI21"; | |
961 | allwinner,function = "ps2"; | |
962 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
963 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
964 | }; | |
965 | ||
966 | ps21_pins_a: ps21@0 { | |
967 | allwinner,pins = "PH12", "PH13"; | |
968 | allwinner,function = "ps2"; | |
969 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
970 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
a4e1099a | 971 | }; |
874b4e45 | 972 | }; |
89b3c99f | 973 | |
69144e3b | 974 | timer@01c20c00 { |
b4f26440 | 975 | compatible = "allwinner,sun4i-a10-timer"; |
69144e3b MR |
976 | reg = <0x01c20c00 0x90>; |
977 | interrupts = <22>; | |
978 | clocks = <&osc24M>; | |
979 | }; | |
980 | ||
981 | wdt: watchdog@01c20c90 { | |
ca5d04d9 | 982 | compatible = "allwinner,sun4i-a10-wdt"; |
69144e3b MR |
983 | reg = <0x01c20c90 0x10>; |
984 | }; | |
985 | ||
b5d905c7 | 986 | rtc: rtc@01c20d00 { |
5fc4bc89 | 987 | compatible = "allwinner,sun4i-a10-rtc"; |
b5d905c7 CC |
988 | reg = <0x01c20d00 0x20>; |
989 | interrupts = <24>; | |
990 | }; | |
991 | ||
4b57a395 AB |
992 | pwm: pwm@01c20e00 { |
993 | compatible = "allwinner,sun4i-a10-pwm"; | |
994 | reg = <0x01c20e00 0xc>; | |
995 | clocks = <&osc24M>; | |
996 | #pwm-cells = <3>; | |
997 | status = "disabled"; | |
998 | }; | |
999 | ||
a4e1099a HG |
1000 | ir0: ir@01c21800 { |
1001 | compatible = "allwinner,sun4i-a10-ir"; | |
1002 | clocks = <&apb0_gates 6>, <&ir0_clk>; | |
1003 | clock-names = "apb", "ir"; | |
1004 | interrupts = <5>; | |
1005 | reg = <0x01c21800 0x40>; | |
1006 | status = "disabled"; | |
1007 | }; | |
1008 | ||
1009 | ir1: ir@01c21c00 { | |
1010 | compatible = "allwinner,sun4i-a10-ir"; | |
1011 | clocks = <&apb0_gates 7>, <&ir1_clk>; | |
1012 | clock-names = "apb", "ir"; | |
1013 | interrupts = <6>; | |
1014 | reg = <0x01c21c00 0x40>; | |
1015 | status = "disabled"; | |
1016 | }; | |
1017 | ||
b0512e15 HG |
1018 | lradc: lradc@01c22800 { |
1019 | compatible = "allwinner,sun4i-a10-lradc-keys"; | |
1020 | reg = <0x01c22800 0x100>; | |
1021 | interrupts = <31>; | |
1022 | status = "disabled"; | |
1023 | }; | |
1024 | ||
bcf88450 MC |
1025 | codec: codec@01c22c00 { |
1026 | #sound-dai-cells = <0>; | |
1027 | compatible = "allwinner,sun4i-a10-codec"; | |
1028 | reg = <0x01c22c00 0x40>; | |
1029 | interrupts = <30>; | |
1030 | clocks = <&apb0_gates 0>, <&codec_clk>; | |
1031 | clock-names = "apb", "codec"; | |
1032 | dmas = <&dma SUN4I_DMA_NORMAL 19>, | |
1033 | <&dma SUN4I_DMA_NORMAL 19>; | |
1034 | dma-names = "rx", "tx"; | |
1035 | status = "disabled"; | |
1036 | }; | |
1037 | ||
2bad969f | 1038 | sid: eeprom@01c23800 { |
043d56ee | 1039 | compatible = "allwinner,sun4i-a10-sid"; |
2bad969f OS |
1040 | reg = <0x01c23800 0x10>; |
1041 | }; | |
1042 | ||
57c8839c | 1043 | rtp: rtp@01c25000 { |
40dd8f3b | 1044 | compatible = "allwinner,sun4i-a10-ts"; |
57c8839c HG |
1045 | reg = <0x01c25000 0x100>; |
1046 | interrupts = <29>; | |
41e7afb1 | 1047 | #thermal-sensor-cells = <0>; |
57c8839c HG |
1048 | }; |
1049 | ||
89b3c99f MR |
1050 | uart0: serial@01c28000 { |
1051 | compatible = "snps,dw-apb-uart"; | |
1052 | reg = <0x01c28000 0x400>; | |
1053 | interrupts = <1>; | |
1054 | reg-shift = <2>; | |
1055 | reg-io-width = <4>; | |
9ff49ec7 | 1056 | clocks = <&apb1_gates 16>; |
89b3c99f MR |
1057 | status = "disabled"; |
1058 | }; | |
76f14d0a | 1059 | |
69144e3b MR |
1060 | uart1: serial@01c28400 { |
1061 | compatible = "snps,dw-apb-uart"; | |
1062 | reg = <0x01c28400 0x400>; | |
1063 | interrupts = <2>; | |
1064 | reg-shift = <2>; | |
1065 | reg-io-width = <4>; | |
1066 | clocks = <&apb1_gates 17>; | |
1067 | status = "disabled"; | |
1068 | }; | |
1069 | ||
76f14d0a MR |
1070 | uart2: serial@01c28800 { |
1071 | compatible = "snps,dw-apb-uart"; | |
1072 | reg = <0x01c28800 0x400>; | |
1073 | interrupts = <3>; | |
1074 | reg-shift = <2>; | |
1075 | reg-io-width = <4>; | |
9ff49ec7 | 1076 | clocks = <&apb1_gates 18>; |
76f14d0a MR |
1077 | status = "disabled"; |
1078 | }; | |
1079 | ||
69144e3b MR |
1080 | uart3: serial@01c28c00 { |
1081 | compatible = "snps,dw-apb-uart"; | |
1082 | reg = <0x01c28c00 0x400>; | |
1083 | interrupts = <4>; | |
1084 | reg-shift = <2>; | |
1085 | reg-io-width = <4>; | |
1086 | clocks = <&apb1_gates 19>; | |
1087 | status = "disabled"; | |
1088 | }; | |
1089 | ||
76f14d0a MR |
1090 | uart4: serial@01c29000 { |
1091 | compatible = "snps,dw-apb-uart"; | |
1092 | reg = <0x01c29000 0x400>; | |
1093 | interrupts = <17>; | |
1094 | reg-shift = <2>; | |
1095 | reg-io-width = <4>; | |
9ff49ec7 | 1096 | clocks = <&apb1_gates 20>; |
76f14d0a MR |
1097 | status = "disabled"; |
1098 | }; | |
1099 | ||
1100 | uart5: serial@01c29400 { | |
1101 | compatible = "snps,dw-apb-uart"; | |
1102 | reg = <0x01c29400 0x400>; | |
1103 | interrupts = <18>; | |
1104 | reg-shift = <2>; | |
1105 | reg-io-width = <4>; | |
9ff49ec7 | 1106 | clocks = <&apb1_gates 21>; |
76f14d0a MR |
1107 | status = "disabled"; |
1108 | }; | |
1109 | ||
1110 | uart6: serial@01c29800 { | |
1111 | compatible = "snps,dw-apb-uart"; | |
1112 | reg = <0x01c29800 0x400>; | |
1113 | interrupts = <19>; | |
1114 | reg-shift = <2>; | |
1115 | reg-io-width = <4>; | |
9ff49ec7 | 1116 | clocks = <&apb1_gates 22>; |
76f14d0a MR |
1117 | status = "disabled"; |
1118 | }; | |
1119 | ||
1120 | uart7: serial@01c29c00 { | |
1121 | compatible = "snps,dw-apb-uart"; | |
1122 | reg = <0x01c29c00 0x400>; | |
1123 | interrupts = <20>; | |
1124 | reg-shift = <2>; | |
1125 | reg-io-width = <4>; | |
9ff49ec7 | 1126 | clocks = <&apb1_gates 23>; |
76f14d0a MR |
1127 | status = "disabled"; |
1128 | }; | |
f1741fda MR |
1129 | |
1130 | i2c0: i2c@01c2ac00 { | |
d275545e | 1131 | compatible = "allwinner,sun4i-a10-i2c"; |
f1741fda MR |
1132 | reg = <0x01c2ac00 0x400>; |
1133 | interrupts = <7>; | |
1134 | clocks = <&apb1_gates 0>; | |
f1741fda | 1135 | status = "disabled"; |
60bbe316 HG |
1136 | #address-cells = <1>; |
1137 | #size-cells = <0>; | |
f1741fda MR |
1138 | }; |
1139 | ||
1140 | i2c1: i2c@01c2b000 { | |
d275545e | 1141 | compatible = "allwinner,sun4i-a10-i2c"; |
f1741fda MR |
1142 | reg = <0x01c2b000 0x400>; |
1143 | interrupts = <8>; | |
1144 | clocks = <&apb1_gates 1>; | |
f1741fda | 1145 | status = "disabled"; |
60bbe316 HG |
1146 | #address-cells = <1>; |
1147 | #size-cells = <0>; | |
f1741fda MR |
1148 | }; |
1149 | ||
1150 | i2c2: i2c@01c2b400 { | |
d275545e | 1151 | compatible = "allwinner,sun4i-a10-i2c"; |
f1741fda MR |
1152 | reg = <0x01c2b400 0x400>; |
1153 | interrupts = <9>; | |
1154 | clocks = <&apb1_gates 2>; | |
f1741fda | 1155 | status = "disabled"; |
60bbe316 HG |
1156 | #address-cells = <1>; |
1157 | #size-cells = <0>; | |
f1741fda | 1158 | }; |
196654ae VP |
1159 | |
1160 | ps20: ps2@01c2a000 { | |
1161 | compatible = "allwinner,sun4i-a10-ps2"; | |
1162 | reg = <0x01c2a000 0x400>; | |
1163 | interrupts = <62>; | |
1164 | clocks = <&apb1_gates 6>; | |
1165 | status = "disabled"; | |
1166 | }; | |
1167 | ||
1168 | ps21: ps2@01c2a400 { | |
1169 | compatible = "allwinner,sun4i-a10-ps2"; | |
1170 | reg = <0x01c2a400 0x400>; | |
1171 | interrupts = <63>; | |
1172 | clocks = <&apb1_gates 7>; | |
1173 | status = "disabled"; | |
1174 | }; | |
874b4e45 | 1175 | }; |
7423d2d8 | 1176 | }; |