projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 7423d2d8 SR |
1 | /* |
| 2 | * Copyright 2012 Stefan Roese | |
| 3 | * Stefan Roese <sr@denx.de> | |
| 4 | * | |
| 5 | * The code contained herein is licensed under the GNU General Public | |
| 6 | * License. You may obtain a copy of the GNU General Public License | |
| 7 | * Version 2 or later at the following locations: | |
| 8 | * | |
| 9 | * http://www.opensource.org/licenses/gpl-license.html | |
| 10 | * http://www.gnu.org/copyleft/gpl.html | |
| 11 | */ | |
| 12 | ||
| 69144e3b | 13 | /include/ "skeleton.dtsi" |
| 7423d2d8 SR |
14 | |
| 15 | / { | |
| 69144e3b MR |
16 | interrupt-parent = <&intc>; |
| 17 | ||
| 18 | cpus { | |
| 8b2efa89 AB |
19 | #address-cells = <1>; |
| 20 | #size-cells = <0>; | |
| 69144e3b | 21 | cpu@0 { |
| 14c44aa5 | 22 | device_type = "cpu"; |
| 69144e3b | 23 | compatible = "arm,cortex-a8"; |
| 14c44aa5 | 24 | reg = <0x0>; |
| 69144e3b MR |
25 | }; |
| 26 | }; | |
| 27 | ||
| 7423d2d8 SR |
28 | memory { |
| 29 | reg = <0x40000000 0x80000000>; | |
| 30 | }; | |
| 874b4e45 | 31 | |
| 69144e3b MR |
32 | clocks { |
| 33 | #address-cells = <1>; | |
| 34 | #size-cells = <1>; | |
| 35 | ranges; | |
| 36 | ||
| 37 | /* | |
| 38 | * This is a dummy clock, to be used as placeholder on | |
| 39 | * other mux clocks when a specific parent clock is not | |
| 40 | * yet implemented. It should be dropped when the driver | |
| 41 | * is complete. | |
| 42 | */ | |
| 43 | dummy: dummy { | |
| 44 | #clock-cells = <0>; | |
| 45 | compatible = "fixed-clock"; | |
| 46 | clock-frequency = <0>; | |
| 47 | }; | |
| 48 | ||
| 69144e3b MR |
49 | osc24M: osc24M@01c20050 { |
| 50 | #clock-cells = <0>; | |
| 51 | compatible = "allwinner,sun4i-osc-clk"; | |
| 52 | reg = <0x01c20050 0x4>; | |
| 92fd6e06 | 53 | clock-frequency = <24000000>; |
| 69144e3b MR |
54 | }; |
| 55 | ||
| 56 | osc32k: osc32k { | |
| 57 | #clock-cells = <0>; | |
| 58 | compatible = "fixed-clock"; | |
| 59 | clock-frequency = <32768>; | |
| 60 | }; | |
| 61 | ||
| 62 | pll1: pll1@01c20000 { | |
| 63 | #clock-cells = <0>; | |
| 64 | compatible = "allwinner,sun4i-pll1-clk"; | |
| 65 | reg = <0x01c20000 0x4>; | |
| 66 | clocks = <&osc24M>; | |
| 67 | }; | |
| 68 | ||
| 69 | /* dummy is 200M */ | |
| 70 | cpu: cpu@01c20054 { | |
| 71 | #clock-cells = <0>; | |
| 72 | compatible = "allwinner,sun4i-cpu-clk"; | |
| 73 | reg = <0x01c20054 0x4>; | |
| 74 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; | |
| 75 | }; | |
| 76 | ||
| 77 | axi: axi@01c20054 { | |
| 78 | #clock-cells = <0>; | |
| 79 | compatible = "allwinner,sun4i-axi-clk"; | |
| 80 | reg = <0x01c20054 0x4>; | |
| 81 | clocks = <&cpu>; | |
| 82 | }; | |
| 83 | ||
| 84 | axi_gates: axi_gates@01c2005c { | |
| 85 | #clock-cells = <1>; | |
| 86 | compatible = "allwinner,sun4i-axi-gates-clk"; | |
| 87 | reg = <0x01c2005c 0x4>; | |
| 88 | clocks = <&axi>; | |
| 89 | clock-output-names = "axi_dram"; | |
| 90 | }; | |
| 91 | ||
| 92 | ahb: ahb@01c20054 { | |
| 93 | #clock-cells = <0>; | |
| 94 | compatible = "allwinner,sun4i-ahb-clk"; | |
| 95 | reg = <0x01c20054 0x4>; | |
| 96 | clocks = <&axi>; | |
| 97 | }; | |
| 98 | ||
| 99 | ahb_gates: ahb_gates@01c20060 { | |
| 100 | #clock-cells = <1>; | |
| 101 | compatible = "allwinner,sun4i-ahb-gates-clk"; | |
| 102 | reg = <0x01c20060 0x8>; | |
| 103 | clocks = <&ahb>; | |
| 104 | clock-output-names = "ahb_usb0", "ahb_ehci0", | |
| 105 | "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss", | |
| 106 | "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1", | |
| 107 | "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand", | |
| 108 | "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts", | |
| 109 | "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3", | |
| 110 | "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve", | |
| 111 | "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0", | |
| 112 | "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi", | |
| 113 | "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0", | |
| 114 | "ahb_de_fe1", "ahb_mp", "ahb_mali400"; | |
| 115 | }; | |
| 116 | ||
| 117 | apb0: apb0@01c20054 { | |
| 118 | #clock-cells = <0>; | |
| 119 | compatible = "allwinner,sun4i-apb0-clk"; | |
| 120 | reg = <0x01c20054 0x4>; | |
| 121 | clocks = <&ahb>; | |
| 122 | }; | |
| 123 | ||
| 124 | apb0_gates: apb0_gates@01c20068 { | |
| 125 | #clock-cells = <1>; | |
| 126 | compatible = "allwinner,sun4i-apb0-gates-clk"; | |
| 127 | reg = <0x01c20068 0x4>; | |
| 128 | clocks = <&apb0>; | |
| 129 | clock-output-names = "apb0_codec", "apb0_spdif", | |
| 130 | "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0", | |
| 131 | "apb0_ir1", "apb0_keypad"; | |
| 132 | }; | |
| 133 | ||
| 134 | /* dummy is pll62 */ | |
| 135 | apb1_mux: apb1_mux@01c20058 { | |
| 136 | #clock-cells = <0>; | |
| 137 | compatible = "allwinner,sun4i-apb1-mux-clk"; | |
| 138 | reg = <0x01c20058 0x4>; | |
| 139 | clocks = <&osc24M>, <&dummy>, <&osc32k>; | |
| 140 | }; | |
| 141 | ||
| 142 | apb1: apb1@01c20058 { | |
| 143 | #clock-cells = <0>; | |
| 144 | compatible = "allwinner,sun4i-apb1-clk"; | |
| 145 | reg = <0x01c20058 0x4>; | |
| 146 | clocks = <&apb1_mux>; | |
| 147 | }; | |
| 148 | ||
| 149 | apb1_gates: apb1_gates@01c2006c { | |
| 150 | #clock-cells = <1>; | |
| 151 | compatible = "allwinner,sun4i-apb1-gates-clk"; | |
| 152 | reg = <0x01c2006c 0x4>; | |
| 153 | clocks = <&apb1>; | |
| 154 | clock-output-names = "apb1_i2c0", "apb1_i2c1", | |
| 155 | "apb1_i2c2", "apb1_can", "apb1_scr", | |
| 156 | "apb1_ps20", "apb1_ps21", "apb1_uart0", | |
| 157 | "apb1_uart1", "apb1_uart2", "apb1_uart3", | |
| 158 | "apb1_uart4", "apb1_uart5", "apb1_uart6", | |
| 159 | "apb1_uart7"; | |
| 160 | }; | |
| 161 | }; | |
| 162 | ||
| 163 | soc@01c20000 { | |
| 164 | compatible = "simple-bus"; | |
| 165 | #address-cells = <1>; | |
| 166 | #size-cells = <1>; | |
| 167 | reg = <0x01c20000 0x300000>; | |
| 168 | ranges; | |
| 169 | ||
| e38afcb3 MR |
170 | emac: ethernet@01c0b000 { |
| 171 | compatible = "allwinner,sun4i-emac"; | |
| 172 | reg = <0x01c0b000 0x1000>; | |
| 173 | interrupts = <55>; | |
| 174 | clocks = <&ahb_gates 17>; | |
| 175 | status = "disabled"; | |
| 176 | }; | |
| 177 | ||
| 178 | mdio@01c0b080 { | |
| 179 | compatible = "allwinner,sun4i-mdio"; | |
| 180 | reg = <0x01c0b080 0x14>; | |
| 181 | status = "disabled"; | |
| 182 | #address-cells = <1>; | |
| 183 | #size-cells = <0>; | |
| 184 | }; | |
| 185 | ||
| 69144e3b | 186 | intc: interrupt-controller@01c20400 { |
| 6def126d | 187 | compatible = "allwinner,sun4i-ic"; |
| 69144e3b MR |
188 | reg = <0x01c20400 0x400>; |
| 189 | interrupt-controller; | |
| 190 | #interrupt-cells = <1>; | |
| 191 | }; | |
| 192 | ||
| e10911e1 | 193 | pio: pinctrl@01c20800 { |
| 874b4e45 MR |
194 | compatible = "allwinner,sun4i-a10-pinctrl"; |
| 195 | reg = <0x01c20800 0x400>; | |
| 39138bc6 | 196 | interrupts = <28>; |
| 36386d6e | 197 | clocks = <&apb0_gates 5>; |
| e10911e1 | 198 | gpio-controller; |
| 39138bc6 | 199 | interrupt-controller; |
| 874b4e45 MR |
200 | #address-cells = <1>; |
| 201 | #size-cells = <0>; | |
| e10911e1 | 202 | #gpio-cells = <3>; |
| 581981be MR |
203 | |
| 204 | uart0_pins_a: uart0@0 { | |
| 205 | allwinner,pins = "PB22", "PB23"; | |
| 206 | allwinner,function = "uart0"; | |
| 207 | allwinner,drive = <0>; | |
| 208 | allwinner,pull = <0>; | |
| 209 | }; | |
| 210 | ||
| 211 | uart0_pins_b: uart0@1 { | |
| 212 | allwinner,pins = "PF2", "PF4"; | |
| 213 | allwinner,function = "uart0"; | |
| 214 | allwinner,drive = <0>; | |
| 215 | allwinner,pull = <0>; | |
| 216 | }; | |
| 217 | ||
| 218 | uart1_pins_a: uart1@0 { | |
| 219 | allwinner,pins = "PA10", "PA11"; | |
| 220 | allwinner,function = "uart1"; | |
| 221 | allwinner,drive = <0>; | |
| 222 | allwinner,pull = <0>; | |
| 223 | }; | |
| 27cce4ff MR |
224 | |
| 225 | i2c0_pins_a: i2c0@0 { | |
| 226 | allwinner,pins = "PB0", "PB1"; | |
| 227 | allwinner,function = "i2c0"; | |
| 228 | allwinner,drive = <0>; | |
| 229 | allwinner,pull = <0>; | |
| 230 | }; | |
| 231 | ||
| 232 | i2c1_pins_a: i2c1@0 { | |
| 233 | allwinner,pins = "PB18", "PB19"; | |
| 234 | allwinner,function = "i2c1"; | |
| 235 | allwinner,drive = <0>; | |
| 236 | allwinner,pull = <0>; | |
| 237 | }; | |
| 238 | ||
| 239 | i2c2_pins_a: i2c2@0 { | |
| 240 | allwinner,pins = "PB20", "PB21"; | |
| 241 | allwinner,function = "i2c2"; | |
| 242 | allwinner,drive = <0>; | |
| 243 | allwinner,pull = <0>; | |
| 244 | }; | |
| 496322bc | 245 | |
| b21da664 MR |
246 | emac_pins_a: emac0@0 { |
| 247 | allwinner,pins = "PA0", "PA1", "PA2", | |
| 248 | "PA3", "PA4", "PA5", "PA6", | |
| 249 | "PA7", "PA8", "PA9", "PA10", | |
| 250 | "PA11", "PA12", "PA13", "PA14", | |
| 251 | "PA15", "PA16"; | |
| 252 | allwinner,function = "emac"; | |
| 253 | allwinner,drive = <0>; | |
| 254 | allwinner,pull = <0>; | |
| 255 | }; | |
| 874b4e45 | 256 | }; |
| 89b3c99f | 257 | |
| 69144e3b | 258 | timer@01c20c00 { |
| b6e1a53b | 259 | compatible = "allwinner,sun4i-timer"; |
| 69144e3b MR |
260 | reg = <0x01c20c00 0x90>; |
| 261 | interrupts = <22>; | |
| 262 | clocks = <&osc24M>; | |
| 263 | }; | |
| 264 | ||
| 265 | wdt: watchdog@01c20c90 { | |
| 0b19b7c2 | 266 | compatible = "allwinner,sun4i-wdt"; |
| 69144e3b MR |
267 | reg = <0x01c20c90 0x10>; |
| 268 | }; | |
| 269 | ||
| 89b3c99f MR |
270 | uart0: serial@01c28000 { |
| 271 | compatible = "snps,dw-apb-uart"; | |
| 272 | reg = <0x01c28000 0x400>; | |
| 273 | interrupts = <1>; | |
| 274 | reg-shift = <2>; | |
| 275 | reg-io-width = <4>; | |
| 9ff49ec7 | 276 | clocks = <&apb1_gates 16>; |
| 89b3c99f MR |
277 | status = "disabled"; |
| 278 | }; | |
| 76f14d0a | 279 | |
| 69144e3b MR |
280 | uart1: serial@01c28400 { |
| 281 | compatible = "snps,dw-apb-uart"; | |
| 282 | reg = <0x01c28400 0x400>; | |
| 283 | interrupts = <2>; | |
| 284 | reg-shift = <2>; | |
| 285 | reg-io-width = <4>; | |
| 286 | clocks = <&apb1_gates 17>; | |
| 287 | status = "disabled"; | |
| 288 | }; | |
| 289 | ||
| 76f14d0a MR |
290 | uart2: serial@01c28800 { |
| 291 | compatible = "snps,dw-apb-uart"; | |
| 292 | reg = <0x01c28800 0x400>; | |
| 293 | interrupts = <3>; | |
| 294 | reg-shift = <2>; | |
| 295 | reg-io-width = <4>; | |
| 9ff49ec7 | 296 | clocks = <&apb1_gates 18>; |
| 76f14d0a MR |
297 | status = "disabled"; |
| 298 | }; | |
| 299 | ||
| 69144e3b MR |
300 | uart3: serial@01c28c00 { |
| 301 | compatible = "snps,dw-apb-uart"; | |
| 302 | reg = <0x01c28c00 0x400>; | |
| 303 | interrupts = <4>; | |
| 304 | reg-shift = <2>; | |
| 305 | reg-io-width = <4>; | |
| 306 | clocks = <&apb1_gates 19>; | |
| 307 | status = "disabled"; | |
| 308 | }; | |
| 309 | ||
| 76f14d0a MR |
310 | uart4: serial@01c29000 { |
| 311 | compatible = "snps,dw-apb-uart"; | |
| 312 | reg = <0x01c29000 0x400>; | |
| 313 | interrupts = <17>; | |
| 314 | reg-shift = <2>; | |
| 315 | reg-io-width = <4>; | |
| 9ff49ec7 | 316 | clocks = <&apb1_gates 20>; |
| 76f14d0a MR |
317 | status = "disabled"; |
| 318 | }; | |
| 319 | ||
| 320 | uart5: serial@01c29400 { | |
| 321 | compatible = "snps,dw-apb-uart"; | |
| 322 | reg = <0x01c29400 0x400>; | |
| 323 | interrupts = <18>; | |
| 324 | reg-shift = <2>; | |
| 325 | reg-io-width = <4>; | |
| 9ff49ec7 | 326 | clocks = <&apb1_gates 21>; |
| 76f14d0a MR |
327 | status = "disabled"; |
| 328 | }; | |
| 329 | ||
| 330 | uart6: serial@01c29800 { | |
| 331 | compatible = "snps,dw-apb-uart"; | |
| 332 | reg = <0x01c29800 0x400>; | |
| 333 | interrupts = <19>; | |
| 334 | reg-shift = <2>; | |
| 335 | reg-io-width = <4>; | |
| 9ff49ec7 | 336 | clocks = <&apb1_gates 22>; |
| 76f14d0a MR |
337 | status = "disabled"; |
| 338 | }; | |
| 339 | ||
| 340 | uart7: serial@01c29c00 { | |
| 341 | compatible = "snps,dw-apb-uart"; | |
| 342 | reg = <0x01c29c00 0x400>; | |
| 343 | interrupts = <20>; | |
| 344 | reg-shift = <2>; | |
| 345 | reg-io-width = <4>; | |
| 9ff49ec7 | 346 | clocks = <&apb1_gates 23>; |
| 76f14d0a MR |
347 | status = "disabled"; |
| 348 | }; | |
| f1741fda MR |
349 | |
| 350 | i2c0: i2c@01c2ac00 { | |
| 351 | compatible = "allwinner,sun4i-i2c"; | |
| 352 | reg = <0x01c2ac00 0x400>; | |
| 353 | interrupts = <7>; | |
| 354 | clocks = <&apb1_gates 0>; | |
| 355 | clock-frequency = <100000>; | |
| 356 | status = "disabled"; | |
| 357 | }; | |
| 358 | ||
| 359 | i2c1: i2c@01c2b000 { | |
| 360 | compatible = "allwinner,sun4i-i2c"; | |
| 361 | reg = <0x01c2b000 0x400>; | |
| 362 | interrupts = <8>; | |
| 363 | clocks = <&apb1_gates 1>; | |
| 364 | clock-frequency = <100000>; | |
| 365 | status = "disabled"; | |
| 366 | }; | |
| 367 | ||
| 368 | i2c2: i2c@01c2b400 { | |
| 369 | compatible = "allwinner,sun4i-i2c"; | |
| 370 | reg = <0x01c2b400 0x400>; | |
| 371 | interrupts = <9>; | |
| 372 | clocks = <&apb1_gates 2>; | |
| 373 | clock-frequency = <100000>; | |
| 374 | status = "disabled"; | |
| 375 | }; | |
| 874b4e45 | 376 | }; |
| 7423d2d8 | 377 | }; |