ARM: sunxi: dt: Add sunxi-common-regulators include file
[deliverable/linux.git] / arch / arm / boot / dts / sun4i-a10.dtsi
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1/*
2 * Copyright 2012 Stefan Roese
3 * Stefan Roese <sr@denx.de>
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
69144e3b 13/include/ "skeleton.dtsi"
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14
15/ {
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16 interrupt-parent = <&intc>;
17
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18 aliases {
19 ethernet0 = &emac;
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20 serial0 = &uart0;
21 serial1 = &uart1;
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22 serial2 = &uart2;
23 serial3 = &uart3;
24 serial4 = &uart4;
25 serial5 = &uart5;
26 serial6 = &uart6;
27 serial7 = &uart7;
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28 };
29
69144e3b 30 cpus {
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31 #address-cells = <1>;
32 #size-cells = <0>;
69144e3b 33 cpu@0 {
14c44aa5 34 device_type = "cpu";
69144e3b 35 compatible = "arm,cortex-a8";
14c44aa5 36 reg = <0x0>;
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37 };
38 };
39
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40 memory {
41 reg = <0x40000000 0x80000000>;
42 };
874b4e45 43
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44 clocks {
45 #address-cells = <1>;
46 #size-cells = <1>;
47 ranges;
48
49 /*
50 * This is a dummy clock, to be used as placeholder on
51 * other mux clocks when a specific parent clock is not
52 * yet implemented. It should be dropped when the driver
53 * is complete.
54 */
55 dummy: dummy {
56 #clock-cells = <0>;
57 compatible = "fixed-clock";
58 clock-frequency = <0>;
59 };
60
dfb12c0c 61 osc24M: clk@01c20050 {
69144e3b 62 #clock-cells = <0>;
bf6534a1 63 compatible = "allwinner,sun4i-a10-osc-clk";
69144e3b 64 reg = <0x01c20050 0x4>;
92fd6e06 65 clock-frequency = <24000000>;
dfb12c0c 66 clock-output-names = "osc24M";
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67 };
68
dfb12c0c 69 osc32k: clk@0 {
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70 #clock-cells = <0>;
71 compatible = "fixed-clock";
72 clock-frequency = <32768>;
dfb12c0c 73 clock-output-names = "osc32k";
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74 };
75
dfb12c0c 76 pll1: clk@01c20000 {
69144e3b 77 #clock-cells = <0>;
bf6534a1 78 compatible = "allwinner,sun4i-a10-pll1-clk";
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79 reg = <0x01c20000 0x4>;
80 clocks = <&osc24M>;
dfb12c0c 81 clock-output-names = "pll1";
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82 };
83
dfb12c0c 84 pll4: clk@01c20018 {
ec5589f7 85 #clock-cells = <0>;
bf6534a1 86 compatible = "allwinner,sun4i-a10-pll1-clk";
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87 reg = <0x01c20018 0x4>;
88 clocks = <&osc24M>;
dfb12c0c 89 clock-output-names = "pll4";
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90 };
91
dfb12c0c 92 pll5: clk@01c20020 {
c3e5e66b 93 #clock-cells = <1>;
bf6534a1 94 compatible = "allwinner,sun4i-a10-pll5-clk";
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95 reg = <0x01c20020 0x4>;
96 clocks = <&osc24M>;
97 clock-output-names = "pll5_ddr", "pll5_other";
98 };
99
dfb12c0c 100 pll6: clk@01c20028 {
c3e5e66b 101 #clock-cells = <1>;
bf6534a1 102 compatible = "allwinner,sun4i-a10-pll6-clk";
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103 reg = <0x01c20028 0x4>;
104 clocks = <&osc24M>;
105 clock-output-names = "pll6_sata", "pll6_other", "pll6";
106 };
107
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108 /* dummy is 200M */
109 cpu: cpu@01c20054 {
110 #clock-cells = <0>;
bf6534a1 111 compatible = "allwinner,sun4i-a10-cpu-clk";
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112 reg = <0x01c20054 0x4>;
113 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
dfb12c0c 114 clock-output-names = "cpu";
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115 };
116
117 axi: axi@01c20054 {
118 #clock-cells = <0>;
bf6534a1 119 compatible = "allwinner,sun4i-a10-axi-clk";
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120 reg = <0x01c20054 0x4>;
121 clocks = <&cpu>;
dfb12c0c 122 clock-output-names = "axi";
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123 };
124
dfb12c0c 125 axi_gates: clk@01c2005c {
69144e3b 126 #clock-cells = <1>;
bf6534a1 127 compatible = "allwinner,sun4i-a10-axi-gates-clk";
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128 reg = <0x01c2005c 0x4>;
129 clocks = <&axi>;
130 clock-output-names = "axi_dram";
131 };
132
133 ahb: ahb@01c20054 {
134 #clock-cells = <0>;
bf6534a1 135 compatible = "allwinner,sun4i-a10-ahb-clk";
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136 reg = <0x01c20054 0x4>;
137 clocks = <&axi>;
dfb12c0c 138 clock-output-names = "ahb";
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139 };
140
dfb12c0c 141 ahb_gates: clk@01c20060 {
69144e3b 142 #clock-cells = <1>;
bf6534a1 143 compatible = "allwinner,sun4i-a10-ahb-gates-clk";
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144 reg = <0x01c20060 0x8>;
145 clocks = <&ahb>;
146 clock-output-names = "ahb_usb0", "ahb_ehci0",
147 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
148 "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
149 "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
150 "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
151 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
152 "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
153 "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
154 "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
155 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
156 "ahb_de_fe1", "ahb_mp", "ahb_mali400";
157 };
158
159 apb0: apb0@01c20054 {
160 #clock-cells = <0>;
bf6534a1 161 compatible = "allwinner,sun4i-a10-apb0-clk";
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162 reg = <0x01c20054 0x4>;
163 clocks = <&ahb>;
dfb12c0c 164 clock-output-names = "apb0";
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165 };
166
dfb12c0c 167 apb0_gates: clk@01c20068 {
69144e3b 168 #clock-cells = <1>;
bf6534a1 169 compatible = "allwinner,sun4i-a10-apb0-gates-clk";
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170 reg = <0x01c20068 0x4>;
171 clocks = <&apb0>;
172 clock-output-names = "apb0_codec", "apb0_spdif",
173 "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
174 "apb0_ir1", "apb0_keypad";
175 };
176
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177 apb1_mux: apb1_mux@01c20058 {
178 #clock-cells = <0>;
bf6534a1 179 compatible = "allwinner,sun4i-a10-apb1-mux-clk";
69144e3b 180 reg = <0x01c20058 0x4>;
c3e5e66b 181 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
dfb12c0c 182 clock-output-names = "apb1_mux";
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183 };
184
185 apb1: apb1@01c20058 {
186 #clock-cells = <0>;
bf6534a1 187 compatible = "allwinner,sun4i-a10-apb1-clk";
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188 reg = <0x01c20058 0x4>;
189 clocks = <&apb1_mux>;
dfb12c0c 190 clock-output-names = "apb1";
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191 };
192
dfb12c0c 193 apb1_gates: clk@01c2006c {
69144e3b 194 #clock-cells = <1>;
bf6534a1 195 compatible = "allwinner,sun4i-a10-apb1-gates-clk";
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196 reg = <0x01c2006c 0x4>;
197 clocks = <&apb1>;
198 clock-output-names = "apb1_i2c0", "apb1_i2c1",
199 "apb1_i2c2", "apb1_can", "apb1_scr",
200 "apb1_ps20", "apb1_ps21", "apb1_uart0",
201 "apb1_uart1", "apb1_uart2", "apb1_uart3",
202 "apb1_uart4", "apb1_uart5", "apb1_uart6",
203 "apb1_uart7";
204 };
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205
206 nand_clk: clk@01c20080 {
207 #clock-cells = <0>;
bf6534a1 208 compatible = "allwinner,sun4i-a10-mod0-clk";
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209 reg = <0x01c20080 0x4>;
210 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
211 clock-output-names = "nand";
212 };
213
214 ms_clk: clk@01c20084 {
215 #clock-cells = <0>;
bf6534a1 216 compatible = "allwinner,sun4i-a10-mod0-clk";
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217 reg = <0x01c20084 0x4>;
218 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
219 clock-output-names = "ms";
220 };
221
222 mmc0_clk: clk@01c20088 {
223 #clock-cells = <0>;
bf6534a1 224 compatible = "allwinner,sun4i-a10-mod0-clk";
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225 reg = <0x01c20088 0x4>;
226 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
227 clock-output-names = "mmc0";
228 };
229
230 mmc1_clk: clk@01c2008c {
231 #clock-cells = <0>;
bf6534a1 232 compatible = "allwinner,sun4i-a10-mod0-clk";
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233 reg = <0x01c2008c 0x4>;
234 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
235 clock-output-names = "mmc1";
236 };
237
238 mmc2_clk: clk@01c20090 {
239 #clock-cells = <0>;
bf6534a1 240 compatible = "allwinner,sun4i-a10-mod0-clk";
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241 reg = <0x01c20090 0x4>;
242 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
243 clock-output-names = "mmc2";
244 };
245
246 mmc3_clk: clk@01c20094 {
247 #clock-cells = <0>;
bf6534a1 248 compatible = "allwinner,sun4i-a10-mod0-clk";
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249 reg = <0x01c20094 0x4>;
250 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
251 clock-output-names = "mmc3";
252 };
253
254 ts_clk: clk@01c20098 {
255 #clock-cells = <0>;
bf6534a1 256 compatible = "allwinner,sun4i-a10-mod0-clk";
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257 reg = <0x01c20098 0x4>;
258 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
259 clock-output-names = "ts";
260 };
261
262 ss_clk: clk@01c2009c {
263 #clock-cells = <0>;
bf6534a1 264 compatible = "allwinner,sun4i-a10-mod0-clk";
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265 reg = <0x01c2009c 0x4>;
266 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
267 clock-output-names = "ss";
268 };
269
270 spi0_clk: clk@01c200a0 {
271 #clock-cells = <0>;
bf6534a1 272 compatible = "allwinner,sun4i-a10-mod0-clk";
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273 reg = <0x01c200a0 0x4>;
274 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
275 clock-output-names = "spi0";
276 };
277
278 spi1_clk: clk@01c200a4 {
279 #clock-cells = <0>;
bf6534a1 280 compatible = "allwinner,sun4i-a10-mod0-clk";
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281 reg = <0x01c200a4 0x4>;
282 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
283 clock-output-names = "spi1";
284 };
285
286 spi2_clk: clk@01c200a8 {
287 #clock-cells = <0>;
bf6534a1 288 compatible = "allwinner,sun4i-a10-mod0-clk";
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289 reg = <0x01c200a8 0x4>;
290 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
291 clock-output-names = "spi2";
292 };
293
294 pata_clk: clk@01c200ac {
295 #clock-cells = <0>;
bf6534a1 296 compatible = "allwinner,sun4i-a10-mod0-clk";
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297 reg = <0x01c200ac 0x4>;
298 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
299 clock-output-names = "pata";
300 };
301
302 ir0_clk: clk@01c200b0 {
303 #clock-cells = <0>;
bf6534a1 304 compatible = "allwinner,sun4i-a10-mod0-clk";
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305 reg = <0x01c200b0 0x4>;
306 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
307 clock-output-names = "ir0";
308 };
309
310 ir1_clk: clk@01c200b4 {
311 #clock-cells = <0>;
bf6534a1 312 compatible = "allwinner,sun4i-a10-mod0-clk";
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313 reg = <0x01c200b4 0x4>;
314 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
315 clock-output-names = "ir1";
316 };
317
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318 usb_clk: clk@01c200cc {
319 #clock-cells = <1>;
320 #reset-cells = <1>;
321 compatible = "allwinner,sun4i-a10-usb-clk";
322 reg = <0x01c200cc 0x4>;
323 clocks = <&pll6 1>;
324 clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
325 };
326
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327 spi3_clk: clk@01c200d4 {
328 #clock-cells = <0>;
bf6534a1 329 compatible = "allwinner,sun4i-a10-mod0-clk";
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330 reg = <0x01c200d4 0x4>;
331 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
332 clock-output-names = "spi3";
333 };
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334 };
335
b74aec1a 336 soc@01c00000 {
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337 compatible = "simple-bus";
338 #address-cells = <1>;
339 #size-cells = <1>;
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340 ranges;
341
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342 spi0: spi@01c05000 {
343 compatible = "allwinner,sun4i-a10-spi";
344 reg = <0x01c05000 0x1000>;
345 interrupts = <10>;
346 clocks = <&ahb_gates 20>, <&spi0_clk>;
347 clock-names = "ahb", "mod";
348 status = "disabled";
349 #address-cells = <1>;
350 #size-cells = <0>;
351 };
352
353 spi1: spi@01c06000 {
354 compatible = "allwinner,sun4i-a10-spi";
355 reg = <0x01c06000 0x1000>;
356 interrupts = <11>;
357 clocks = <&ahb_gates 21>, <&spi1_clk>;
358 clock-names = "ahb", "mod";
359 status = "disabled";
360 #address-cells = <1>;
361 #size-cells = <0>;
362 };
363
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364 emac: ethernet@01c0b000 {
365 compatible = "allwinner,sun4i-emac";
366 reg = <0x01c0b000 0x1000>;
367 interrupts = <55>;
368 clocks = <&ahb_gates 17>;
369 status = "disabled";
370 };
371
372 mdio@01c0b080 {
373 compatible = "allwinner,sun4i-mdio";
374 reg = <0x01c0b080 0x14>;
375 status = "disabled";
376 #address-cells = <1>;
377 #size-cells = <0>;
378 };
379
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380 spi2: spi@01c17000 {
381 compatible = "allwinner,sun4i-a10-spi";
382 reg = <0x01c17000 0x1000>;
383 interrupts = <12>;
384 clocks = <&ahb_gates 22>, <&spi2_clk>;
385 clock-names = "ahb", "mod";
386 status = "disabled";
387 #address-cells = <1>;
388 #size-cells = <0>;
389 };
390
391 spi3: spi@01c1f000 {
392 compatible = "allwinner,sun4i-a10-spi";
393 reg = <0x01c1f000 0x1000>;
394 interrupts = <50>;
395 clocks = <&ahb_gates 23>, <&spi3_clk>;
396 clock-names = "ahb", "mod";
397 status = "disabled";
398 #address-cells = <1>;
399 #size-cells = <0>;
400 };
401
69144e3b 402 intc: interrupt-controller@01c20400 {
6def126d 403 compatible = "allwinner,sun4i-ic";
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404 reg = <0x01c20400 0x400>;
405 interrupt-controller;
406 #interrupt-cells = <1>;
407 };
408
e10911e1 409 pio: pinctrl@01c20800 {
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410 compatible = "allwinner,sun4i-a10-pinctrl";
411 reg = <0x01c20800 0x400>;
39138bc6 412 interrupts = <28>;
36386d6e 413 clocks = <&apb0_gates 5>;
e10911e1 414 gpio-controller;
39138bc6 415 interrupt-controller;
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416 #address-cells = <1>;
417 #size-cells = <0>;
e10911e1 418 #gpio-cells = <3>;
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419
420 uart0_pins_a: uart0@0 {
421 allwinner,pins = "PB22", "PB23";
422 allwinner,function = "uart0";
423 allwinner,drive = <0>;
424 allwinner,pull = <0>;
425 };
426
427 uart0_pins_b: uart0@1 {
428 allwinner,pins = "PF2", "PF4";
429 allwinner,function = "uart0";
430 allwinner,drive = <0>;
431 allwinner,pull = <0>;
432 };
433
434 uart1_pins_a: uart1@0 {
435 allwinner,pins = "PA10", "PA11";
436 allwinner,function = "uart1";
437 allwinner,drive = <0>;
438 allwinner,pull = <0>;
439 };
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440
441 i2c0_pins_a: i2c0@0 {
442 allwinner,pins = "PB0", "PB1";
443 allwinner,function = "i2c0";
444 allwinner,drive = <0>;
445 allwinner,pull = <0>;
446 };
447
448 i2c1_pins_a: i2c1@0 {
449 allwinner,pins = "PB18", "PB19";
450 allwinner,function = "i2c1";
451 allwinner,drive = <0>;
452 allwinner,pull = <0>;
453 };
454
455 i2c2_pins_a: i2c2@0 {
456 allwinner,pins = "PB20", "PB21";
457 allwinner,function = "i2c2";
458 allwinner,drive = <0>;
459 allwinner,pull = <0>;
460 };
496322bc 461
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462 emac_pins_a: emac0@0 {
463 allwinner,pins = "PA0", "PA1", "PA2",
464 "PA3", "PA4", "PA5", "PA6",
465 "PA7", "PA8", "PA9", "PA10",
466 "PA11", "PA12", "PA13", "PA14",
467 "PA15", "PA16";
468 allwinner,function = "emac";
469 allwinner,drive = <0>;
470 allwinner,pull = <0>;
471 };
874b4e45 472 };
89b3c99f 473
69144e3b 474 timer@01c20c00 {
b6e1a53b 475 compatible = "allwinner,sun4i-timer";
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476 reg = <0x01c20c00 0x90>;
477 interrupts = <22>;
478 clocks = <&osc24M>;
479 };
480
481 wdt: watchdog@01c20c90 {
0b19b7c2 482 compatible = "allwinner,sun4i-wdt";
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483 reg = <0x01c20c90 0x10>;
484 };
485
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486 rtc: rtc@01c20d00 {
487 compatible = "allwinner,sun4i-rtc";
488 reg = <0x01c20d00 0x20>;
489 interrupts = <24>;
490 };
491
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492 sid: eeprom@01c23800 {
493 compatible = "allwinner,sun4i-sid";
494 reg = <0x01c23800 0x10>;
495 };
496
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497 rtp: rtp@01c25000 {
498 compatible = "allwinner,sun4i-ts";
499 reg = <0x01c25000 0x100>;
500 interrupts = <29>;
501 };
502
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503 uart0: serial@01c28000 {
504 compatible = "snps,dw-apb-uart";
505 reg = <0x01c28000 0x400>;
506 interrupts = <1>;
507 reg-shift = <2>;
508 reg-io-width = <4>;
9ff49ec7 509 clocks = <&apb1_gates 16>;
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510 status = "disabled";
511 };
76f14d0a 512
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513 uart1: serial@01c28400 {
514 compatible = "snps,dw-apb-uart";
515 reg = <0x01c28400 0x400>;
516 interrupts = <2>;
517 reg-shift = <2>;
518 reg-io-width = <4>;
519 clocks = <&apb1_gates 17>;
520 status = "disabled";
521 };
522
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523 uart2: serial@01c28800 {
524 compatible = "snps,dw-apb-uart";
525 reg = <0x01c28800 0x400>;
526 interrupts = <3>;
527 reg-shift = <2>;
528 reg-io-width = <4>;
9ff49ec7 529 clocks = <&apb1_gates 18>;
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530 status = "disabled";
531 };
532
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533 uart3: serial@01c28c00 {
534 compatible = "snps,dw-apb-uart";
535 reg = <0x01c28c00 0x400>;
536 interrupts = <4>;
537 reg-shift = <2>;
538 reg-io-width = <4>;
539 clocks = <&apb1_gates 19>;
540 status = "disabled";
541 };
542
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543 uart4: serial@01c29000 {
544 compatible = "snps,dw-apb-uart";
545 reg = <0x01c29000 0x400>;
546 interrupts = <17>;
547 reg-shift = <2>;
548 reg-io-width = <4>;
9ff49ec7 549 clocks = <&apb1_gates 20>;
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550 status = "disabled";
551 };
552
553 uart5: serial@01c29400 {
554 compatible = "snps,dw-apb-uart";
555 reg = <0x01c29400 0x400>;
556 interrupts = <18>;
557 reg-shift = <2>;
558 reg-io-width = <4>;
9ff49ec7 559 clocks = <&apb1_gates 21>;
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560 status = "disabled";
561 };
562
563 uart6: serial@01c29800 {
564 compatible = "snps,dw-apb-uart";
565 reg = <0x01c29800 0x400>;
566 interrupts = <19>;
567 reg-shift = <2>;
568 reg-io-width = <4>;
9ff49ec7 569 clocks = <&apb1_gates 22>;
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570 status = "disabled";
571 };
572
573 uart7: serial@01c29c00 {
574 compatible = "snps,dw-apb-uart";
575 reg = <0x01c29c00 0x400>;
576 interrupts = <20>;
577 reg-shift = <2>;
578 reg-io-width = <4>;
9ff49ec7 579 clocks = <&apb1_gates 23>;
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580 status = "disabled";
581 };
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582
583 i2c0: i2c@01c2ac00 {
584 compatible = "allwinner,sun4i-i2c";
585 reg = <0x01c2ac00 0x400>;
586 interrupts = <7>;
587 clocks = <&apb1_gates 0>;
588 clock-frequency = <100000>;
589 status = "disabled";
590 };
591
592 i2c1: i2c@01c2b000 {
593 compatible = "allwinner,sun4i-i2c";
594 reg = <0x01c2b000 0x400>;
595 interrupts = <8>;
596 clocks = <&apb1_gates 1>;
597 clock-frequency = <100000>;
598 status = "disabled";
599 };
600
601 i2c2: i2c@01c2b400 {
602 compatible = "allwinner,sun4i-i2c";
603 reg = <0x01c2b400 0x400>;
604 interrupts = <9>;
605 clocks = <&apb1_gates 2>;
606 clock-frequency = <100000>;
607 status = "disabled";
608 };
874b4e45 609 };
7423d2d8 610};
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