projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 7423d2d8 SR |
1 | /* |
| 2 | * Copyright 2012 Stefan Roese | |
| 3 | * Stefan Roese <sr@denx.de> | |
| 4 | * | |
| 5 | * The code contained herein is licensed under the GNU General Public | |
| 6 | * License. You may obtain a copy of the GNU General Public License | |
| 7 | * Version 2 or later at the following locations: | |
| 8 | * | |
| 9 | * http://www.opensource.org/licenses/gpl-license.html | |
| 10 | * http://www.gnu.org/copyleft/gpl.html | |
| 11 | */ | |
| 12 | ||
| 69144e3b | 13 | /include/ "skeleton.dtsi" |
| 7423d2d8 SR |
14 | |
| 15 | / { | |
| 69144e3b MR |
16 | interrupt-parent = <&intc>; |
| 17 | ||
| e751cce9 EL |
18 | aliases { |
| 19 | ethernet0 = &emac; | |
| 10b302a2 MR |
20 | serial0 = &uart0; |
| 21 | serial1 = &uart1; | |
| 143b13d6 MR |
22 | serial2 = &uart2; |
| 23 | serial3 = &uart3; | |
| 24 | serial4 = &uart4; | |
| 25 | serial5 = &uart5; | |
| 26 | serial6 = &uart6; | |
| 27 | serial7 = &uart7; | |
| e751cce9 EL |
28 | }; |
| 29 | ||
| 69144e3b | 30 | cpus { |
| 8b2efa89 AB |
31 | #address-cells = <1>; |
| 32 | #size-cells = <0>; | |
| 69144e3b | 33 | cpu@0 { |
| 14c44aa5 | 34 | device_type = "cpu"; |
| 69144e3b | 35 | compatible = "arm,cortex-a8"; |
| 14c44aa5 | 36 | reg = <0x0>; |
| 69144e3b MR |
37 | }; |
| 38 | }; | |
| 39 | ||
| 7423d2d8 SR |
40 | memory { |
| 41 | reg = <0x40000000 0x80000000>; | |
| 42 | }; | |
| 874b4e45 | 43 | |
| 69144e3b MR |
44 | clocks { |
| 45 | #address-cells = <1>; | |
| 46 | #size-cells = <1>; | |
| 47 | ranges; | |
| 48 | ||
| 49 | /* | |
| 50 | * This is a dummy clock, to be used as placeholder on | |
| 51 | * other mux clocks when a specific parent clock is not | |
| 52 | * yet implemented. It should be dropped when the driver | |
| 53 | * is complete. | |
| 54 | */ | |
| 55 | dummy: dummy { | |
| 56 | #clock-cells = <0>; | |
| 57 | compatible = "fixed-clock"; | |
| 58 | clock-frequency = <0>; | |
| 59 | }; | |
| 60 | ||
| dfb12c0c | 61 | osc24M: clk@01c20050 { |
| 69144e3b | 62 | #clock-cells = <0>; |
| bf6534a1 | 63 | compatible = "allwinner,sun4i-a10-osc-clk"; |
| 69144e3b | 64 | reg = <0x01c20050 0x4>; |
| 92fd6e06 | 65 | clock-frequency = <24000000>; |
| dfb12c0c | 66 | clock-output-names = "osc24M"; |
| 69144e3b MR |
67 | }; |
| 68 | ||
| dfb12c0c | 69 | osc32k: clk@0 { |
| 69144e3b MR |
70 | #clock-cells = <0>; |
| 71 | compatible = "fixed-clock"; | |
| 72 | clock-frequency = <32768>; | |
| dfb12c0c | 73 | clock-output-names = "osc32k"; |
| 69144e3b MR |
74 | }; |
| 75 | ||
| dfb12c0c | 76 | pll1: clk@01c20000 { |
| 69144e3b | 77 | #clock-cells = <0>; |
| bf6534a1 | 78 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
| 69144e3b MR |
79 | reg = <0x01c20000 0x4>; |
| 80 | clocks = <&osc24M>; | |
| dfb12c0c | 81 | clock-output-names = "pll1"; |
| 69144e3b MR |
82 | }; |
| 83 | ||
| dfb12c0c | 84 | pll4: clk@01c20018 { |
| ec5589f7 | 85 | #clock-cells = <0>; |
| bf6534a1 | 86 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
| ec5589f7 EL |
87 | reg = <0x01c20018 0x4>; |
| 88 | clocks = <&osc24M>; | |
| dfb12c0c | 89 | clock-output-names = "pll4"; |
| ec5589f7 EL |
90 | }; |
| 91 | ||
| dfb12c0c | 92 | pll5: clk@01c20020 { |
| c3e5e66b | 93 | #clock-cells = <1>; |
| bf6534a1 | 94 | compatible = "allwinner,sun4i-a10-pll5-clk"; |
| c3e5e66b EL |
95 | reg = <0x01c20020 0x4>; |
| 96 | clocks = <&osc24M>; | |
| 97 | clock-output-names = "pll5_ddr", "pll5_other"; | |
| 98 | }; | |
| 99 | ||
| dfb12c0c | 100 | pll6: clk@01c20028 { |
| c3e5e66b | 101 | #clock-cells = <1>; |
| bf6534a1 | 102 | compatible = "allwinner,sun4i-a10-pll6-clk"; |
| c3e5e66b EL |
103 | reg = <0x01c20028 0x4>; |
| 104 | clocks = <&osc24M>; | |
| 105 | clock-output-names = "pll6_sata", "pll6_other", "pll6"; | |
| 106 | }; | |
| 107 | ||
| 69144e3b MR |
108 | /* dummy is 200M */ |
| 109 | cpu: cpu@01c20054 { | |
| 110 | #clock-cells = <0>; | |
| bf6534a1 | 111 | compatible = "allwinner,sun4i-a10-cpu-clk"; |
| 69144e3b MR |
112 | reg = <0x01c20054 0x4>; |
| 113 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; | |
| dfb12c0c | 114 | clock-output-names = "cpu"; |
| 69144e3b MR |
115 | }; |
| 116 | ||
| 117 | axi: axi@01c20054 { | |
| 118 | #clock-cells = <0>; | |
| bf6534a1 | 119 | compatible = "allwinner,sun4i-a10-axi-clk"; |
| 69144e3b MR |
120 | reg = <0x01c20054 0x4>; |
| 121 | clocks = <&cpu>; | |
| dfb12c0c | 122 | clock-output-names = "axi"; |
| 69144e3b MR |
123 | }; |
| 124 | ||
| dfb12c0c | 125 | axi_gates: clk@01c2005c { |
| 69144e3b | 126 | #clock-cells = <1>; |
| bf6534a1 | 127 | compatible = "allwinner,sun4i-a10-axi-gates-clk"; |
| 69144e3b MR |
128 | reg = <0x01c2005c 0x4>; |
| 129 | clocks = <&axi>; | |
| 130 | clock-output-names = "axi_dram"; | |
| 131 | }; | |
| 132 | ||
| 133 | ahb: ahb@01c20054 { | |
| 134 | #clock-cells = <0>; | |
| bf6534a1 | 135 | compatible = "allwinner,sun4i-a10-ahb-clk"; |
| 69144e3b MR |
136 | reg = <0x01c20054 0x4>; |
| 137 | clocks = <&axi>; | |
| dfb12c0c | 138 | clock-output-names = "ahb"; |
| 69144e3b MR |
139 | }; |
| 140 | ||
| dfb12c0c | 141 | ahb_gates: clk@01c20060 { |
| 69144e3b | 142 | #clock-cells = <1>; |
| bf6534a1 | 143 | compatible = "allwinner,sun4i-a10-ahb-gates-clk"; |
| 69144e3b MR |
144 | reg = <0x01c20060 0x8>; |
| 145 | clocks = <&ahb>; | |
| 146 | clock-output-names = "ahb_usb0", "ahb_ehci0", | |
| 147 | "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss", | |
| 148 | "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1", | |
| 149 | "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand", | |
| 150 | "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts", | |
| 151 | "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3", | |
| 152 | "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve", | |
| 153 | "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0", | |
| 154 | "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi", | |
| 155 | "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0", | |
| 156 | "ahb_de_fe1", "ahb_mp", "ahb_mali400"; | |
| 157 | }; | |
| 158 | ||
| 159 | apb0: apb0@01c20054 { | |
| 160 | #clock-cells = <0>; | |
| bf6534a1 | 161 | compatible = "allwinner,sun4i-a10-apb0-clk"; |
| 69144e3b MR |
162 | reg = <0x01c20054 0x4>; |
| 163 | clocks = <&ahb>; | |
| dfb12c0c | 164 | clock-output-names = "apb0"; |
| 69144e3b MR |
165 | }; |
| 166 | ||
| dfb12c0c | 167 | apb0_gates: clk@01c20068 { |
| 69144e3b | 168 | #clock-cells = <1>; |
| bf6534a1 | 169 | compatible = "allwinner,sun4i-a10-apb0-gates-clk"; |
| 69144e3b MR |
170 | reg = <0x01c20068 0x4>; |
| 171 | clocks = <&apb0>; | |
| 172 | clock-output-names = "apb0_codec", "apb0_spdif", | |
| 173 | "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0", | |
| 174 | "apb0_ir1", "apb0_keypad"; | |
| 175 | }; | |
| 176 | ||
| 69144e3b MR |
177 | apb1_mux: apb1_mux@01c20058 { |
| 178 | #clock-cells = <0>; | |
| bf6534a1 | 179 | compatible = "allwinner,sun4i-a10-apb1-mux-clk"; |
| 69144e3b | 180 | reg = <0x01c20058 0x4>; |
| c3e5e66b | 181 | clocks = <&osc24M>, <&pll6 1>, <&osc32k>; |
| dfb12c0c | 182 | clock-output-names = "apb1_mux"; |
| 69144e3b MR |
183 | }; |
| 184 | ||
| 185 | apb1: apb1@01c20058 { | |
| 186 | #clock-cells = <0>; | |
| bf6534a1 | 187 | compatible = "allwinner,sun4i-a10-apb1-clk"; |
| 69144e3b MR |
188 | reg = <0x01c20058 0x4>; |
| 189 | clocks = <&apb1_mux>; | |
| dfb12c0c | 190 | clock-output-names = "apb1"; |
| 69144e3b MR |
191 | }; |
| 192 | ||
| dfb12c0c | 193 | apb1_gates: clk@01c2006c { |
| 69144e3b | 194 | #clock-cells = <1>; |
| bf6534a1 | 195 | compatible = "allwinner,sun4i-a10-apb1-gates-clk"; |
| 69144e3b MR |
196 | reg = <0x01c2006c 0x4>; |
| 197 | clocks = <&apb1>; | |
| 198 | clock-output-names = "apb1_i2c0", "apb1_i2c1", | |
| 199 | "apb1_i2c2", "apb1_can", "apb1_scr", | |
| 200 | "apb1_ps20", "apb1_ps21", "apb1_uart0", | |
| 201 | "apb1_uart1", "apb1_uart2", "apb1_uart3", | |
| 202 | "apb1_uart4", "apb1_uart5", "apb1_uart6", | |
| 203 | "apb1_uart7"; | |
| 204 | }; | |
| 4b756ffb EL |
205 | |
| 206 | nand_clk: clk@01c20080 { | |
| 207 | #clock-cells = <0>; | |
| bf6534a1 | 208 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 4b756ffb EL |
209 | reg = <0x01c20080 0x4>; |
| 210 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 211 | clock-output-names = "nand"; | |
| 212 | }; | |
| 213 | ||
| 214 | ms_clk: clk@01c20084 { | |
| 215 | #clock-cells = <0>; | |
| bf6534a1 | 216 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 4b756ffb EL |
217 | reg = <0x01c20084 0x4>; |
| 218 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 219 | clock-output-names = "ms"; | |
| 220 | }; | |
| 221 | ||
| 222 | mmc0_clk: clk@01c20088 { | |
| 223 | #clock-cells = <0>; | |
| bf6534a1 | 224 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 4b756ffb EL |
225 | reg = <0x01c20088 0x4>; |
| 226 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 227 | clock-output-names = "mmc0"; | |
| 228 | }; | |
| 229 | ||
| 230 | mmc1_clk: clk@01c2008c { | |
| 231 | #clock-cells = <0>; | |
| bf6534a1 | 232 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 4b756ffb EL |
233 | reg = <0x01c2008c 0x4>; |
| 234 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 235 | clock-output-names = "mmc1"; | |
| 236 | }; | |
| 237 | ||
| 238 | mmc2_clk: clk@01c20090 { | |
| 239 | #clock-cells = <0>; | |
| bf6534a1 | 240 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 4b756ffb EL |
241 | reg = <0x01c20090 0x4>; |
| 242 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 243 | clock-output-names = "mmc2"; | |
| 244 | }; | |
| 245 | ||
| 246 | mmc3_clk: clk@01c20094 { | |
| 247 | #clock-cells = <0>; | |
| bf6534a1 | 248 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 4b756ffb EL |
249 | reg = <0x01c20094 0x4>; |
| 250 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 251 | clock-output-names = "mmc3"; | |
| 252 | }; | |
| 253 | ||
| 254 | ts_clk: clk@01c20098 { | |
| 255 | #clock-cells = <0>; | |
| bf6534a1 | 256 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 4b756ffb EL |
257 | reg = <0x01c20098 0x4>; |
| 258 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 259 | clock-output-names = "ts"; | |
| 260 | }; | |
| 261 | ||
| 262 | ss_clk: clk@01c2009c { | |
| 263 | #clock-cells = <0>; | |
| bf6534a1 | 264 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 4b756ffb EL |
265 | reg = <0x01c2009c 0x4>; |
| 266 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 267 | clock-output-names = "ss"; | |
| 268 | }; | |
| 269 | ||
| 270 | spi0_clk: clk@01c200a0 { | |
| 271 | #clock-cells = <0>; | |
| bf6534a1 | 272 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 4b756ffb EL |
273 | reg = <0x01c200a0 0x4>; |
| 274 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 275 | clock-output-names = "spi0"; | |
| 276 | }; | |
| 277 | ||
| 278 | spi1_clk: clk@01c200a4 { | |
| 279 | #clock-cells = <0>; | |
| bf6534a1 | 280 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 4b756ffb EL |
281 | reg = <0x01c200a4 0x4>; |
| 282 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 283 | clock-output-names = "spi1"; | |
| 284 | }; | |
| 285 | ||
| 286 | spi2_clk: clk@01c200a8 { | |
| 287 | #clock-cells = <0>; | |
| bf6534a1 | 288 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 4b756ffb EL |
289 | reg = <0x01c200a8 0x4>; |
| 290 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 291 | clock-output-names = "spi2"; | |
| 292 | }; | |
| 293 | ||
| 294 | pata_clk: clk@01c200ac { | |
| 295 | #clock-cells = <0>; | |
| bf6534a1 | 296 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 4b756ffb EL |
297 | reg = <0x01c200ac 0x4>; |
| 298 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 299 | clock-output-names = "pata"; | |
| 300 | }; | |
| 301 | ||
| 302 | ir0_clk: clk@01c200b0 { | |
| 303 | #clock-cells = <0>; | |
| bf6534a1 | 304 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 4b756ffb EL |
305 | reg = <0x01c200b0 0x4>; |
| 306 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 307 | clock-output-names = "ir0"; | |
| 308 | }; | |
| 309 | ||
| 310 | ir1_clk: clk@01c200b4 { | |
| 311 | #clock-cells = <0>; | |
| bf6534a1 | 312 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 4b756ffb EL |
313 | reg = <0x01c200b4 0x4>; |
| 314 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 315 | clock-output-names = "ir1"; | |
| 316 | }; | |
| 317 | ||
| 0076c8bd RB |
318 | usb_clk: clk@01c200cc { |
| 319 | #clock-cells = <1>; | |
| 320 | #reset-cells = <1>; | |
| 321 | compatible = "allwinner,sun4i-a10-usb-clk"; | |
| 322 | reg = <0x01c200cc 0x4>; | |
| 323 | clocks = <&pll6 1>; | |
| 324 | clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy"; | |
| 325 | }; | |
| 326 | ||
| 4b756ffb EL |
327 | spi3_clk: clk@01c200d4 { |
| 328 | #clock-cells = <0>; | |
| bf6534a1 | 329 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 4b756ffb EL |
330 | reg = <0x01c200d4 0x4>; |
| 331 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 332 | clock-output-names = "spi3"; | |
| 333 | }; | |
| 69144e3b MR |
334 | }; |
| 335 | ||
| b74aec1a | 336 | soc@01c00000 { |
| 69144e3b MR |
337 | compatible = "simple-bus"; |
| 338 | #address-cells = <1>; | |
| 339 | #size-cells = <1>; | |
| 69144e3b MR |
340 | ranges; |
| 341 | ||
| 65918e26 MR |
342 | spi0: spi@01c05000 { |
| 343 | compatible = "allwinner,sun4i-a10-spi"; | |
| 344 | reg = <0x01c05000 0x1000>; | |
| 345 | interrupts = <10>; | |
| 346 | clocks = <&ahb_gates 20>, <&spi0_clk>; | |
| 347 | clock-names = "ahb", "mod"; | |
| 348 | status = "disabled"; | |
| 349 | #address-cells = <1>; | |
| 350 | #size-cells = <0>; | |
| 351 | }; | |
| 352 | ||
| 353 | spi1: spi@01c06000 { | |
| 354 | compatible = "allwinner,sun4i-a10-spi"; | |
| 355 | reg = <0x01c06000 0x1000>; | |
| 356 | interrupts = <11>; | |
| 357 | clocks = <&ahb_gates 21>, <&spi1_clk>; | |
| 358 | clock-names = "ahb", "mod"; | |
| 359 | status = "disabled"; | |
| 360 | #address-cells = <1>; | |
| 361 | #size-cells = <0>; | |
| 362 | }; | |
| 363 | ||
| e38afcb3 | 364 | emac: ethernet@01c0b000 { |
| 1c70e099 | 365 | compatible = "allwinner,sun4i-a10-emac"; |
| e38afcb3 MR |
366 | reg = <0x01c0b000 0x1000>; |
| 367 | interrupts = <55>; | |
| 368 | clocks = <&ahb_gates 17>; | |
| 369 | status = "disabled"; | |
| 370 | }; | |
| 371 | ||
| 372 | mdio@01c0b080 { | |
| 1c70e099 | 373 | compatible = "allwinner,sun4i-a10-mdio"; |
| e38afcb3 MR |
374 | reg = <0x01c0b080 0x14>; |
| 375 | status = "disabled"; | |
| 376 | #address-cells = <1>; | |
| 377 | #size-cells = <0>; | |
| 378 | }; | |
| 379 | ||
| b258b369 DL |
380 | mmc0: mmc@01c0f000 { |
| 381 | compatible = "allwinner,sun4i-a10-mmc"; | |
| 382 | reg = <0x01c0f000 0x1000>; | |
| 383 | clocks = <&ahb_gates 8>, <&mmc0_clk>; | |
| 384 | clock-names = "ahb", "mmc"; | |
| 385 | interrupts = <32>; | |
| 386 | status = "disabled"; | |
| 387 | }; | |
| 388 | ||
| 389 | mmc1: mmc@01c10000 { | |
| 390 | compatible = "allwinner,sun4i-a10-mmc"; | |
| 391 | reg = <0x01c10000 0x1000>; | |
| 392 | clocks = <&ahb_gates 9>, <&mmc1_clk>; | |
| 393 | clock-names = "ahb", "mmc"; | |
| 394 | interrupts = <33>; | |
| 395 | status = "disabled"; | |
| 396 | }; | |
| 397 | ||
| 398 | mmc2: mmc@01c11000 { | |
| 399 | compatible = "allwinner,sun4i-a10-mmc"; | |
| 400 | reg = <0x01c11000 0x1000>; | |
| 401 | clocks = <&ahb_gates 10>, <&mmc2_clk>; | |
| 402 | clock-names = "ahb", "mmc"; | |
| 403 | interrupts = <34>; | |
| 404 | status = "disabled"; | |
| 405 | }; | |
| 406 | ||
| 407 | mmc3: mmc@01c12000 { | |
| 408 | compatible = "allwinner,sun4i-a10-mmc"; | |
| 409 | reg = <0x01c12000 0x1000>; | |
| 410 | clocks = <&ahb_gates 11>, <&mmc3_clk>; | |
| 411 | clock-names = "ahb", "mmc"; | |
| 412 | interrupts = <35>; | |
| 413 | status = "disabled"; | |
| 414 | }; | |
| 415 | ||
| 6ab1ce24 RB |
416 | usbphy: phy@01c13400 { |
| 417 | #phy-cells = <1>; | |
| 418 | compatible = "allwinner,sun4i-a10-usb-phy"; | |
| 419 | reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; | |
| 420 | reg-names = "phy_ctrl", "pmu1", "pmu2"; | |
| 421 | clocks = <&usb_clk 8>; | |
| 422 | clock-names = "usb_phy"; | |
| 423 | resets = <&usb_clk 1>, <&usb_clk 2>; | |
| 424 | reset-names = "usb1_reset", "usb2_reset"; | |
| 425 | status = "disabled"; | |
| 426 | }; | |
| 427 | ||
| 428 | ehci0: usb@01c14000 { | |
| 429 | compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; | |
| 430 | reg = <0x01c14000 0x100>; | |
| 431 | interrupts = <39>; | |
| 432 | clocks = <&ahb_gates 1>; | |
| 433 | phys = <&usbphy 1>; | |
| 434 | phy-names = "usb"; | |
| 435 | status = "disabled"; | |
| 436 | }; | |
| 437 | ||
| 438 | ohci0: usb@01c14400 { | |
| 439 | compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; | |
| 440 | reg = <0x01c14400 0x100>; | |
| 441 | interrupts = <64>; | |
| 442 | clocks = <&usb_clk 6>, <&ahb_gates 2>; | |
| 443 | phys = <&usbphy 1>; | |
| 444 | phy-names = "usb"; | |
| 445 | status = "disabled"; | |
| 446 | }; | |
| 447 | ||
| 65918e26 MR |
448 | spi2: spi@01c17000 { |
| 449 | compatible = "allwinner,sun4i-a10-spi"; | |
| 450 | reg = <0x01c17000 0x1000>; | |
| 451 | interrupts = <12>; | |
| 452 | clocks = <&ahb_gates 22>, <&spi2_clk>; | |
| 453 | clock-names = "ahb", "mod"; | |
| 454 | status = "disabled"; | |
| 455 | #address-cells = <1>; | |
| 456 | #size-cells = <0>; | |
| 457 | }; | |
| 458 | ||
| 248bd1e2 OS |
459 | ahci: sata@01c18000 { |
| 460 | compatible = "allwinner,sun4i-a10-ahci"; | |
| 461 | reg = <0x01c18000 0x1000>; | |
| 462 | interrupts = <56>; | |
| 463 | clocks = <&pll6 0>, <&ahb_gates 25>; | |
| 464 | status = "disabled"; | |
| 465 | }; | |
| 466 | ||
| 6ab1ce24 RB |
467 | ehci1: usb@01c1c000 { |
| 468 | compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; | |
| 469 | reg = <0x01c1c000 0x100>; | |
| 470 | interrupts = <40>; | |
| 471 | clocks = <&ahb_gates 3>; | |
| 472 | phys = <&usbphy 2>; | |
| 473 | phy-names = "usb"; | |
| 474 | status = "disabled"; | |
| 475 | }; | |
| 476 | ||
| 477 | ohci1: usb@01c1c400 { | |
| 478 | compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; | |
| 479 | reg = <0x01c1c400 0x100>; | |
| 480 | interrupts = <65>; | |
| 481 | clocks = <&usb_clk 7>, <&ahb_gates 4>; | |
| 482 | phys = <&usbphy 2>; | |
| 483 | phy-names = "usb"; | |
| 484 | status = "disabled"; | |
| 485 | }; | |
| 486 | ||
| 65918e26 MR |
487 | spi3: spi@01c1f000 { |
| 488 | compatible = "allwinner,sun4i-a10-spi"; | |
| 489 | reg = <0x01c1f000 0x1000>; | |
| 490 | interrupts = <50>; | |
| 491 | clocks = <&ahb_gates 23>, <&spi3_clk>; | |
| 492 | clock-names = "ahb", "mod"; | |
| 493 | status = "disabled"; | |
| 494 | #address-cells = <1>; | |
| 495 | #size-cells = <0>; | |
| 496 | }; | |
| 497 | ||
| 69144e3b | 498 | intc: interrupt-controller@01c20400 { |
| 09504a7d | 499 | compatible = "allwinner,sun4i-a10-ic"; |
| 69144e3b MR |
500 | reg = <0x01c20400 0x400>; |
| 501 | interrupt-controller; | |
| 502 | #interrupt-cells = <1>; | |
| 503 | }; | |
| 504 | ||
| e10911e1 | 505 | pio: pinctrl@01c20800 { |
| 874b4e45 MR |
506 | compatible = "allwinner,sun4i-a10-pinctrl"; |
| 507 | reg = <0x01c20800 0x400>; | |
| 39138bc6 | 508 | interrupts = <28>; |
| 36386d6e | 509 | clocks = <&apb0_gates 5>; |
| e10911e1 | 510 | gpio-controller; |
| 39138bc6 | 511 | interrupt-controller; |
| 874b4e45 MR |
512 | #address-cells = <1>; |
| 513 | #size-cells = <0>; | |
| e10911e1 | 514 | #gpio-cells = <3>; |
| 581981be | 515 | |
| 1d5726e9 AB |
516 | pwm0_pins_a: pwm0@0 { |
| 517 | allwinner,pins = "PB2"; | |
| 518 | allwinner,function = "pwm"; | |
| 519 | allwinner,drive = <0>; | |
| 520 | allwinner,pull = <0>; | |
| 521 | }; | |
| 522 | ||
| 523 | pwm1_pins_a: pwm1@0 { | |
| 524 | allwinner,pins = "PI3"; | |
| 525 | allwinner,function = "pwm"; | |
| 526 | allwinner,drive = <0>; | |
| 527 | allwinner,pull = <0>; | |
| 528 | }; | |
| 529 | ||
| 581981be MR |
530 | uart0_pins_a: uart0@0 { |
| 531 | allwinner,pins = "PB22", "PB23"; | |
| 532 | allwinner,function = "uart0"; | |
| 533 | allwinner,drive = <0>; | |
| 534 | allwinner,pull = <0>; | |
| 535 | }; | |
| 536 | ||
| 537 | uart0_pins_b: uart0@1 { | |
| 538 | allwinner,pins = "PF2", "PF4"; | |
| 539 | allwinner,function = "uart0"; | |
| 540 | allwinner,drive = <0>; | |
| 541 | allwinner,pull = <0>; | |
| 542 | }; | |
| 543 | ||
| 544 | uart1_pins_a: uart1@0 { | |
| 545 | allwinner,pins = "PA10", "PA11"; | |
| 546 | allwinner,function = "uart1"; | |
| 547 | allwinner,drive = <0>; | |
| 548 | allwinner,pull = <0>; | |
| 549 | }; | |
| 27cce4ff MR |
550 | |
| 551 | i2c0_pins_a: i2c0@0 { | |
| 552 | allwinner,pins = "PB0", "PB1"; | |
| 553 | allwinner,function = "i2c0"; | |
| 554 | allwinner,drive = <0>; | |
| 555 | allwinner,pull = <0>; | |
| 556 | }; | |
| 557 | ||
| 558 | i2c1_pins_a: i2c1@0 { | |
| 559 | allwinner,pins = "PB18", "PB19"; | |
| 560 | allwinner,function = "i2c1"; | |
| 561 | allwinner,drive = <0>; | |
| 562 | allwinner,pull = <0>; | |
| 563 | }; | |
| 564 | ||
| 565 | i2c2_pins_a: i2c2@0 { | |
| 566 | allwinner,pins = "PB20", "PB21"; | |
| 567 | allwinner,function = "i2c2"; | |
| 568 | allwinner,drive = <0>; | |
| 569 | allwinner,pull = <0>; | |
| 570 | }; | |
| 496322bc | 571 | |
| b21da664 MR |
572 | emac_pins_a: emac0@0 { |
| 573 | allwinner,pins = "PA0", "PA1", "PA2", | |
| 574 | "PA3", "PA4", "PA5", "PA6", | |
| 575 | "PA7", "PA8", "PA9", "PA10", | |
| 576 | "PA11", "PA12", "PA13", "PA14", | |
| 577 | "PA15", "PA16"; | |
| 578 | allwinner,function = "emac"; | |
| 579 | allwinner,drive = <0>; | |
| 580 | allwinner,pull = <0>; | |
| 581 | }; | |
| 874b4e45 | 582 | }; |
| 89b3c99f | 583 | |
| 69144e3b | 584 | timer@01c20c00 { |
| b4f26440 | 585 | compatible = "allwinner,sun4i-a10-timer"; |
| 69144e3b MR |
586 | reg = <0x01c20c00 0x90>; |
| 587 | interrupts = <22>; | |
| 588 | clocks = <&osc24M>; | |
| 589 | }; | |
| 590 | ||
| 591 | wdt: watchdog@01c20c90 { | |
| ca5d04d9 | 592 | compatible = "allwinner,sun4i-a10-wdt"; |
| 69144e3b MR |
593 | reg = <0x01c20c90 0x10>; |
| 594 | }; | |
| 595 | ||
| b5d905c7 | 596 | rtc: rtc@01c20d00 { |
| 5fc4bc89 | 597 | compatible = "allwinner,sun4i-a10-rtc"; |
| b5d905c7 CC |
598 | reg = <0x01c20d00 0x20>; |
| 599 | interrupts = <24>; | |
| 600 | }; | |
| 601 | ||
| 4b57a395 AB |
602 | pwm: pwm@01c20e00 { |
| 603 | compatible = "allwinner,sun4i-a10-pwm"; | |
| 604 | reg = <0x01c20e00 0xc>; | |
| 605 | clocks = <&osc24M>; | |
| 606 | #pwm-cells = <3>; | |
| 607 | status = "disabled"; | |
| 608 | }; | |
| 609 | ||
| 2bad969f | 610 | sid: eeprom@01c23800 { |
| 043d56ee | 611 | compatible = "allwinner,sun4i-a10-sid"; |
| 2bad969f OS |
612 | reg = <0x01c23800 0x10>; |
| 613 | }; | |
| 614 | ||
| 57c8839c | 615 | rtp: rtp@01c25000 { |
| 40dd8f3b | 616 | compatible = "allwinner,sun4i-a10-ts"; |
| 57c8839c HG |
617 | reg = <0x01c25000 0x100>; |
| 618 | interrupts = <29>; | |
| 619 | }; | |
| 620 | ||
| 89b3c99f MR |
621 | uart0: serial@01c28000 { |
| 622 | compatible = "snps,dw-apb-uart"; | |
| 623 | reg = <0x01c28000 0x400>; | |
| 624 | interrupts = <1>; | |
| 625 | reg-shift = <2>; | |
| 626 | reg-io-width = <4>; | |
| 9ff49ec7 | 627 | clocks = <&apb1_gates 16>; |
| 89b3c99f MR |
628 | status = "disabled"; |
| 629 | }; | |
| 76f14d0a | 630 | |
| 69144e3b MR |
631 | uart1: serial@01c28400 { |
| 632 | compatible = "snps,dw-apb-uart"; | |
| 633 | reg = <0x01c28400 0x400>; | |
| 634 | interrupts = <2>; | |
| 635 | reg-shift = <2>; | |
| 636 | reg-io-width = <4>; | |
| 637 | clocks = <&apb1_gates 17>; | |
| 638 | status = "disabled"; | |
| 639 | }; | |
| 640 | ||
| 76f14d0a MR |
641 | uart2: serial@01c28800 { |
| 642 | compatible = "snps,dw-apb-uart"; | |
| 643 | reg = <0x01c28800 0x400>; | |
| 644 | interrupts = <3>; | |
| 645 | reg-shift = <2>; | |
| 646 | reg-io-width = <4>; | |
| 9ff49ec7 | 647 | clocks = <&apb1_gates 18>; |
| 76f14d0a MR |
648 | status = "disabled"; |
| 649 | }; | |
| 650 | ||
| 69144e3b MR |
651 | uart3: serial@01c28c00 { |
| 652 | compatible = "snps,dw-apb-uart"; | |
| 653 | reg = <0x01c28c00 0x400>; | |
| 654 | interrupts = <4>; | |
| 655 | reg-shift = <2>; | |
| 656 | reg-io-width = <4>; | |
| 657 | clocks = <&apb1_gates 19>; | |
| 658 | status = "disabled"; | |
| 659 | }; | |
| 660 | ||
| 76f14d0a MR |
661 | uart4: serial@01c29000 { |
| 662 | compatible = "snps,dw-apb-uart"; | |
| 663 | reg = <0x01c29000 0x400>; | |
| 664 | interrupts = <17>; | |
| 665 | reg-shift = <2>; | |
| 666 | reg-io-width = <4>; | |
| 9ff49ec7 | 667 | clocks = <&apb1_gates 20>; |
| 76f14d0a MR |
668 | status = "disabled"; |
| 669 | }; | |
| 670 | ||
| 671 | uart5: serial@01c29400 { | |
| 672 | compatible = "snps,dw-apb-uart"; | |
| 673 | reg = <0x01c29400 0x400>; | |
| 674 | interrupts = <18>; | |
| 675 | reg-shift = <2>; | |
| 676 | reg-io-width = <4>; | |
| 9ff49ec7 | 677 | clocks = <&apb1_gates 21>; |
| 76f14d0a MR |
678 | status = "disabled"; |
| 679 | }; | |
| 680 | ||
| 681 | uart6: serial@01c29800 { | |
| 682 | compatible = "snps,dw-apb-uart"; | |
| 683 | reg = <0x01c29800 0x400>; | |
| 684 | interrupts = <19>; | |
| 685 | reg-shift = <2>; | |
| 686 | reg-io-width = <4>; | |
| 9ff49ec7 | 687 | clocks = <&apb1_gates 22>; |
| 76f14d0a MR |
688 | status = "disabled"; |
| 689 | }; | |
| 690 | ||
| 691 | uart7: serial@01c29c00 { | |
| 692 | compatible = "snps,dw-apb-uart"; | |
| 693 | reg = <0x01c29c00 0x400>; | |
| 694 | interrupts = <20>; | |
| 695 | reg-shift = <2>; | |
| 696 | reg-io-width = <4>; | |
| 9ff49ec7 | 697 | clocks = <&apb1_gates 23>; |
| 76f14d0a MR |
698 | status = "disabled"; |
| 699 | }; | |
| f1741fda MR |
700 | |
| 701 | i2c0: i2c@01c2ac00 { | |
| 702 | compatible = "allwinner,sun4i-i2c"; | |
| 703 | reg = <0x01c2ac00 0x400>; | |
| 704 | interrupts = <7>; | |
| 705 | clocks = <&apb1_gates 0>; | |
| 706 | clock-frequency = <100000>; | |
| 707 | status = "disabled"; | |
| 60bbe316 HG |
708 | #address-cells = <1>; |
| 709 | #size-cells = <0>; | |
| f1741fda MR |
710 | }; |
| 711 | ||
| 712 | i2c1: i2c@01c2b000 { | |
| 713 | compatible = "allwinner,sun4i-i2c"; | |
| 714 | reg = <0x01c2b000 0x400>; | |
| 715 | interrupts = <8>; | |
| 716 | clocks = <&apb1_gates 1>; | |
| 717 | clock-frequency = <100000>; | |
| 718 | status = "disabled"; | |
| 60bbe316 HG |
719 | #address-cells = <1>; |
| 720 | #size-cells = <0>; | |
| f1741fda MR |
721 | }; |
| 722 | ||
| 723 | i2c2: i2c@01c2b400 { | |
| 724 | compatible = "allwinner,sun4i-i2c"; | |
| 725 | reg = <0x01c2b400 0x400>; | |
| 726 | interrupts = <9>; | |
| 727 | clocks = <&apb1_gates 2>; | |
| 728 | clock-frequency = <100000>; | |
| 729 | status = "disabled"; | |
| 60bbe316 HG |
730 | #address-cells = <1>; |
| 731 | #size-cells = <0>; | |
| f1741fda | 732 | }; |
| 874b4e45 | 733 | }; |
| 7423d2d8 | 734 | }; |