Commit | Line | Data |
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d3ae078e MR |
1 | /* |
2 | * Copyright 2013 Maxime Ripard | |
3 | * | |
4 | * Maxime Ripard <maxime.ripard@free-electrons.com> | |
5 | * | |
6 | * The code contained herein is licensed under the GNU General Public | |
7 | * License. You may obtain a copy of the GNU General Public License | |
8 | * Version 2 or later at the following locations: | |
9 | * | |
10 | * http://www.opensource.org/licenses/gpl-license.html | |
11 | * http://www.gnu.org/copyleft/gpl.html | |
12 | */ | |
13 | ||
14 | /include/ "skeleton.dtsi" | |
15 | ||
16 | / { | |
17 | interrupt-parent = <&intc>; | |
18 | ||
e751cce9 EL |
19 | aliases { |
20 | ethernet0 = &emac; | |
4dd4065f MR |
21 | serial0 = &uart0; |
22 | serial1 = &uart1; | |
23 | serial2 = &uart2; | |
24 | serial3 = &uart3; | |
e751cce9 EL |
25 | }; |
26 | ||
d3ae078e MR |
27 | cpus { |
28 | cpu@0 { | |
29 | compatible = "arm,cortex-a8"; | |
30 | }; | |
31 | }; | |
32 | ||
33 | memory { | |
34 | reg = <0x40000000 0x20000000>; | |
35 | }; | |
36 | ||
37 | clocks { | |
38 | #address-cells = <1>; | |
39 | #size-cells = <1>; | |
40 | ranges; | |
41 | ||
42 | /* | |
43 | * This is a dummy clock, to be used as placeholder on | |
44 | * other mux clocks when a specific parent clock is not | |
45 | * yet implemented. It should be dropped when the driver | |
46 | * is complete. | |
47 | */ | |
48 | dummy: dummy { | |
49 | #clock-cells = <0>; | |
50 | compatible = "fixed-clock"; | |
51 | clock-frequency = <0>; | |
52 | }; | |
53 | ||
3dce8324 | 54 | osc24M: clk@01c20050 { |
d3ae078e | 55 | #clock-cells = <0>; |
bf6534a1 | 56 | compatible = "allwinner,sun4i-a10-osc-clk"; |
d3ae078e MR |
57 | reg = <0x01c20050 0x4>; |
58 | clock-frequency = <24000000>; | |
3dce8324 | 59 | clock-output-names = "osc24M"; |
d3ae078e MR |
60 | }; |
61 | ||
3dce8324 | 62 | osc32k: clk@0 { |
d3ae078e MR |
63 | #clock-cells = <0>; |
64 | compatible = "fixed-clock"; | |
65 | clock-frequency = <32768>; | |
3dce8324 | 66 | clock-output-names = "osc32k"; |
d3ae078e MR |
67 | }; |
68 | ||
3dce8324 | 69 | pll1: clk@01c20000 { |
d3ae078e | 70 | #clock-cells = <0>; |
bf6534a1 | 71 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
d3ae078e MR |
72 | reg = <0x01c20000 0x4>; |
73 | clocks = <&osc24M>; | |
3dce8324 | 74 | clock-output-names = "pll1"; |
d3ae078e MR |
75 | }; |
76 | ||
3dce8324 | 77 | pll4: clk@01c20018 { |
ec5589f7 | 78 | #clock-cells = <0>; |
bf6534a1 | 79 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
ec5589f7 EL |
80 | reg = <0x01c20018 0x4>; |
81 | clocks = <&osc24M>; | |
3dce8324 | 82 | clock-output-names = "pll4"; |
ec5589f7 EL |
83 | }; |
84 | ||
3dce8324 | 85 | pll5: clk@01c20020 { |
c3e5e66b | 86 | #clock-cells = <1>; |
bf6534a1 | 87 | compatible = "allwinner,sun4i-a10-pll5-clk"; |
c3e5e66b EL |
88 | reg = <0x01c20020 0x4>; |
89 | clocks = <&osc24M>; | |
90 | clock-output-names = "pll5_ddr", "pll5_other"; | |
91 | }; | |
92 | ||
3dce8324 | 93 | pll6: clk@01c20028 { |
c3e5e66b | 94 | #clock-cells = <1>; |
bf6534a1 | 95 | compatible = "allwinner,sun4i-a10-pll6-clk"; |
c3e5e66b EL |
96 | reg = <0x01c20028 0x4>; |
97 | clocks = <&osc24M>; | |
98 | clock-output-names = "pll6_sata", "pll6_other", "pll6"; | |
99 | }; | |
100 | ||
d3ae078e MR |
101 | /* dummy is 200M */ |
102 | cpu: cpu@01c20054 { | |
103 | #clock-cells = <0>; | |
bf6534a1 | 104 | compatible = "allwinner,sun4i-a10-cpu-clk"; |
d3ae078e MR |
105 | reg = <0x01c20054 0x4>; |
106 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; | |
3dce8324 | 107 | clock-output-names = "cpu"; |
d3ae078e MR |
108 | }; |
109 | ||
110 | axi: axi@01c20054 { | |
111 | #clock-cells = <0>; | |
bf6534a1 | 112 | compatible = "allwinner,sun4i-a10-axi-clk"; |
d3ae078e MR |
113 | reg = <0x01c20054 0x4>; |
114 | clocks = <&cpu>; | |
3dce8324 | 115 | clock-output-names = "axi"; |
d3ae078e MR |
116 | }; |
117 | ||
3dce8324 | 118 | axi_gates: clk@01c2005c { |
d3ae078e | 119 | #clock-cells = <1>; |
bf6534a1 | 120 | compatible = "allwinner,sun4i-a10-axi-gates-clk"; |
d3ae078e MR |
121 | reg = <0x01c2005c 0x4>; |
122 | clocks = <&axi>; | |
123 | clock-output-names = "axi_dram"; | |
124 | }; | |
125 | ||
126 | ahb: ahb@01c20054 { | |
127 | #clock-cells = <0>; | |
bf6534a1 | 128 | compatible = "allwinner,sun4i-a10-ahb-clk"; |
d3ae078e MR |
129 | reg = <0x01c20054 0x4>; |
130 | clocks = <&axi>; | |
3dce8324 | 131 | clock-output-names = "ahb"; |
d3ae078e MR |
132 | }; |
133 | ||
3dce8324 | 134 | ahb_gates: clk@01c20060 { |
d3ae078e | 135 | #clock-cells = <1>; |
29bb8054 | 136 | compatible = "allwinner,sun5i-a10s-ahb-gates-clk"; |
d3ae078e MR |
137 | reg = <0x01c20060 0x8>; |
138 | clocks = <&ahb>; | |
29bb8054 MR |
139 | clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci", |
140 | "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0", | |
141 | "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram", | |
142 | "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1", | |
143 | "ahb_spi2", "ahb_gps", "ahb_stimer", "ahb_ve", | |
144 | "ahb_tve", "ahb_lcd", "ahb_csi", "ahb_hdmi", | |
145 | "ahb_de_be", "ahb_de_fe", "ahb_iep", "ahb_mali400"; | |
d3ae078e MR |
146 | }; |
147 | ||
148 | apb0: apb0@01c20054 { | |
149 | #clock-cells = <0>; | |
bf6534a1 | 150 | compatible = "allwinner,sun4i-a10-apb0-clk"; |
d3ae078e MR |
151 | reg = <0x01c20054 0x4>; |
152 | clocks = <&ahb>; | |
3dce8324 | 153 | clock-output-names = "apb0"; |
d3ae078e MR |
154 | }; |
155 | ||
3dce8324 | 156 | apb0_gates: clk@01c20068 { |
d3ae078e | 157 | #clock-cells = <1>; |
29bb8054 | 158 | compatible = "allwinner,sun5i-a10s-apb0-gates-clk"; |
d3ae078e MR |
159 | reg = <0x01c20068 0x4>; |
160 | clocks = <&apb0>; | |
29bb8054 MR |
161 | clock-output-names = "apb0_codec", "apb0_iis", "apb0_pio", |
162 | "apb0_ir", "apb0_keypad"; | |
d3ae078e MR |
163 | }; |
164 | ||
d3ae078e MR |
165 | apb1_mux: apb1_mux@01c20058 { |
166 | #clock-cells = <0>; | |
bf6534a1 | 167 | compatible = "allwinner,sun4i-a10-apb1-mux-clk"; |
d3ae078e | 168 | reg = <0x01c20058 0x4>; |
c3e5e66b | 169 | clocks = <&osc24M>, <&pll6 1>, <&osc32k>; |
3dce8324 | 170 | clock-output-names = "apb1_mux"; |
d3ae078e MR |
171 | }; |
172 | ||
173 | apb1: apb1@01c20058 { | |
174 | #clock-cells = <0>; | |
bf6534a1 | 175 | compatible = "allwinner,sun4i-a10-apb1-clk"; |
d3ae078e MR |
176 | reg = <0x01c20058 0x4>; |
177 | clocks = <&apb1_mux>; | |
3dce8324 | 178 | clock-output-names = "apb1"; |
d3ae078e MR |
179 | }; |
180 | ||
3dce8324 | 181 | apb1_gates: clk@01c2006c { |
d3ae078e | 182 | #clock-cells = <1>; |
29bb8054 | 183 | compatible = "allwinner,sun5i-a10s-apb1-gates-clk"; |
d3ae078e MR |
184 | reg = <0x01c2006c 0x4>; |
185 | clocks = <&apb1>; | |
186 | clock-output-names = "apb1_i2c0", "apb1_i2c1", | |
29bb8054 MR |
187 | "apb1_i2c2", "apb1_uart0", "apb1_uart1", |
188 | "apb1_uart2", "apb1_uart3"; | |
d3ae078e | 189 | }; |
8dc36bff EL |
190 | |
191 | nand_clk: clk@01c20080 { | |
192 | #clock-cells = <0>; | |
bf6534a1 | 193 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
8dc36bff EL |
194 | reg = <0x01c20080 0x4>; |
195 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
196 | clock-output-names = "nand"; | |
197 | }; | |
198 | ||
199 | ms_clk: clk@01c20084 { | |
200 | #clock-cells = <0>; | |
bf6534a1 | 201 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
8dc36bff EL |
202 | reg = <0x01c20084 0x4>; |
203 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
204 | clock-output-names = "ms"; | |
205 | }; | |
206 | ||
207 | mmc0_clk: clk@01c20088 { | |
208 | #clock-cells = <0>; | |
bf6534a1 | 209 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
8dc36bff EL |
210 | reg = <0x01c20088 0x4>; |
211 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
212 | clock-output-names = "mmc0"; | |
213 | }; | |
214 | ||
215 | mmc1_clk: clk@01c2008c { | |
216 | #clock-cells = <0>; | |
bf6534a1 | 217 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
8dc36bff EL |
218 | reg = <0x01c2008c 0x4>; |
219 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
220 | clock-output-names = "mmc1"; | |
221 | }; | |
222 | ||
223 | mmc2_clk: clk@01c20090 { | |
224 | #clock-cells = <0>; | |
bf6534a1 | 225 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
8dc36bff EL |
226 | reg = <0x01c20090 0x4>; |
227 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
228 | clock-output-names = "mmc2"; | |
229 | }; | |
230 | ||
231 | ts_clk: clk@01c20098 { | |
232 | #clock-cells = <0>; | |
bf6534a1 | 233 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
8dc36bff EL |
234 | reg = <0x01c20098 0x4>; |
235 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
236 | clock-output-names = "ts"; | |
237 | }; | |
238 | ||
239 | ss_clk: clk@01c2009c { | |
240 | #clock-cells = <0>; | |
bf6534a1 | 241 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
8dc36bff EL |
242 | reg = <0x01c2009c 0x4>; |
243 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
244 | clock-output-names = "ss"; | |
245 | }; | |
246 | ||
247 | spi0_clk: clk@01c200a0 { | |
248 | #clock-cells = <0>; | |
bf6534a1 | 249 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
8dc36bff EL |
250 | reg = <0x01c200a0 0x4>; |
251 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
252 | clock-output-names = "spi0"; | |
253 | }; | |
254 | ||
255 | spi1_clk: clk@01c200a4 { | |
256 | #clock-cells = <0>; | |
bf6534a1 | 257 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
8dc36bff EL |
258 | reg = <0x01c200a4 0x4>; |
259 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
260 | clock-output-names = "spi1"; | |
261 | }; | |
262 | ||
263 | spi2_clk: clk@01c200a8 { | |
264 | #clock-cells = <0>; | |
bf6534a1 | 265 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
8dc36bff EL |
266 | reg = <0x01c200a8 0x4>; |
267 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
268 | clock-output-names = "spi2"; | |
269 | }; | |
270 | ||
271 | ir0_clk: clk@01c200b0 { | |
272 | #clock-cells = <0>; | |
bf6534a1 | 273 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
8dc36bff EL |
274 | reg = <0x01c200b0 0x4>; |
275 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
276 | clock-output-names = "ir0"; | |
277 | }; | |
118c07ae | 278 | |
4c5d72f8 RB |
279 | usb_clk: clk@01c200cc { |
280 | #clock-cells = <1>; | |
281 | #reset-cells = <1>; | |
282 | compatible = "allwinner,sun5i-a13-usb-clk"; | |
283 | reg = <0x01c200cc 0x4>; | |
284 | clocks = <&pll6 1>; | |
285 | clock-output-names = "usb_ohci0", "usb_phy"; | |
286 | }; | |
287 | ||
118c07ae EL |
288 | mbus_clk: clk@01c2015c { |
289 | #clock-cells = <0>; | |
bf6534a1 | 290 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
118c07ae EL |
291 | reg = <0x01c2015c 0x4>; |
292 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
293 | clock-output-names = "mbus"; | |
294 | }; | |
d3ae078e MR |
295 | }; |
296 | ||
9e199292 | 297 | soc@01c00000 { |
d3ae078e MR |
298 | compatible = "simple-bus"; |
299 | #address-cells = <1>; | |
300 | #size-cells = <1>; | |
d3ae078e MR |
301 | ranges; |
302 | ||
8a689569 MR |
303 | spi0: spi@01c05000 { |
304 | compatible = "allwinner,sun4i-a10-spi"; | |
305 | reg = <0x01c05000 0x1000>; | |
306 | interrupts = <10>; | |
307 | clocks = <&ahb_gates 20>, <&spi0_clk>; | |
308 | clock-names = "ahb", "mod"; | |
309 | status = "disabled"; | |
310 | #address-cells = <1>; | |
311 | #size-cells = <0>; | |
312 | }; | |
313 | ||
314 | spi1: spi@01c06000 { | |
315 | compatible = "allwinner,sun4i-a10-spi"; | |
316 | reg = <0x01c06000 0x1000>; | |
317 | interrupts = <11>; | |
318 | clocks = <&ahb_gates 21>, <&spi1_clk>; | |
319 | clock-names = "ahb", "mod"; | |
320 | status = "disabled"; | |
321 | #address-cells = <1>; | |
322 | #size-cells = <0>; | |
323 | }; | |
324 | ||
d3ae078e | 325 | emac: ethernet@01c0b000 { |
1c70e099 | 326 | compatible = "allwinner,sun4i-a10-emac"; |
d3ae078e MR |
327 | reg = <0x01c0b000 0x1000>; |
328 | interrupts = <55>; | |
329 | clocks = <&ahb_gates 17>; | |
330 | status = "disabled"; | |
331 | }; | |
332 | ||
333 | mdio@01c0b080 { | |
1c70e099 | 334 | compatible = "allwinner,sun4i-a10-mdio"; |
d3ae078e MR |
335 | reg = <0x01c0b080 0x14>; |
336 | status = "disabled"; | |
337 | #address-cells = <1>; | |
338 | #size-cells = <0>; | |
339 | }; | |
340 | ||
d3aed1df DL |
341 | mmc0: mmc@01c0f000 { |
342 | compatible = "allwinner,sun5i-a13-mmc"; | |
343 | reg = <0x01c0f000 0x1000>; | |
344 | clocks = <&ahb_gates 8>, <&mmc0_clk>; | |
345 | clock-names = "ahb", "mmc"; | |
346 | interrupts = <32>; | |
347 | status = "disabled"; | |
348 | }; | |
349 | ||
350 | mmc1: mmc@01c10000 { | |
351 | compatible = "allwinner,sun5i-a13-mmc"; | |
352 | reg = <0x01c10000 0x1000>; | |
353 | clocks = <&ahb_gates 9>, <&mmc1_clk>; | |
354 | clock-names = "ahb", "mmc"; | |
355 | interrupts = <33>; | |
356 | status = "disabled"; | |
357 | }; | |
358 | ||
359 | mmc2: mmc@01c11000 { | |
360 | compatible = "allwinner,sun5i-a13-mmc"; | |
361 | reg = <0x01c11000 0x1000>; | |
362 | clocks = <&ahb_gates 10>, <&mmc2_clk>; | |
363 | clock-names = "ahb", "mmc"; | |
364 | interrupts = <34>; | |
365 | status = "disabled"; | |
366 | }; | |
367 | ||
06c7d52f RB |
368 | usbphy: phy@01c13400 { |
369 | #phy-cells = <1>; | |
370 | compatible = "allwinner,sun5i-a13-usb-phy"; | |
371 | reg = <0x01c13400 0x10 0x01c14800 0x4>; | |
372 | reg-names = "phy_ctrl", "pmu1"; | |
373 | clocks = <&usb_clk 8>; | |
374 | clock-names = "usb_phy"; | |
375 | resets = <&usb_clk 1>; | |
376 | reset-names = "usb1_reset"; | |
377 | status = "disabled"; | |
378 | }; | |
379 | ||
380 | ehci0: usb@01c14000 { | |
381 | compatible = "allwinner,sun5i-a10s-ehci", "generic-ehci"; | |
382 | reg = <0x01c14000 0x100>; | |
383 | interrupts = <39>; | |
384 | clocks = <&ahb_gates 1>; | |
385 | phys = <&usbphy 1>; | |
386 | phy-names = "usb"; | |
387 | status = "disabled"; | |
388 | }; | |
389 | ||
390 | ohci0: usb@01c14400 { | |
391 | compatible = "allwinner,sun5i-a10s-ohci", "generic-ohci"; | |
392 | reg = <0x01c14400 0x100>; | |
393 | interrupts = <40>; | |
394 | clocks = <&usb_clk 6>, <&ahb_gates 2>; | |
395 | phys = <&usbphy 1>; | |
396 | phy-names = "usb"; | |
397 | status = "disabled"; | |
398 | }; | |
399 | ||
8a689569 MR |
400 | spi2: spi@01c17000 { |
401 | compatible = "allwinner,sun4i-a10-spi"; | |
402 | reg = <0x01c17000 0x1000>; | |
403 | interrupts = <12>; | |
404 | clocks = <&ahb_gates 22>, <&spi2_clk>; | |
405 | clock-names = "ahb", "mod"; | |
406 | status = "disabled"; | |
407 | #address-cells = <1>; | |
408 | #size-cells = <0>; | |
409 | }; | |
410 | ||
d3ae078e | 411 | intc: interrupt-controller@01c20400 { |
09504a7d | 412 | compatible = "allwinner,sun4i-a10-ic"; |
d3ae078e MR |
413 | reg = <0x01c20400 0x400>; |
414 | interrupt-controller; | |
415 | #interrupt-cells = <1>; | |
416 | }; | |
417 | ||
418 | pio: pinctrl@01c20800 { | |
419 | compatible = "allwinner,sun5i-a10s-pinctrl"; | |
420 | reg = <0x01c20800 0x400>; | |
421 | interrupts = <28>; | |
422 | clocks = <&apb0_gates 5>; | |
423 | gpio-controller; | |
424 | interrupt-controller; | |
7d4ff96d | 425 | #interrupt-cells = <2>; |
d3ae078e MR |
426 | #size-cells = <0>; |
427 | #gpio-cells = <3>; | |
428 | ||
429 | uart0_pins_a: uart0@0 { | |
430 | allwinner,pins = "PB19", "PB20"; | |
431 | allwinner,function = "uart0"; | |
432 | allwinner,drive = <0>; | |
433 | allwinner,pull = <0>; | |
434 | }; | |
435 | ||
436 | uart2_pins_a: uart2@0 { | |
437 | allwinner,pins = "PC18", "PC19"; | |
438 | allwinner,function = "uart2"; | |
439 | allwinner,drive = <0>; | |
440 | allwinner,pull = <0>; | |
441 | }; | |
442 | ||
443 | uart3_pins_a: uart3@0 { | |
444 | allwinner,pins = "PG9", "PG10"; | |
445 | allwinner,function = "uart3"; | |
446 | allwinner,drive = <0>; | |
447 | allwinner,pull = <0>; | |
448 | }; | |
449 | ||
450 | emac_pins_a: emac0@0 { | |
451 | allwinner,pins = "PA0", "PA1", "PA2", | |
452 | "PA3", "PA4", "PA5", "PA6", | |
453 | "PA7", "PA8", "PA9", "PA10", | |
454 | "PA11", "PA12", "PA13", "PA14", | |
455 | "PA15", "PA16"; | |
456 | allwinner,function = "emac"; | |
457 | allwinner,drive = <0>; | |
458 | allwinner,pull = <0>; | |
459 | }; | |
170ab436 EL |
460 | |
461 | i2c0_pins_a: i2c0@0 { | |
462 | allwinner,pins = "PB0", "PB1"; | |
463 | allwinner,function = "i2c0"; | |
464 | allwinner,drive = <0>; | |
465 | allwinner,pull = <0>; | |
466 | }; | |
467 | ||
468 | i2c1_pins_a: i2c1@0 { | |
469 | allwinner,pins = "PB15", "PB16"; | |
470 | allwinner,function = "i2c1"; | |
471 | allwinner,drive = <0>; | |
472 | allwinner,pull = <0>; | |
473 | }; | |
474 | ||
475 | i2c2_pins_a: i2c2@0 { | |
476 | allwinner,pins = "PB17", "PB18"; | |
477 | allwinner,function = "i2c2"; | |
478 | allwinner,drive = <0>; | |
479 | allwinner,pull = <0>; | |
480 | }; | |
6da50f13 HG |
481 | |
482 | mmc0_pins_a: mmc0@0 { | |
483 | allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; | |
484 | allwinner,function = "mmc0"; | |
485 | allwinner,drive = <2>; | |
486 | allwinner,pull = <0>; | |
487 | }; | |
488 | ||
489 | mmc1_pins_a: mmc1@0 { | |
490 | allwinner,pins = "PG3","PG4","PG5","PG6","PG7","PG8"; | |
491 | allwinner,function = "mmc1"; | |
492 | allwinner,drive = <2>; | |
493 | allwinner,pull = <0>; | |
494 | }; | |
d3ae078e MR |
495 | }; |
496 | ||
497 | timer@01c20c00 { | |
b4f26440 | 498 | compatible = "allwinner,sun4i-a10-timer"; |
d3ae078e MR |
499 | reg = <0x01c20c00 0x90>; |
500 | interrupts = <22>; | |
501 | clocks = <&osc24M>; | |
502 | }; | |
503 | ||
504 | wdt: watchdog@01c20c90 { | |
ca5d04d9 | 505 | compatible = "allwinner,sun4i-a10-wdt"; |
d3ae078e MR |
506 | reg = <0x01c20c90 0x10>; |
507 | }; | |
508 | ||
2bad969f | 509 | sid: eeprom@01c23800 { |
043d56ee | 510 | compatible = "allwinner,sun4i-a10-sid"; |
2bad969f OS |
511 | reg = <0x01c23800 0x10>; |
512 | }; | |
513 | ||
f65c93a0 | 514 | rtp: rtp@01c25000 { |
40dd8f3b | 515 | compatible = "allwinner,sun4i-a10-ts"; |
f65c93a0 HG |
516 | reg = <0x01c25000 0x100>; |
517 | interrupts = <29>; | |
518 | }; | |
519 | ||
d3ae078e MR |
520 | uart0: serial@01c28000 { |
521 | compatible = "snps,dw-apb-uart"; | |
522 | reg = <0x01c28000 0x400>; | |
523 | interrupts = <1>; | |
524 | reg-shift = <2>; | |
525 | reg-io-width = <4>; | |
526 | clocks = <&apb1_gates 16>; | |
527 | status = "disabled"; | |
528 | }; | |
529 | ||
530 | uart1: serial@01c28400 { | |
531 | compatible = "snps,dw-apb-uart"; | |
532 | reg = <0x01c28400 0x400>; | |
533 | interrupts = <2>; | |
534 | reg-shift = <2>; | |
535 | reg-io-width = <4>; | |
536 | clocks = <&apb1_gates 17>; | |
537 | status = "disabled"; | |
538 | }; | |
539 | ||
540 | uart2: serial@01c28800 { | |
541 | compatible = "snps,dw-apb-uart"; | |
542 | reg = <0x01c28800 0x400>; | |
543 | interrupts = <3>; | |
544 | reg-shift = <2>; | |
545 | reg-io-width = <4>; | |
546 | clocks = <&apb1_gates 18>; | |
547 | status = "disabled"; | |
548 | }; | |
549 | ||
550 | uart3: serial@01c28c00 { | |
551 | compatible = "snps,dw-apb-uart"; | |
552 | reg = <0x01c28c00 0x400>; | |
553 | interrupts = <4>; | |
554 | reg-shift = <2>; | |
555 | reg-io-width = <4>; | |
556 | clocks = <&apb1_gates 19>; | |
557 | status = "disabled"; | |
558 | }; | |
ca3d4ed5 EL |
559 | |
560 | i2c0: i2c@01c2ac00 { | |
561 | #address-cells = <1>; | |
562 | #size-cells = <0>; | |
d275545e | 563 | compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c"; |
ca3d4ed5 EL |
564 | reg = <0x01c2ac00 0x400>; |
565 | interrupts = <7>; | |
566 | clocks = <&apb1_gates 0>; | |
567 | clock-frequency = <100000>; | |
568 | status = "disabled"; | |
569 | }; | |
570 | ||
571 | i2c1: i2c@01c2b000 { | |
572 | #address-cells = <1>; | |
573 | #size-cells = <0>; | |
d275545e | 574 | compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c"; |
ca3d4ed5 EL |
575 | reg = <0x01c2b000 0x400>; |
576 | interrupts = <8>; | |
577 | clocks = <&apb1_gates 1>; | |
578 | clock-frequency = <100000>; | |
579 | status = "disabled"; | |
580 | }; | |
581 | ||
582 | i2c2: i2c@01c2b400 { | |
583 | #address-cells = <1>; | |
584 | #size-cells = <0>; | |
d275545e | 585 | compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c"; |
ca3d4ed5 EL |
586 | reg = <0x01c2b400 0x400>; |
587 | interrupts = <9>; | |
588 | clocks = <&apb1_gates 2>; | |
589 | clock-frequency = <100000>; | |
590 | status = "disabled"; | |
591 | }; | |
f2b50028 MR |
592 | |
593 | timer@01c60000 { | |
594 | compatible = "allwinner,sun5i-a13-hstimer"; | |
595 | reg = <0x01c60000 0x1000>; | |
596 | interrupts = <82>, <83>; | |
597 | clocks = <&ahb_gates 28>; | |
598 | }; | |
d3ae078e MR |
599 | }; |
600 | }; |