projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| d3ae078e MR |
1 | /* |
| 2 | * Copyright 2013 Maxime Ripard | |
| 3 | * | |
| 4 | * Maxime Ripard <maxime.ripard@free-electrons.com> | |
| 5 | * | |
| 6 | * The code contained herein is licensed under the GNU General Public | |
| 7 | * License. You may obtain a copy of the GNU General Public License | |
| 8 | * Version 2 or later at the following locations: | |
| 9 | * | |
| 10 | * http://www.opensource.org/licenses/gpl-license.html | |
| 11 | * http://www.gnu.org/copyleft/gpl.html | |
| 12 | */ | |
| 13 | ||
| 14 | /include/ "skeleton.dtsi" | |
| 15 | ||
| 16 | / { | |
| 17 | interrupt-parent = <&intc>; | |
| 18 | ||
| e751cce9 EL |
19 | aliases { |
| 20 | ethernet0 = &emac; | |
| 4dd4065f MR |
21 | serial0 = &uart0; |
| 22 | serial1 = &uart1; | |
| 23 | serial2 = &uart2; | |
| 24 | serial3 = &uart3; | |
| e751cce9 EL |
25 | }; |
| 26 | ||
| d501841f HG |
27 | chosen { |
| 28 | #address-cells = <1>; | |
| 29 | #size-cells = <1>; | |
| 30 | ranges; | |
| 31 | ||
| a9f8cda3 HG |
32 | framebuffer@0 { |
| 33 | compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; | |
| 34 | allwinner,pipeline = "de_be0-lcd0-hdmi"; | |
| 678e75d3 HG |
35 | clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, |
| 36 | <&ahb_gates 44>; | |
| d501841f HG |
37 | status = "disabled"; |
| 38 | }; | |
| 39 | }; | |
| 40 | ||
| d3ae078e MR |
41 | cpus { |
| 42 | cpu@0 { | |
| 43 | compatible = "arm,cortex-a8"; | |
| 44 | }; | |
| 45 | }; | |
| 46 | ||
| 47 | memory { | |
| 48 | reg = <0x40000000 0x20000000>; | |
| 49 | }; | |
| 50 | ||
| 51 | clocks { | |
| 52 | #address-cells = <1>; | |
| 53 | #size-cells = <1>; | |
| 54 | ranges; | |
| 55 | ||
| 56 | /* | |
| 57 | * This is a dummy clock, to be used as placeholder on | |
| 58 | * other mux clocks when a specific parent clock is not | |
| 59 | * yet implemented. It should be dropped when the driver | |
| 60 | * is complete. | |
| 61 | */ | |
| 62 | dummy: dummy { | |
| 63 | #clock-cells = <0>; | |
| 64 | compatible = "fixed-clock"; | |
| 65 | clock-frequency = <0>; | |
| 66 | }; | |
| 67 | ||
| 3dce8324 | 68 | osc24M: clk@01c20050 { |
| d3ae078e | 69 | #clock-cells = <0>; |
| bf6534a1 | 70 | compatible = "allwinner,sun4i-a10-osc-clk"; |
| d3ae078e MR |
71 | reg = <0x01c20050 0x4>; |
| 72 | clock-frequency = <24000000>; | |
| 3dce8324 | 73 | clock-output-names = "osc24M"; |
| d3ae078e MR |
74 | }; |
| 75 | ||
| 3dce8324 | 76 | osc32k: clk@0 { |
| d3ae078e MR |
77 | #clock-cells = <0>; |
| 78 | compatible = "fixed-clock"; | |
| 79 | clock-frequency = <32768>; | |
| 3dce8324 | 80 | clock-output-names = "osc32k"; |
| d3ae078e MR |
81 | }; |
| 82 | ||
| 3dce8324 | 83 | pll1: clk@01c20000 { |
| d3ae078e | 84 | #clock-cells = <0>; |
| bf6534a1 | 85 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
| d3ae078e MR |
86 | reg = <0x01c20000 0x4>; |
| 87 | clocks = <&osc24M>; | |
| 3dce8324 | 88 | clock-output-names = "pll1"; |
| d3ae078e MR |
89 | }; |
| 90 | ||
| 3dce8324 | 91 | pll4: clk@01c20018 { |
| ec5589f7 | 92 | #clock-cells = <0>; |
| bf6534a1 | 93 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
| ec5589f7 EL |
94 | reg = <0x01c20018 0x4>; |
| 95 | clocks = <&osc24M>; | |
| 3dce8324 | 96 | clock-output-names = "pll4"; |
| ec5589f7 EL |
97 | }; |
| 98 | ||
| 3dce8324 | 99 | pll5: clk@01c20020 { |
| c3e5e66b | 100 | #clock-cells = <1>; |
| bf6534a1 | 101 | compatible = "allwinner,sun4i-a10-pll5-clk"; |
| c3e5e66b EL |
102 | reg = <0x01c20020 0x4>; |
| 103 | clocks = <&osc24M>; | |
| 104 | clock-output-names = "pll5_ddr", "pll5_other"; | |
| 105 | }; | |
| 106 | ||
| 3dce8324 | 107 | pll6: clk@01c20028 { |
| c3e5e66b | 108 | #clock-cells = <1>; |
| bf6534a1 | 109 | compatible = "allwinner,sun4i-a10-pll6-clk"; |
| c3e5e66b EL |
110 | reg = <0x01c20028 0x4>; |
| 111 | clocks = <&osc24M>; | |
| 112 | clock-output-names = "pll6_sata", "pll6_other", "pll6"; | |
| 113 | }; | |
| 114 | ||
| d3ae078e MR |
115 | /* dummy is 200M */ |
| 116 | cpu: cpu@01c20054 { | |
| 117 | #clock-cells = <0>; | |
| bf6534a1 | 118 | compatible = "allwinner,sun4i-a10-cpu-clk"; |
| d3ae078e MR |
119 | reg = <0x01c20054 0x4>; |
| 120 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; | |
| 3dce8324 | 121 | clock-output-names = "cpu"; |
| d3ae078e MR |
122 | }; |
| 123 | ||
| 124 | axi: axi@01c20054 { | |
| 125 | #clock-cells = <0>; | |
| bf6534a1 | 126 | compatible = "allwinner,sun4i-a10-axi-clk"; |
| d3ae078e MR |
127 | reg = <0x01c20054 0x4>; |
| 128 | clocks = <&cpu>; | |
| 3dce8324 | 129 | clock-output-names = "axi"; |
| d3ae078e MR |
130 | }; |
| 131 | ||
| 3dce8324 | 132 | axi_gates: clk@01c2005c { |
| d3ae078e | 133 | #clock-cells = <1>; |
| bf6534a1 | 134 | compatible = "allwinner,sun4i-a10-axi-gates-clk"; |
| d3ae078e MR |
135 | reg = <0x01c2005c 0x4>; |
| 136 | clocks = <&axi>; | |
| 137 | clock-output-names = "axi_dram"; | |
| 138 | }; | |
| 139 | ||
| 140 | ahb: ahb@01c20054 { | |
| 141 | #clock-cells = <0>; | |
| bf6534a1 | 142 | compatible = "allwinner,sun4i-a10-ahb-clk"; |
| d3ae078e MR |
143 | reg = <0x01c20054 0x4>; |
| 144 | clocks = <&axi>; | |
| 3dce8324 | 145 | clock-output-names = "ahb"; |
| d3ae078e MR |
146 | }; |
| 147 | ||
| 3dce8324 | 148 | ahb_gates: clk@01c20060 { |
| d3ae078e | 149 | #clock-cells = <1>; |
| 29bb8054 | 150 | compatible = "allwinner,sun5i-a10s-ahb-gates-clk"; |
| d3ae078e MR |
151 | reg = <0x01c20060 0x8>; |
| 152 | clocks = <&ahb>; | |
| 29bb8054 MR |
153 | clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci", |
| 154 | "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0", | |
| 155 | "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram", | |
| 156 | "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1", | |
| 157 | "ahb_spi2", "ahb_gps", "ahb_stimer", "ahb_ve", | |
| 158 | "ahb_tve", "ahb_lcd", "ahb_csi", "ahb_hdmi", | |
| 159 | "ahb_de_be", "ahb_de_fe", "ahb_iep", "ahb_mali400"; | |
| d3ae078e MR |
160 | }; |
| 161 | ||
| 162 | apb0: apb0@01c20054 { | |
| 163 | #clock-cells = <0>; | |
| bf6534a1 | 164 | compatible = "allwinner,sun4i-a10-apb0-clk"; |
| d3ae078e MR |
165 | reg = <0x01c20054 0x4>; |
| 166 | clocks = <&ahb>; | |
| 3dce8324 | 167 | clock-output-names = "apb0"; |
| d3ae078e MR |
168 | }; |
| 169 | ||
| 3dce8324 | 170 | apb0_gates: clk@01c20068 { |
| d3ae078e | 171 | #clock-cells = <1>; |
| 29bb8054 | 172 | compatible = "allwinner,sun5i-a10s-apb0-gates-clk"; |
| d3ae078e MR |
173 | reg = <0x01c20068 0x4>; |
| 174 | clocks = <&apb0>; | |
| 29bb8054 MR |
175 | clock-output-names = "apb0_codec", "apb0_iis", "apb0_pio", |
| 176 | "apb0_ir", "apb0_keypad"; | |
| d3ae078e MR |
177 | }; |
| 178 | ||
| d3ae078e MR |
179 | apb1_mux: apb1_mux@01c20058 { |
| 180 | #clock-cells = <0>; | |
| bf6534a1 | 181 | compatible = "allwinner,sun4i-a10-apb1-mux-clk"; |
| d3ae078e | 182 | reg = <0x01c20058 0x4>; |
| c3e5e66b | 183 | clocks = <&osc24M>, <&pll6 1>, <&osc32k>; |
| 3dce8324 | 184 | clock-output-names = "apb1_mux"; |
| d3ae078e MR |
185 | }; |
| 186 | ||
| 187 | apb1: apb1@01c20058 { | |
| 188 | #clock-cells = <0>; | |
| bf6534a1 | 189 | compatible = "allwinner,sun4i-a10-apb1-clk"; |
| d3ae078e MR |
190 | reg = <0x01c20058 0x4>; |
| 191 | clocks = <&apb1_mux>; | |
| 3dce8324 | 192 | clock-output-names = "apb1"; |
| d3ae078e MR |
193 | }; |
| 194 | ||
| 3dce8324 | 195 | apb1_gates: clk@01c2006c { |
| d3ae078e | 196 | #clock-cells = <1>; |
| 29bb8054 | 197 | compatible = "allwinner,sun5i-a10s-apb1-gates-clk"; |
| d3ae078e MR |
198 | reg = <0x01c2006c 0x4>; |
| 199 | clocks = <&apb1>; | |
| 200 | clock-output-names = "apb1_i2c0", "apb1_i2c1", | |
| 29bb8054 MR |
201 | "apb1_i2c2", "apb1_uart0", "apb1_uart1", |
| 202 | "apb1_uart2", "apb1_uart3"; | |
| d3ae078e | 203 | }; |
| 8dc36bff EL |
204 | |
| 205 | nand_clk: clk@01c20080 { | |
| 206 | #clock-cells = <0>; | |
| bf6534a1 | 207 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 8dc36bff EL |
208 | reg = <0x01c20080 0x4>; |
| 209 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 210 | clock-output-names = "nand"; | |
| 211 | }; | |
| 212 | ||
| 213 | ms_clk: clk@01c20084 { | |
| 214 | #clock-cells = <0>; | |
| bf6534a1 | 215 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 8dc36bff EL |
216 | reg = <0x01c20084 0x4>; |
| 217 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 218 | clock-output-names = "ms"; | |
| 219 | }; | |
| 220 | ||
| 221 | mmc0_clk: clk@01c20088 { | |
| 222 | #clock-cells = <0>; | |
| bf6534a1 | 223 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 8dc36bff EL |
224 | reg = <0x01c20088 0x4>; |
| 225 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 226 | clock-output-names = "mmc0"; | |
| 227 | }; | |
| 228 | ||
| 229 | mmc1_clk: clk@01c2008c { | |
| 230 | #clock-cells = <0>; | |
| bf6534a1 | 231 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 8dc36bff EL |
232 | reg = <0x01c2008c 0x4>; |
| 233 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 234 | clock-output-names = "mmc1"; | |
| 235 | }; | |
| 236 | ||
| 237 | mmc2_clk: clk@01c20090 { | |
| 238 | #clock-cells = <0>; | |
| bf6534a1 | 239 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 8dc36bff EL |
240 | reg = <0x01c20090 0x4>; |
| 241 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 242 | clock-output-names = "mmc2"; | |
| 243 | }; | |
| 244 | ||
| 245 | ts_clk: clk@01c20098 { | |
| 246 | #clock-cells = <0>; | |
| bf6534a1 | 247 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 8dc36bff EL |
248 | reg = <0x01c20098 0x4>; |
| 249 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 250 | clock-output-names = "ts"; | |
| 251 | }; | |
| 252 | ||
| 253 | ss_clk: clk@01c2009c { | |
| 254 | #clock-cells = <0>; | |
| bf6534a1 | 255 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 8dc36bff EL |
256 | reg = <0x01c2009c 0x4>; |
| 257 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 258 | clock-output-names = "ss"; | |
| 259 | }; | |
| 260 | ||
| 261 | spi0_clk: clk@01c200a0 { | |
| 262 | #clock-cells = <0>; | |
| bf6534a1 | 263 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 8dc36bff EL |
264 | reg = <0x01c200a0 0x4>; |
| 265 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 266 | clock-output-names = "spi0"; | |
| 267 | }; | |
| 268 | ||
| 269 | spi1_clk: clk@01c200a4 { | |
| 270 | #clock-cells = <0>; | |
| bf6534a1 | 271 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 8dc36bff EL |
272 | reg = <0x01c200a4 0x4>; |
| 273 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 274 | clock-output-names = "spi1"; | |
| 275 | }; | |
| 276 | ||
| 277 | spi2_clk: clk@01c200a8 { | |
| 278 | #clock-cells = <0>; | |
| bf6534a1 | 279 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 8dc36bff EL |
280 | reg = <0x01c200a8 0x4>; |
| 281 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 282 | clock-output-names = "spi2"; | |
| 283 | }; | |
| 284 | ||
| 285 | ir0_clk: clk@01c200b0 { | |
| 286 | #clock-cells = <0>; | |
| bf6534a1 | 287 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 8dc36bff EL |
288 | reg = <0x01c200b0 0x4>; |
| 289 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 290 | clock-output-names = "ir0"; | |
| 291 | }; | |
| 118c07ae | 292 | |
| 4c5d72f8 RB |
293 | usb_clk: clk@01c200cc { |
| 294 | #clock-cells = <1>; | |
| 295 | #reset-cells = <1>; | |
| 296 | compatible = "allwinner,sun5i-a13-usb-clk"; | |
| 297 | reg = <0x01c200cc 0x4>; | |
| 298 | clocks = <&pll6 1>; | |
| 299 | clock-output-names = "usb_ohci0", "usb_phy"; | |
| 300 | }; | |
| 301 | ||
| 118c07ae EL |
302 | mbus_clk: clk@01c2015c { |
| 303 | #clock-cells = <0>; | |
| 7868c5eb | 304 | compatible = "allwinner,sun5i-a13-mbus-clk"; |
| 118c07ae EL |
305 | reg = <0x01c2015c 0x4>; |
| 306 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 307 | clock-output-names = "mbus"; | |
| 308 | }; | |
| d3ae078e MR |
309 | }; |
| 310 | ||
| 9e199292 | 311 | soc@01c00000 { |
| d3ae078e MR |
312 | compatible = "simple-bus"; |
| 313 | #address-cells = <1>; | |
| 314 | #size-cells = <1>; | |
| d3ae078e MR |
315 | ranges; |
| 316 | ||
| 6a5775e4 EL |
317 | dma: dma-controller@01c02000 { |
| 318 | compatible = "allwinner,sun4i-a10-dma"; | |
| 319 | reg = <0x01c02000 0x1000>; | |
| 320 | interrupts = <27>; | |
| 321 | clocks = <&ahb_gates 6>; | |
| 322 | #dma-cells = <2>; | |
| 323 | }; | |
| 324 | ||
| 8a689569 MR |
325 | spi0: spi@01c05000 { |
| 326 | compatible = "allwinner,sun4i-a10-spi"; | |
| 327 | reg = <0x01c05000 0x1000>; | |
| 328 | interrupts = <10>; | |
| 329 | clocks = <&ahb_gates 20>, <&spi0_clk>; | |
| 330 | clock-names = "ahb", "mod"; | |
| fed4c5c6 EL |
331 | dmas = <&dma 1 27>, <&dma 1 26>; |
| 332 | dma-names = "rx", "tx"; | |
| 8a689569 MR |
333 | status = "disabled"; |
| 334 | #address-cells = <1>; | |
| 335 | #size-cells = <0>; | |
| 336 | }; | |
| 337 | ||
| 338 | spi1: spi@01c06000 { | |
| 339 | compatible = "allwinner,sun4i-a10-spi"; | |
| 340 | reg = <0x01c06000 0x1000>; | |
| 341 | interrupts = <11>; | |
| 342 | clocks = <&ahb_gates 21>, <&spi1_clk>; | |
| 343 | clock-names = "ahb", "mod"; | |
| fed4c5c6 EL |
344 | dmas = <&dma 1 9>, <&dma 1 8>; |
| 345 | dma-names = "rx", "tx"; | |
| 8a689569 MR |
346 | status = "disabled"; |
| 347 | #address-cells = <1>; | |
| 348 | #size-cells = <0>; | |
| 349 | }; | |
| 350 | ||
| d3ae078e | 351 | emac: ethernet@01c0b000 { |
| 1c70e099 | 352 | compatible = "allwinner,sun4i-a10-emac"; |
| d3ae078e MR |
353 | reg = <0x01c0b000 0x1000>; |
| 354 | interrupts = <55>; | |
| 355 | clocks = <&ahb_gates 17>; | |
| 356 | status = "disabled"; | |
| 357 | }; | |
| 358 | ||
| 359 | mdio@01c0b080 { | |
| 1c70e099 | 360 | compatible = "allwinner,sun4i-a10-mdio"; |
| d3ae078e MR |
361 | reg = <0x01c0b080 0x14>; |
| 362 | status = "disabled"; | |
| 363 | #address-cells = <1>; | |
| 364 | #size-cells = <0>; | |
| 365 | }; | |
| 366 | ||
| d3aed1df DL |
367 | mmc0: mmc@01c0f000 { |
| 368 | compatible = "allwinner,sun5i-a13-mmc"; | |
| 369 | reg = <0x01c0f000 0x1000>; | |
| 370 | clocks = <&ahb_gates 8>, <&mmc0_clk>; | |
| 371 | clock-names = "ahb", "mmc"; | |
| 372 | interrupts = <32>; | |
| 373 | status = "disabled"; | |
| 374 | }; | |
| 375 | ||
| 376 | mmc1: mmc@01c10000 { | |
| 377 | compatible = "allwinner,sun5i-a13-mmc"; | |
| 378 | reg = <0x01c10000 0x1000>; | |
| 379 | clocks = <&ahb_gates 9>, <&mmc1_clk>; | |
| 380 | clock-names = "ahb", "mmc"; | |
| 381 | interrupts = <33>; | |
| 382 | status = "disabled"; | |
| 383 | }; | |
| 384 | ||
| 385 | mmc2: mmc@01c11000 { | |
| 386 | compatible = "allwinner,sun5i-a13-mmc"; | |
| 387 | reg = <0x01c11000 0x1000>; | |
| 388 | clocks = <&ahb_gates 10>, <&mmc2_clk>; | |
| 389 | clock-names = "ahb", "mmc"; | |
| 390 | interrupts = <34>; | |
| 391 | status = "disabled"; | |
| 392 | }; | |
| 393 | ||
| 06c7d52f RB |
394 | usbphy: phy@01c13400 { |
| 395 | #phy-cells = <1>; | |
| 396 | compatible = "allwinner,sun5i-a13-usb-phy"; | |
| 397 | reg = <0x01c13400 0x10 0x01c14800 0x4>; | |
| 398 | reg-names = "phy_ctrl", "pmu1"; | |
| 399 | clocks = <&usb_clk 8>; | |
| 400 | clock-names = "usb_phy"; | |
| 401 | resets = <&usb_clk 1>; | |
| 402 | reset-names = "usb1_reset"; | |
| 403 | status = "disabled"; | |
| 404 | }; | |
| 405 | ||
| 406 | ehci0: usb@01c14000 { | |
| 407 | compatible = "allwinner,sun5i-a10s-ehci", "generic-ehci"; | |
| 408 | reg = <0x01c14000 0x100>; | |
| 409 | interrupts = <39>; | |
| 410 | clocks = <&ahb_gates 1>; | |
| 411 | phys = <&usbphy 1>; | |
| 412 | phy-names = "usb"; | |
| 413 | status = "disabled"; | |
| 414 | }; | |
| 415 | ||
| 416 | ohci0: usb@01c14400 { | |
| 417 | compatible = "allwinner,sun5i-a10s-ohci", "generic-ohci"; | |
| 418 | reg = <0x01c14400 0x100>; | |
| 419 | interrupts = <40>; | |
| 420 | clocks = <&usb_clk 6>, <&ahb_gates 2>; | |
| 421 | phys = <&usbphy 1>; | |
| 422 | phy-names = "usb"; | |
| 423 | status = "disabled"; | |
| 424 | }; | |
| 425 | ||
| 8a689569 MR |
426 | spi2: spi@01c17000 { |
| 427 | compatible = "allwinner,sun4i-a10-spi"; | |
| 428 | reg = <0x01c17000 0x1000>; | |
| 429 | interrupts = <12>; | |
| 430 | clocks = <&ahb_gates 22>, <&spi2_clk>; | |
| 431 | clock-names = "ahb", "mod"; | |
| fed4c5c6 EL |
432 | dmas = <&dma 1 29>, <&dma 1 28>; |
| 433 | dma-names = "rx", "tx"; | |
| 8a689569 MR |
434 | status = "disabled"; |
| 435 | #address-cells = <1>; | |
| 436 | #size-cells = <0>; | |
| 437 | }; | |
| 438 | ||
| d3ae078e | 439 | intc: interrupt-controller@01c20400 { |
| 09504a7d | 440 | compatible = "allwinner,sun4i-a10-ic"; |
| d3ae078e MR |
441 | reg = <0x01c20400 0x400>; |
| 442 | interrupt-controller; | |
| 443 | #interrupt-cells = <1>; | |
| 444 | }; | |
| 445 | ||
| 446 | pio: pinctrl@01c20800 { | |
| 447 | compatible = "allwinner,sun5i-a10s-pinctrl"; | |
| 448 | reg = <0x01c20800 0x400>; | |
| 449 | interrupts = <28>; | |
| 450 | clocks = <&apb0_gates 5>; | |
| 451 | gpio-controller; | |
| 452 | interrupt-controller; | |
| 7d4ff96d | 453 | #interrupt-cells = <2>; |
| d3ae078e MR |
454 | #size-cells = <0>; |
| 455 | #gpio-cells = <3>; | |
| 456 | ||
| 457 | uart0_pins_a: uart0@0 { | |
| 458 | allwinner,pins = "PB19", "PB20"; | |
| 459 | allwinner,function = "uart0"; | |
| 460 | allwinner,drive = <0>; | |
| 461 | allwinner,pull = <0>; | |
| 462 | }; | |
| 463 | ||
| 464 | uart2_pins_a: uart2@0 { | |
| 465 | allwinner,pins = "PC18", "PC19"; | |
| 466 | allwinner,function = "uart2"; | |
| 467 | allwinner,drive = <0>; | |
| 468 | allwinner,pull = <0>; | |
| 469 | }; | |
| 470 | ||
| 471 | uart3_pins_a: uart3@0 { | |
| 472 | allwinner,pins = "PG9", "PG10"; | |
| 473 | allwinner,function = "uart3"; | |
| 474 | allwinner,drive = <0>; | |
| 475 | allwinner,pull = <0>; | |
| 476 | }; | |
| 477 | ||
| 478 | emac_pins_a: emac0@0 { | |
| 479 | allwinner,pins = "PA0", "PA1", "PA2", | |
| 480 | "PA3", "PA4", "PA5", "PA6", | |
| 481 | "PA7", "PA8", "PA9", "PA10", | |
| 482 | "PA11", "PA12", "PA13", "PA14", | |
| 483 | "PA15", "PA16"; | |
| 484 | allwinner,function = "emac"; | |
| 485 | allwinner,drive = <0>; | |
| 486 | allwinner,pull = <0>; | |
| 487 | }; | |
| 170ab436 EL |
488 | |
| 489 | i2c0_pins_a: i2c0@0 { | |
| 490 | allwinner,pins = "PB0", "PB1"; | |
| 491 | allwinner,function = "i2c0"; | |
| 492 | allwinner,drive = <0>; | |
| 493 | allwinner,pull = <0>; | |
| 494 | }; | |
| 495 | ||
| 496 | i2c1_pins_a: i2c1@0 { | |
| 497 | allwinner,pins = "PB15", "PB16"; | |
| 498 | allwinner,function = "i2c1"; | |
| 499 | allwinner,drive = <0>; | |
| 500 | allwinner,pull = <0>; | |
| 501 | }; | |
| 502 | ||
| 503 | i2c2_pins_a: i2c2@0 { | |
| 504 | allwinner,pins = "PB17", "PB18"; | |
| 505 | allwinner,function = "i2c2"; | |
| 506 | allwinner,drive = <0>; | |
| 507 | allwinner,pull = <0>; | |
| 508 | }; | |
| 6da50f13 HG |
509 | |
| 510 | mmc0_pins_a: mmc0@0 { | |
| 511 | allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; | |
| 512 | allwinner,function = "mmc0"; | |
| 513 | allwinner,drive = <2>; | |
| 514 | allwinner,pull = <0>; | |
| 515 | }; | |
| 516 | ||
| 517 | mmc1_pins_a: mmc1@0 { | |
| 518 | allwinner,pins = "PG3","PG4","PG5","PG6","PG7","PG8"; | |
| 519 | allwinner,function = "mmc1"; | |
| 520 | allwinner,drive = <2>; | |
| 521 | allwinner,pull = <0>; | |
| 522 | }; | |
| d3ae078e MR |
523 | }; |
| 524 | ||
| 525 | timer@01c20c00 { | |
| b4f26440 | 526 | compatible = "allwinner,sun4i-a10-timer"; |
| d3ae078e MR |
527 | reg = <0x01c20c00 0x90>; |
| 528 | interrupts = <22>; | |
| 529 | clocks = <&osc24M>; | |
| 530 | }; | |
| 531 | ||
| 532 | wdt: watchdog@01c20c90 { | |
| ca5d04d9 | 533 | compatible = "allwinner,sun4i-a10-wdt"; |
| d3ae078e MR |
534 | reg = <0x01c20c90 0x10>; |
| 535 | }; | |
| 536 | ||
| 2bad969f | 537 | sid: eeprom@01c23800 { |
| 043d56ee | 538 | compatible = "allwinner,sun4i-a10-sid"; |
| 2bad969f OS |
539 | reg = <0x01c23800 0x10>; |
| 540 | }; | |
| 541 | ||
| f65c93a0 | 542 | rtp: rtp@01c25000 { |
| 40dd8f3b | 543 | compatible = "allwinner,sun4i-a10-ts"; |
| f65c93a0 HG |
544 | reg = <0x01c25000 0x100>; |
| 545 | interrupts = <29>; | |
| 546 | }; | |
| 547 | ||
| d3ae078e MR |
548 | uart0: serial@01c28000 { |
| 549 | compatible = "snps,dw-apb-uart"; | |
| 550 | reg = <0x01c28000 0x400>; | |
| 551 | interrupts = <1>; | |
| 552 | reg-shift = <2>; | |
| 553 | reg-io-width = <4>; | |
| 554 | clocks = <&apb1_gates 16>; | |
| 555 | status = "disabled"; | |
| 556 | }; | |
| 557 | ||
| 558 | uart1: serial@01c28400 { | |
| 559 | compatible = "snps,dw-apb-uart"; | |
| 560 | reg = <0x01c28400 0x400>; | |
| 561 | interrupts = <2>; | |
| 562 | reg-shift = <2>; | |
| 563 | reg-io-width = <4>; | |
| 564 | clocks = <&apb1_gates 17>; | |
| 565 | status = "disabled"; | |
| 566 | }; | |
| 567 | ||
| 568 | uart2: serial@01c28800 { | |
| 569 | compatible = "snps,dw-apb-uart"; | |
| 570 | reg = <0x01c28800 0x400>; | |
| 571 | interrupts = <3>; | |
| 572 | reg-shift = <2>; | |
| 573 | reg-io-width = <4>; | |
| 574 | clocks = <&apb1_gates 18>; | |
| 575 | status = "disabled"; | |
| 576 | }; | |
| 577 | ||
| 578 | uart3: serial@01c28c00 { | |
| 579 | compatible = "snps,dw-apb-uart"; | |
| 580 | reg = <0x01c28c00 0x400>; | |
| 581 | interrupts = <4>; | |
| 582 | reg-shift = <2>; | |
| 583 | reg-io-width = <4>; | |
| 584 | clocks = <&apb1_gates 19>; | |
| 585 | status = "disabled"; | |
| 586 | }; | |
| ca3d4ed5 EL |
587 | |
| 588 | i2c0: i2c@01c2ac00 { | |
| 589 | #address-cells = <1>; | |
| 590 | #size-cells = <0>; | |
| d275545e | 591 | compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c"; |
| ca3d4ed5 EL |
592 | reg = <0x01c2ac00 0x400>; |
| 593 | interrupts = <7>; | |
| 594 | clocks = <&apb1_gates 0>; | |
| ca3d4ed5 EL |
595 | status = "disabled"; |
| 596 | }; | |
| 597 | ||
| 598 | i2c1: i2c@01c2b000 { | |
| 599 | #address-cells = <1>; | |
| 600 | #size-cells = <0>; | |
| d275545e | 601 | compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c"; |
| ca3d4ed5 EL |
602 | reg = <0x01c2b000 0x400>; |
| 603 | interrupts = <8>; | |
| 604 | clocks = <&apb1_gates 1>; | |
| ca3d4ed5 EL |
605 | status = "disabled"; |
| 606 | }; | |
| 607 | ||
| 608 | i2c2: i2c@01c2b400 { | |
| 609 | #address-cells = <1>; | |
| 610 | #size-cells = <0>; | |
| d275545e | 611 | compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c"; |
| ca3d4ed5 EL |
612 | reg = <0x01c2b400 0x400>; |
| 613 | interrupts = <9>; | |
| 614 | clocks = <&apb1_gates 2>; | |
| ca3d4ed5 EL |
615 | status = "disabled"; |
| 616 | }; | |
| f2b50028 MR |
617 | |
| 618 | timer@01c60000 { | |
| 619 | compatible = "allwinner,sun5i-a13-hstimer"; | |
| 620 | reg = <0x01c60000 0x1000>; | |
| 621 | interrupts = <82>, <83>; | |
| 622 | clocks = <&ahb_gates 28>; | |
| 623 | }; | |
| d3ae078e MR |
624 | }; |
| 625 | }; |