projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| d4da2ebb MR |
1 | /* |
| 2 | * Copyright 2012 Maxime Ripard | |
| 3 | * | |
| 4 | * Maxime Ripard <maxime.ripard@free-electrons.com> | |
| 5 | * | |
| 6 | * The code contained herein is licensed under the GNU General Public | |
| 7 | * License. You may obtain a copy of the GNU General Public License | |
| 8 | * Version 2 or later at the following locations: | |
| 9 | * | |
| 10 | * http://www.opensource.org/licenses/gpl-license.html | |
| 11 | * http://www.gnu.org/copyleft/gpl.html | |
| 12 | */ | |
| 13 | ||
| 69144e3b | 14 | /include/ "skeleton.dtsi" |
| d4da2ebb MR |
15 | |
| 16 | / { | |
| 69144e3b MR |
17 | interrupt-parent = <&intc>; |
| 18 | ||
| 19 | cpus { | |
| 8b2efa89 AB |
20 | #address-cells = <1>; |
| 21 | #size-cells = <0>; | |
| 69144e3b | 22 | cpu@0 { |
| 14c44aa5 | 23 | device_type = "cpu"; |
| 69144e3b | 24 | compatible = "arm,cortex-a8"; |
| 14c44aa5 | 25 | reg = <0x0>; |
| 69144e3b MR |
26 | }; |
| 27 | }; | |
| 28 | ||
| d4da2ebb MR |
29 | memory { |
| 30 | reg = <0x40000000 0x20000000>; | |
| 31 | }; | |
| 9e2dcb2f | 32 | |
| 69144e3b MR |
33 | clocks { |
| 34 | #address-cells = <1>; | |
| 35 | #size-cells = <1>; | |
| 36 | ranges; | |
| 37 | ||
| 38 | /* | |
| 39 | * This is a dummy clock, to be used as placeholder on | |
| 40 | * other mux clocks when a specific parent clock is not | |
| 41 | * yet implemented. It should be dropped when the driver | |
| 42 | * is complete. | |
| 43 | */ | |
| 44 | dummy: dummy { | |
| 45 | #clock-cells = <0>; | |
| 46 | compatible = "fixed-clock"; | |
| 47 | clock-frequency = <0>; | |
| 48 | }; | |
| 49 | ||
| 69144e3b MR |
50 | osc24M: osc24M@01c20050 { |
| 51 | #clock-cells = <0>; | |
| 52 | compatible = "allwinner,sun4i-osc-clk"; | |
| 53 | reg = <0x01c20050 0x4>; | |
| 92fd6e06 | 54 | clock-frequency = <24000000>; |
| 69144e3b MR |
55 | }; |
| 56 | ||
| 57 | osc32k: osc32k { | |
| 58 | #clock-cells = <0>; | |
| 59 | compatible = "fixed-clock"; | |
| 60 | clock-frequency = <32768>; | |
| 61 | }; | |
| 62 | ||
| 63 | pll1: pll1@01c20000 { | |
| 64 | #clock-cells = <0>; | |
| 65 | compatible = "allwinner,sun4i-pll1-clk"; | |
| 66 | reg = <0x01c20000 0x4>; | |
| 67 | clocks = <&osc24M>; | |
| 68 | }; | |
| 69 | ||
| 70 | /* dummy is 200M */ | |
| 71 | cpu: cpu@01c20054 { | |
| 72 | #clock-cells = <0>; | |
| 73 | compatible = "allwinner,sun4i-cpu-clk"; | |
| 74 | reg = <0x01c20054 0x4>; | |
| 75 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; | |
| 76 | }; | |
| 77 | ||
| 78 | axi: axi@01c20054 { | |
| 79 | #clock-cells = <0>; | |
| 80 | compatible = "allwinner,sun4i-axi-clk"; | |
| 81 | reg = <0x01c20054 0x4>; | |
| 82 | clocks = <&cpu>; | |
| 83 | }; | |
| 84 | ||
| 85 | axi_gates: axi_gates@01c2005c { | |
| 86 | #clock-cells = <1>; | |
| 87 | compatible = "allwinner,sun4i-axi-gates-clk"; | |
| 88 | reg = <0x01c2005c 0x4>; | |
| 89 | clocks = <&axi>; | |
| 90 | clock-output-names = "axi_dram"; | |
| 91 | }; | |
| 92 | ||
| 93 | ahb: ahb@01c20054 { | |
| 94 | #clock-cells = <0>; | |
| 95 | compatible = "allwinner,sun4i-ahb-clk"; | |
| 96 | reg = <0x01c20054 0x4>; | |
| 97 | clocks = <&axi>; | |
| 98 | }; | |
| 99 | ||
| 100 | ahb_gates: ahb_gates@01c20060 { | |
| 101 | #clock-cells = <1>; | |
| 70be4ee6 | 102 | compatible = "allwinner,sun5i-a13-ahb-gates-clk"; |
| 69144e3b MR |
103 | reg = <0x01c20060 0x8>; |
| 104 | clocks = <&ahb>; | |
| 70be4ee6 MR |
105 | clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci", |
| 106 | "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0", | |
| 107 | "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram", | |
| 108 | "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_stimer", | |
| 109 | "ahb_ve", "ahb_lcd", "ahb_csi", "ahb_de_be", | |
| 110 | "ahb_de_fe", "ahb_iep", "ahb_mali400"; | |
| 69144e3b MR |
111 | }; |
| 112 | ||
| 113 | apb0: apb0@01c20054 { | |
| 114 | #clock-cells = <0>; | |
| 115 | compatible = "allwinner,sun4i-apb0-clk"; | |
| 116 | reg = <0x01c20054 0x4>; | |
| 117 | clocks = <&ahb>; | |
| 118 | }; | |
| 119 | ||
| 120 | apb0_gates: apb0_gates@01c20068 { | |
| 121 | #clock-cells = <1>; | |
| 70be4ee6 | 122 | compatible = "allwinner,sun5i-a13-apb0-gates-clk"; |
| 69144e3b MR |
123 | reg = <0x01c20068 0x4>; |
| 124 | clocks = <&apb0>; | |
| 70be4ee6 | 125 | clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir"; |
| 69144e3b MR |
126 | }; |
| 127 | ||
| 70be4ee6 | 128 | /* dummy is pll6 */ |
| 69144e3b MR |
129 | apb1_mux: apb1_mux@01c20058 { |
| 130 | #clock-cells = <0>; | |
| 131 | compatible = "allwinner,sun4i-apb1-mux-clk"; | |
| 132 | reg = <0x01c20058 0x4>; | |
| 133 | clocks = <&osc24M>, <&dummy>, <&osc32k>; | |
| 134 | }; | |
| 135 | ||
| 136 | apb1: apb1@01c20058 { | |
| 137 | #clock-cells = <0>; | |
| 138 | compatible = "allwinner,sun4i-apb1-clk"; | |
| 139 | reg = <0x01c20058 0x4>; | |
| 140 | clocks = <&apb1_mux>; | |
| 141 | }; | |
| 142 | ||
| 143 | apb1_gates: apb1_gates@01c2006c { | |
| 144 | #clock-cells = <1>; | |
| 70be4ee6 | 145 | compatible = "allwinner,sun5i-a13-apb1-gates-clk"; |
| 69144e3b MR |
146 | reg = <0x01c2006c 0x4>; |
| 147 | clocks = <&apb1>; | |
| 148 | clock-output-names = "apb1_i2c0", "apb1_i2c1", | |
| 70be4ee6 | 149 | "apb1_i2c2", "apb1_uart1", "apb1_uart3"; |
| 69144e3b MR |
150 | }; |
| 151 | }; | |
| 152 | ||
| 153 | soc@01c20000 { | |
| 154 | compatible = "simple-bus"; | |
| 155 | #address-cells = <1>; | |
| 156 | #size-cells = <1>; | |
| 157 | reg = <0x01c20000 0x300000>; | |
| 158 | ranges; | |
| 159 | ||
| 160 | intc: interrupt-controller@01c20400 { | |
| 6def126d | 161 | compatible = "allwinner,sun4i-ic"; |
| 69144e3b MR |
162 | reg = <0x01c20400 0x400>; |
| 163 | interrupt-controller; | |
| 164 | #interrupt-cells = <1>; | |
| 165 | }; | |
| 166 | ||
| e10911e1 | 167 | pio: pinctrl@01c20800 { |
| 9e2dcb2f MR |
168 | compatible = "allwinner,sun5i-a13-pinctrl"; |
| 169 | reg = <0x01c20800 0x400>; | |
| 39138bc6 | 170 | interrupts = <28>; |
| 36386d6e | 171 | clocks = <&apb0_gates 5>; |
| e10911e1 | 172 | gpio-controller; |
| 39138bc6 | 173 | interrupt-controller; |
| 9e2dcb2f MR |
174 | #address-cells = <1>; |
| 175 | #size-cells = <0>; | |
| e10911e1 | 176 | #gpio-cells = <3>; |
| 4348cc64 MR |
177 | |
| 178 | uart1_pins_a: uart1@0 { | |
| 179 | allwinner,pins = "PE10", "PE11"; | |
| 180 | allwinner,function = "uart1"; | |
| 181 | allwinner,drive = <0>; | |
| 182 | allwinner,pull = <0>; | |
| 183 | }; | |
| 184 | ||
| 185 | uart1_pins_b: uart1@1 { | |
| 186 | allwinner,pins = "PG3", "PG4"; | |
| 187 | allwinner,function = "uart1"; | |
| 188 | allwinner,drive = <0>; | |
| 189 | allwinner,pull = <0>; | |
| 190 | }; | |
| b4d7c230 MR |
191 | |
| 192 | i2c0_pins_a: i2c0@0 { | |
| 193 | allwinner,pins = "PB0", "PB1"; | |
| 194 | allwinner,function = "i2c0"; | |
| 195 | allwinner,drive = <0>; | |
| 196 | allwinner,pull = <0>; | |
| 197 | }; | |
| 198 | ||
| 199 | i2c1_pins_a: i2c1@0 { | |
| 200 | allwinner,pins = "PB15", "PB16"; | |
| 201 | allwinner,function = "i2c1"; | |
| 202 | allwinner,drive = <0>; | |
| 203 | allwinner,pull = <0>; | |
| 204 | }; | |
| 205 | ||
| 206 | i2c2_pins_a: i2c2@0 { | |
| 207 | allwinner,pins = "PB17", "PB18"; | |
| 208 | allwinner,function = "i2c2"; | |
| 209 | allwinner,drive = <0>; | |
| 210 | allwinner,pull = <0>; | |
| 211 | }; | |
| 9e2dcb2f | 212 | }; |
| 69144e3b MR |
213 | |
| 214 | timer@01c20c00 { | |
| b6e1a53b | 215 | compatible = "allwinner,sun4i-timer"; |
| 69144e3b MR |
216 | reg = <0x01c20c00 0x90>; |
| 217 | interrupts = <22>; | |
| 218 | clocks = <&osc24M>; | |
| 219 | }; | |
| 220 | ||
| 221 | wdt: watchdog@01c20c90 { | |
| 0b19b7c2 | 222 | compatible = "allwinner,sun4i-wdt"; |
| 69144e3b MR |
223 | reg = <0x01c20c90 0x10>; |
| 224 | }; | |
| 225 | ||
| 226 | uart1: serial@01c28400 { | |
| 227 | compatible = "snps,dw-apb-uart"; | |
| 228 | reg = <0x01c28400 0x400>; | |
| 229 | interrupts = <2>; | |
| 230 | reg-shift = <2>; | |
| 231 | reg-io-width = <4>; | |
| 232 | clocks = <&apb1_gates 17>; | |
| 233 | status = "disabled"; | |
| 234 | }; | |
| 235 | ||
| 236 | uart3: serial@01c28c00 { | |
| 237 | compatible = "snps,dw-apb-uart"; | |
| 238 | reg = <0x01c28c00 0x400>; | |
| 239 | interrupts = <4>; | |
| 240 | reg-shift = <2>; | |
| 241 | reg-io-width = <4>; | |
| 242 | clocks = <&apb1_gates 19>; | |
| 243 | status = "disabled"; | |
| 244 | }; | |
| f1741fda MR |
245 | |
| 246 | i2c0: i2c@01c2ac00 { | |
| 247 | compatible = "allwinner,sun4i-i2c"; | |
| 248 | reg = <0x01c2ac00 0x400>; | |
| 249 | interrupts = <7>; | |
| 250 | clocks = <&apb1_gates 0>; | |
| 251 | clock-frequency = <100000>; | |
| 252 | status = "disabled"; | |
| 253 | }; | |
| 254 | ||
| 255 | i2c1: i2c@01c2b000 { | |
| 256 | compatible = "allwinner,sun4i-i2c"; | |
| 257 | reg = <0x01c2b000 0x400>; | |
| 258 | interrupts = <8>; | |
| 259 | clocks = <&apb1_gates 1>; | |
| 260 | clock-frequency = <100000>; | |
| 261 | status = "disabled"; | |
| 262 | }; | |
| 263 | ||
| 264 | i2c2: i2c@01c2b400 { | |
| 265 | compatible = "allwinner,sun4i-i2c"; | |
| 266 | reg = <0x01c2b400 0x400>; | |
| 267 | interrupts = <9>; | |
| 268 | clocks = <&apb1_gates 2>; | |
| 269 | clock-frequency = <100000>; | |
| 270 | status = "disabled"; | |
| 271 | }; | |
| 9e2dcb2f | 272 | }; |
| d4da2ebb | 273 | }; |