[deliverable/linux.git] / arch / arm / boot / dts / sun5i-a13.dtsi

/*
 * Copyright 2012 Maxime Ripard
 *
 * Maxime Ripard <maxime.ripard@free-electrons.com>
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include "skeleton.dtsi"

#include <dt-bindings/thermal/thermal.h>

#include <dt-bindings/dma/sun4i-a10.h>
#include <dt-bindings/pinctrl/sun4i-a10.h>

/ {
	interrupt-parent = <&intc>;

	chosen {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		framebuffer@0 {
			compatible = "allwinner,simple-framebuffer",
				     "simple-framebuffer";
			allwinner,pipeline = "de_be0-lcd0";
			clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
			status = "disabled";
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a8";
			reg = <0x0>;
			clocks = <&cpu>;
			clock-latency = <244144>; /* 8 32k periods */
			operating-points = <
				/* kHz    uV */
				1008000 1400000
				912000  1350000
				864000  1300000
				624000  1200000
				576000  1200000
				432000  1200000
				>;
			#cooling-cells = <2>;
			cooling-min-level = <0>;
			cooling-max-level = <5>;
		};
	};

	thermal-zones {
		cpu_thermal {
			/* milliseconds */
			polling-delay-passive = <250>;
			polling-delay = <1000>;
			thermal-sensors = <&rtp>;

			cooling-maps {
				map0 {
					trip = <&cpu_alert0>;
					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};

			trips {
				cpu_alert0: cpu_alert0 {
					/* milliCelsius */
					temperature = <850000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu_crit: cpu_crit {
					/* milliCelsius */
					temperature = <100000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};
	};

	memory {
		reg = <0x40000000 0x20000000>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		/*
		 * This is a dummy clock, to be used as placeholder on
		 * other mux clocks when a specific parent clock is not
		 * yet implemented. It should be dropped when the driver
		 * is complete.
		 */
		dummy: dummy {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <0>;
		};

		osc24M: clk@01c20050 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-osc-clk";
			reg = <0x01c20050 0x4>;
			clock-frequency = <24000000>;
			clock-output-names = "osc24M";
		};

		osc32k: clk@0 {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32768>;
			clock-output-names = "osc32k";
		};

		pll1: clk@01c20000 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-pll1-clk";
			reg = <0x01c20000 0x4>;
			clocks = <&osc24M>;
			clock-output-names = "pll1";
		};

		pll4: clk@01c20018 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-pll1-clk";
			reg = <0x01c20018 0x4>;
			clocks = <&osc24M>;
			clock-output-names = "pll4";
		};

		pll5: clk@01c20020 {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-pll5-clk";
			reg = <0x01c20020 0x4>;
			clocks = <&osc24M>;
			clock-output-names = "pll5_ddr", "pll5_other";
		};

		pll6: clk@01c20028 {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-pll6-clk";
			reg = <0x01c20028 0x4>;
			clocks = <&osc24M>;
			clock-output-names = "pll6_sata", "pll6_other", "pll6";
		};

		/* dummy is 200M */
		cpu: cpu@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-cpu-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
			clock-output-names = "cpu";
		};

		axi: axi@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-axi-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&cpu>;
			clock-output-names = "axi";
		};

		axi_gates: clk@01c2005c {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-axi-gates-clk";
			reg = <0x01c2005c 0x4>;
			clocks = <&axi>;
			clock-output-names = "axi_dram";
		};

		ahb: ahb@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-ahb-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&axi>;
			clock-output-names = "ahb";
		};

		ahb_gates: clk@01c20060 {
			#clock-cells = <1>;
			compatible = "allwinner,sun5i-a13-ahb-gates-clk";
			reg = <0x01c20060 0x8>;
			clocks = <&ahb>;
			clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
				"ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
				"ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
				"ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_stimer",
				"ahb_ve", "ahb_lcd", "ahb_csi", "ahb_de_be",
				"ahb_de_fe", "ahb_iep", "ahb_mali400";
		};

		apb0: apb0@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-apb0-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&ahb>;
			clock-output-names = "apb0";
		};

		apb0_gates: clk@01c20068 {
			#clock-cells = <1>;
			compatible = "allwinner,sun5i-a13-apb0-gates-clk";
			reg = <0x01c20068 0x4>;
			clocks = <&apb0>;
			clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
		};

		apb1: clk@01c20058 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-apb1-clk";
			reg = <0x01c20058 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
			clock-output-names = "apb1";
		};

		apb1_gates: clk@01c2006c {
			#clock-cells = <1>;
			compatible = "allwinner,sun5i-a13-apb1-gates-clk";
			reg = <0x01c2006c 0x4>;
			clocks = <&apb1>;
			clock-output-names = "apb1_i2c0", "apb1_i2c1",
				"apb1_i2c2", "apb1_uart1", "apb1_uart3";
		};

		nand_clk: clk@01c20080 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c20080 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "nand";
		};

		ms_clk: clk@01c20084 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c20084 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "ms";
		};

		mmc0_clk: clk@01c20088 {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-mmc-clk";
			reg = <0x01c20088 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "mmc0",
					     "mmc0_output",
					     "mmc0_sample";
		};

		mmc1_clk: clk@01c2008c {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-mmc-clk";
			reg = <0x01c2008c 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "mmc1",
					     "mmc1_output",
					     "mmc1_sample";
		};

		mmc2_clk: clk@01c20090 {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-mmc-clk";
			reg = <0x01c20090 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "mmc2",
					     "mmc2_output",
					     "mmc2_sample";
		};

		ts_clk: clk@01c20098 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c20098 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "ts";
		};

		ss_clk: clk@01c2009c {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c2009c 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "ss";
		};

		spi0_clk: clk@01c200a0 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c200a0 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "spi0";
		};

		spi1_clk: clk@01c200a4 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c200a4 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "spi1";
		};

		spi2_clk: clk@01c200a8 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c200a8 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "spi2";
		};

		ir0_clk: clk@01c200b0 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c200b0 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "ir0";
		};

		usb_clk: clk@01c200cc {
			#clock-cells = <1>;
		        #reset-cells = <1>;
			compatible = "allwinner,sun5i-a13-usb-clk";
			reg = <0x01c200cc 0x4>;
			clocks = <&pll6 1>;
			clock-output-names = "usb_ohci0", "usb_phy";
		};

		mbus_clk: clk@01c2015c {
			#clock-cells = <0>;
			compatible = "allwinner,sun5i-a13-mbus-clk";
			reg = <0x01c2015c 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "mbus";
		};
	};

	soc@01c00000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		dma: dma-controller@01c02000 {
			compatible = "allwinner,sun4i-a10-dma";
			reg = <0x01c02000 0x1000>;
			interrupts = <27>;
			clocks = <&ahb_gates 6>;
			#dma-cells = <2>;
		};

		spi0: spi@01c05000 {
			compatible = "allwinner,sun4i-a10-spi";
			reg = <0x01c05000 0x1000>;
			interrupts = <10>;
			clocks = <&ahb_gates 20>, <&spi0_clk>;
			clock-names = "ahb", "mod";
			dmas = <&dma SUN4I_DMA_DEDICATED 27>,
			       <&dma SUN4I_DMA_DEDICATED 26>;
			dma-names = "rx", "tx";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		spi1: spi@01c06000 {
			compatible = "allwinner,sun4i-a10-spi";
			reg = <0x01c06000 0x1000>;
			interrupts = <11>;
			clocks = <&ahb_gates 21>, <&spi1_clk>;
			clock-names = "ahb", "mod";
			dmas = <&dma SUN4I_DMA_DEDICATED 9>,
			       <&dma SUN4I_DMA_DEDICATED 8>;
			dma-names = "rx", "tx";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		mmc0: mmc@01c0f000 {
			compatible = "allwinner,sun5i-a13-mmc";
			reg = <0x01c0f000 0x1000>;
			clocks = <&ahb_gates 8>,
				 <&mmc0_clk 0>,
				 <&mmc0_clk 1>,
				 <&mmc0_clk 2>;
			clock-names = "ahb",
				      "mmc",
				      "output",
				      "sample";
			interrupts = <32>;
			status = "disabled";
		};

		mmc2: mmc@01c11000 {
			compatible = "allwinner,sun5i-a13-mmc";
			reg = <0x01c11000 0x1000>;
			clocks = <&ahb_gates 10>,
				 <&mmc2_clk 0>,
				 <&mmc2_clk 1>,
				 <&mmc2_clk 2>;
			clock-names = "ahb",
				      "mmc",
				      "output",
				      "sample";
			interrupts = <34>;
			status = "disabled";
		};

		usbphy: phy@01c13400 {
			#phy-cells = <1>;
			compatible = "allwinner,sun5i-a13-usb-phy";
			reg = <0x01c13400 0x10 0x01c14800 0x4>;
			reg-names = "phy_ctrl", "pmu1";
			clocks = <&usb_clk 8>;
			clock-names = "usb_phy";
			resets = <&usb_clk 0>, <&usb_clk 1>;
			reset-names = "usb0_reset", "usb1_reset";
			status = "disabled";
		};

		ehci0: usb@01c14000 {
			compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
			reg = <0x01c14000 0x100>;
			interrupts = <39>;
			clocks = <&ahb_gates 1>;
			phys = <&usbphy 1>;
			phy-names = "usb";
			status = "disabled";
		};

		ohci0: usb@01c14400 {
			compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
			reg = <0x01c14400 0x100>;
			interrupts = <40>;
			clocks = <&usb_clk 6>, <&ahb_gates 2>;
			phys = <&usbphy 1>;
			phy-names = "usb";
			status = "disabled";
		};

		spi2: spi@01c17000 {
			compatible = "allwinner,sun4i-a10-spi";
			reg = <0x01c17000 0x1000>;
			interrupts = <12>;
			clocks = <&ahb_gates 22>, <&spi2_clk>;
			clock-names = "ahb", "mod";
			dmas = <&dma SUN4I_DMA_DEDICATED 29>,
			       <&dma SUN4I_DMA_DEDICATED 28>;
			dma-names = "rx", "tx";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		intc: interrupt-controller@01c20400 {
			compatible = "allwinner,sun4i-a10-ic";
			reg = <0x01c20400 0x400>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		pio: pinctrl@01c20800 {
			compatible = "allwinner,sun5i-a13-pinctrl";
			reg = <0x01c20800 0x400>;
			interrupts = <28>;
			clocks = <&apb0_gates 5>;
			gpio-controller;
			interrupt-controller;
			#interrupt-cells = <2>;
			#size-cells = <0>;
			#gpio-cells = <3>;

			uart1_pins_a: uart1@0 {
				allwinner,pins = "PE10", "PE11";
				allwinner,function = "uart1";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			uart1_pins_b: uart1@1 {
				allwinner,pins = "PG3", "PG4";
				allwinner,function = "uart1";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			i2c0_pins_a: i2c0@0 {
				allwinner,pins = "PB0", "PB1";
				allwinner,function = "i2c0";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			i2c1_pins_a: i2c1@0 {
				allwinner,pins = "PB15", "PB16";
				allwinner,function = "i2c1";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			i2c2_pins_a: i2c2@0 {
				allwinner,pins = "PB17", "PB18";
				allwinner,function = "i2c2";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			mmc0_pins_a: mmc0@0 {
				allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
				allwinner,function = "mmc0";
				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};
		};

		timer@01c20c00 {
			compatible = "allwinner,sun4i-a10-timer";
			reg = <0x01c20c00 0x90>;
			interrupts = <22>;
			clocks = <&osc24M>;
		};

		wdt: watchdog@01c20c90 {
			compatible = "allwinner,sun4i-a10-wdt";
			reg = <0x01c20c90 0x10>;
		};

		lradc: lradc@01c22800 {
			compatible = "allwinner,sun4i-a10-lradc-keys";
			reg = <0x01c22800 0x100>;
			interrupts = <31>;
			status = "disabled";
		};

		sid: eeprom@01c23800 {
			compatible = "allwinner,sun4i-a10-sid";
			reg = <0x01c23800 0x10>;
		};

		rtp: rtp@01c25000 {
			compatible = "allwinner,sun4i-a10-ts";
			reg = <0x01c25000 0x100>;
			interrupts = <29>;
			#thermal-sensor-cells = <0>;
		};

		uart1: serial@01c28400 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28400 0x400>;
			interrupts = <2>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 17>;
			status = "disabled";
		};

		uart3: serial@01c28c00 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28c00 0x400>;
			interrupts = <4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 19>;
			status = "disabled";
		};

		i2c0: i2c@01c2ac00 {
			compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";
			reg = <0x01c2ac00 0x400>;
			interrupts = <7>;
			clocks = <&apb1_gates 0>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c1: i2c@01c2b000 {
			compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";
			reg = <0x01c2b000 0x400>;
			interrupts = <8>;
			clocks = <&apb1_gates 1>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c2: i2c@01c2b400 {
			compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";
			reg = <0x01c2b400 0x400>;
			interrupts = <9>;
			clocks = <&apb1_gates 2>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		timer@01c60000 {
			compatible = "allwinner,sun5i-a13-hstimer";
			reg = <0x01c60000 0x1000>;
			interrupts = <82>, <83>;
			clocks = <&ahb_gates 28>;
		};
	};
};
Commit	Line	Data
d4da2ebb MR	1	/*
	2	* Copyright 2012 Maxime Ripard
	3	*
	4	* Maxime Ripard <maxime.ripard@free-electrons.com>
	5	*
	6	* The code contained herein is licensed under the GNU General Public
	7	* License. You may obtain a copy of the GNU General Public License
	8	* Version 2 or later at the following locations:
	9	*
	10	* http://www.opensource.org/licenses/gpl-license.html
	11	* http://www.gnu.org/copyleft/gpl.html
	12	*/
	13
71455701	14	#include "skeleton.dtsi"
d4da2ebb	15
32a5d2d1 CYT	16	#include <dt-bindings/thermal/thermal.h>
32a5d2d1 CYT	17
1f9f6a78	18	#include <dt-bindings/dma/sun4i-a10.h>
092a0c3b	19	#include <dt-bindings/pinctrl/sun4i-a10.h>
d4da2ebb MR	20
d4da2ebb MR	21	/ {
69144e3b MR	22	interrupt-parent = <&intc>;
69144e3b MR	23
fd18c7ea HG	24	chosen {
	25	#address-cells = <1>;
	26	#size-cells = <1>;
	27	ranges;
	28
	29	framebuffer@0 {
	30	compatible = "allwinner,simple-framebuffer",
	31	"simple-framebuffer";
	32	allwinner,pipeline = "de_be0-lcd0";
	33	clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
	34	status = "disabled";
	35	};
	36	};
	37
69144e3b	38	cpus {
8b2efa89 AB	39	#address-cells = <1>;
8b2efa89 AB	40	#size-cells = <0>;
882facf7 CYT	41
882facf7 CYT	42	cpu0: cpu@0 {
14c44aa5	43	device_type = "cpu";
69144e3b	44	compatible = "arm,cortex-a8";
14c44aa5	45	reg = <0x0>;
882facf7 CYT	46	clocks = <&cpu>;
	47	clock-latency = <244144>; /* 8 32k periods */
	48	operating-points = <
	49	/* kHz uV */
882facf7 CYT	50	1008000 1400000
	51	912000 1350000
	52	864000 1300000
	53	624000 1200000
	54	576000 1200000
	55	432000 1200000
	56	>;
	57	#cooling-cells = <2>;
	58	cooling-min-level = <0>;
370a9b5f	59	cooling-max-level = <5>;
69144e3b MR	60	};
	61	};
	62
32a5d2d1 CYT	63	thermal-zones {
	64	cpu_thermal {
	65	/* milliseconds */
	66	polling-delay-passive = <250>;
	67	polling-delay = <1000>;
	68	thermal-sensors = <&rtp>;
	69
	70	cooling-maps {
	71	map0 {
	72	trip = <&cpu_alert0>;
	73	cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	74	};
	75	};
	76
	77	trips {
	78	cpu_alert0: cpu_alert0 {
	79	/* milliCelsius */
	80	temperature = <850000>;
	81	hysteresis = <2000>;
	82	type = "passive";
	83	};
	84
	85	cpu_crit: cpu_crit {
	86	/* milliCelsius */
	87	temperature = <100000>;
	88	hysteresis = <2000>;
	89	type = "critical";
	90	};
	91	};
69144e3b MR	92	};
	93	};
	94
d4da2ebb MR	95	memory {
	96	reg = <0x40000000 0x20000000>;
	97	};
9e2dcb2f	98
69144e3b MR	99	clocks {
	100	#address-cells = <1>;
	101	#size-cells = <1>;
	102	ranges;
	103
	104	/*
	105	* This is a dummy clock, to be used as placeholder on
	106	* other mux clocks when a specific parent clock is not
	107	* yet implemented. It should be dropped when the driver
	108	* is complete.
	109	*/
	110	dummy: dummy {
	111	#clock-cells = <0>;
	112	compatible = "fixed-clock";
	113	clock-frequency = <0>;
	114	};
	115
3dce8324	116	osc24M: clk@01c20050 {
69144e3b	117	#clock-cells = <0>;
bf6534a1	118	compatible = "allwinner,sun4i-a10-osc-clk";
69144e3b	119	reg = <0x01c20050 0x4>;
92fd6e06	120	clock-frequency = <24000000>;
3dce8324	121	clock-output-names = "osc24M";
69144e3b MR	122	};
69144e3b MR	123
3dce8324	124	osc32k: clk@0 {
69144e3b MR	125	#clock-cells = <0>;
	126	compatible = "fixed-clock";
	127	clock-frequency = <32768>;
3dce8324	128	clock-output-names = "osc32k";
69144e3b MR	129	};
69144e3b MR	130
3dce8324	131	pll1: clk@01c20000 {
69144e3b	132	#clock-cells = <0>;
bf6534a1	133	compatible = "allwinner,sun4i-a10-pll1-clk";
69144e3b MR	134	reg = <0x01c20000 0x4>;
69144e3b MR	135	clocks = <&osc24M>;
3dce8324	136	clock-output-names = "pll1";
69144e3b MR	137	};
69144e3b MR	138
3dce8324	139	pll4: clk@01c20018 {
ec5589f7	140	#clock-cells = <0>;
bf6534a1	141	compatible = "allwinner,sun4i-a10-pll1-clk";
ec5589f7 EL	142	reg = <0x01c20018 0x4>;
ec5589f7 EL	143	clocks = <&osc24M>;
3dce8324	144	clock-output-names = "pll4";
ec5589f7 EL	145	};
ec5589f7 EL	146
3dce8324	147	pll5: clk@01c20020 {
c3e5e66b	148	#clock-cells = <1>;
bf6534a1	149	compatible = "allwinner,sun4i-a10-pll5-clk";
c3e5e66b EL	150	reg = <0x01c20020 0x4>;
	151	clocks = <&osc24M>;
	152	clock-output-names = "pll5_ddr", "pll5_other";
	153	};
	154
3dce8324	155	pll6: clk@01c20028 {
c3e5e66b	156	#clock-cells = <1>;
bf6534a1	157	compatible = "allwinner,sun4i-a10-pll6-clk";
c3e5e66b EL	158	reg = <0x01c20028 0x4>;
	159	clocks = <&osc24M>;
	160	clock-output-names = "pll6_sata", "pll6_other", "pll6";
	161	};
	162
69144e3b MR	163	/* dummy is 200M */
	164	cpu: cpu@01c20054 {
	165	#clock-cells = <0>;
bf6534a1	166	compatible = "allwinner,sun4i-a10-cpu-clk";
69144e3b MR	167	reg = <0x01c20054 0x4>;
69144e3b MR	168	clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
3dce8324	169	clock-output-names = "cpu";
69144e3b MR	170	};
	171
	172	axi: axi@01c20054 {
	173	#clock-cells = <0>;
bf6534a1	174	compatible = "allwinner,sun4i-a10-axi-clk";
69144e3b MR	175	reg = <0x01c20054 0x4>;
69144e3b MR	176	clocks = <&cpu>;
3dce8324	177	clock-output-names = "axi";
69144e3b MR	178	};
69144e3b MR	179
3dce8324	180	axi_gates: clk@01c2005c {
69144e3b	181	#clock-cells = <1>;
bf6534a1	182	compatible = "allwinner,sun4i-a10-axi-gates-clk";
69144e3b MR	183	reg = <0x01c2005c 0x4>;
	184	clocks = <&axi>;
	185	clock-output-names = "axi_dram";
	186	};
	187
	188	ahb: ahb@01c20054 {
	189	#clock-cells = <0>;
bf6534a1	190	compatible = "allwinner,sun4i-a10-ahb-clk";
69144e3b MR	191	reg = <0x01c20054 0x4>;
69144e3b MR	192	clocks = <&axi>;
3dce8324	193	clock-output-names = "ahb";
69144e3b MR	194	};
69144e3b MR	195
3dce8324	196	ahb_gates: clk@01c20060 {
69144e3b	197	#clock-cells = <1>;
70be4ee6	198	compatible = "allwinner,sun5i-a13-ahb-gates-clk";
69144e3b MR	199	reg = <0x01c20060 0x8>;
69144e3b MR	200	clocks = <&ahb>;
70be4ee6 MR	201	clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
	202	"ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
	203	"ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
	204	"ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_stimer",
	205	"ahb_ve", "ahb_lcd", "ahb_csi", "ahb_de_be",
	206	"ahb_de_fe", "ahb_iep", "ahb_mali400";
69144e3b MR	207	};
	208
	209	apb0: apb0@01c20054 {
	210	#clock-cells = <0>;
bf6534a1	211	compatible = "allwinner,sun4i-a10-apb0-clk";
69144e3b MR	212	reg = <0x01c20054 0x4>;
69144e3b MR	213	clocks = <&ahb>;
3dce8324	214	clock-output-names = "apb0";
69144e3b MR	215	};
69144e3b MR	216
3dce8324	217	apb0_gates: clk@01c20068 {
69144e3b	218	#clock-cells = <1>;
70be4ee6	219	compatible = "allwinner,sun5i-a13-apb0-gates-clk";
69144e3b MR	220	reg = <0x01c20068 0x4>;
69144e3b MR	221	clocks = <&apb0>;
70be4ee6	222	clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
69144e3b MR	223	};
69144e3b MR	224
acbcc0f0	225	apb1: clk@01c20058 {
69144e3b	226	#clock-cells = <0>;
bf6534a1	227	compatible = "allwinner,sun4i-a10-apb1-clk";
69144e3b	228	reg = <0x01c20058 0x4>;
acbcc0f0	229	clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
3dce8324	230	clock-output-names = "apb1";
69144e3b MR	231	};
69144e3b MR	232
3dce8324	233	apb1_gates: clk@01c2006c {
69144e3b	234	#clock-cells = <1>;
70be4ee6	235	compatible = "allwinner,sun5i-a13-apb1-gates-clk";
69144e3b MR	236	reg = <0x01c2006c 0x4>;
	237	clocks = <&apb1>;
	238	clock-output-names = "apb1_i2c0", "apb1_i2c1",
70be4ee6	239	"apb1_i2c2", "apb1_uart1", "apb1_uart3";
69144e3b	240	};
8dc36bff EL	241
	242	nand_clk: clk@01c20080 {
	243	#clock-cells = <0>;
bf6534a1	244	compatible = "allwinner,sun4i-a10-mod0-clk";
8dc36bff EL	245	reg = <0x01c20080 0x4>;
	246	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
	247	clock-output-names = "nand";
	248	};
	249
	250	ms_clk: clk@01c20084 {
	251	#clock-cells = <0>;
bf6534a1	252	compatible = "allwinner,sun4i-a10-mod0-clk";
8dc36bff EL	253	reg = <0x01c20084 0x4>;
	254	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
	255	clock-output-names = "ms";
	256	};
	257
	258	mmc0_clk: clk@01c20088 {
d8c3a392 MR	259	#clock-cells = <1>;
d8c3a392 MR	260	compatible = "allwinner,sun4i-a10-mmc-clk";
8dc36bff EL	261	reg = <0x01c20088 0x4>;
8dc36bff EL	262	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
d8c3a392 MR	263	clock-output-names = "mmc0",
	264	"mmc0_output",
	265	"mmc0_sample";
8dc36bff EL	266	};
	267
	268	mmc1_clk: clk@01c2008c {
d8c3a392 MR	269	#clock-cells = <1>;
d8c3a392 MR	270	compatible = "allwinner,sun4i-a10-mmc-clk";
8dc36bff EL	271	reg = <0x01c2008c 0x4>;
8dc36bff EL	272	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
d8c3a392 MR	273	clock-output-names = "mmc1",
	274	"mmc1_output",
	275	"mmc1_sample";
8dc36bff EL	276	};
	277
	278	mmc2_clk: clk@01c20090 {
d8c3a392 MR	279	#clock-cells = <1>;
d8c3a392 MR	280	compatible = "allwinner,sun4i-a10-mmc-clk";
8dc36bff EL	281	reg = <0x01c20090 0x4>;
8dc36bff EL	282	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
d8c3a392 MR	283	clock-output-names = "mmc2",
	284	"mmc2_output",
	285	"mmc2_sample";
8dc36bff EL	286	};
	287
	288	ts_clk: clk@01c20098 {
	289	#clock-cells = <0>;
bf6534a1	290	compatible = "allwinner,sun4i-a10-mod0-clk";
8dc36bff EL	291	reg = <0x01c20098 0x4>;
	292	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
	293	clock-output-names = "ts";
	294	};
	295
	296	ss_clk: clk@01c2009c {
	297	#clock-cells = <0>;
bf6534a1	298	compatible = "allwinner,sun4i-a10-mod0-clk";
8dc36bff EL	299	reg = <0x01c2009c 0x4>;
	300	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
	301	clock-output-names = "ss";
	302	};
	303
	304	spi0_clk: clk@01c200a0 {
	305	#clock-cells = <0>;
bf6534a1	306	compatible = "allwinner,sun4i-a10-mod0-clk";
8dc36bff EL	307	reg = <0x01c200a0 0x4>;
	308	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
	309	clock-output-names = "spi0";
	310	};
	311
	312	spi1_clk: clk@01c200a4 {
	313	#clock-cells = <0>;
bf6534a1	314	compatible = "allwinner,sun4i-a10-mod0-clk";
8dc36bff EL	315	reg = <0x01c200a4 0x4>;
	316	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
	317	clock-output-names = "spi1";
	318	};
	319
	320	spi2_clk: clk@01c200a8 {
	321	#clock-cells = <0>;
bf6534a1	322	compatible = "allwinner,sun4i-a10-mod0-clk";
8dc36bff EL	323	reg = <0x01c200a8 0x4>;
	324	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
	325	clock-output-names = "spi2";
	326	};
	327
	328	ir0_clk: clk@01c200b0 {
	329	#clock-cells = <0>;
bf6534a1	330	compatible = "allwinner,sun4i-a10-mod0-clk";
8dc36bff EL	331	reg = <0x01c200b0 0x4>;
	332	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
	333	clock-output-names = "ir0";
	334	};
118c07ae	335
4c5d72f8 RB	336	usb_clk: clk@01c200cc {
	337	#clock-cells = <1>;
	338	#reset-cells = <1>;
	339	compatible = "allwinner,sun5i-a13-usb-clk";
	340	reg = <0x01c200cc 0x4>;
	341	clocks = <&pll6 1>;
	342	clock-output-names = "usb_ohci0", "usb_phy";
	343	};
	344
118c07ae EL	345	mbus_clk: clk@01c2015c {
118c07ae EL	346	#clock-cells = <0>;
7868c5eb	347	compatible = "allwinner,sun5i-a13-mbus-clk";
118c07ae EL	348	reg = <0x01c2015c 0x4>;
	349	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
	350	clock-output-names = "mbus";
	351	};
69144e3b MR	352	};
69144e3b MR	353
278fe8b8	354	soc@01c00000 {
69144e3b MR	355	compatible = "simple-bus";
	356	#address-cells = <1>;
	357	#size-cells = <1>;
69144e3b MR	358	ranges;
69144e3b MR	359
6a5775e4 EL	360	dma: dma-controller@01c02000 {
	361	compatible = "allwinner,sun4i-a10-dma";
	362	reg = <0x01c02000 0x1000>;
	363	interrupts = <27>;
	364	clocks = <&ahb_gates 6>;
	365	#dma-cells = <2>;
	366	};
	367
8f8658b7 MR	368	spi0: spi@01c05000 {
	369	compatible = "allwinner,sun4i-a10-spi";
	370	reg = <0x01c05000 0x1000>;
	371	interrupts = <10>;
	372	clocks = <&ahb_gates 20>, <&spi0_clk>;
	373	clock-names = "ahb", "mod";
1f9f6a78 MR	374	dmas = <&dma SUN4I_DMA_DEDICATED 27>,
1f9f6a78 MR	375	<&dma SUN4I_DMA_DEDICATED 26>;
fed4c5c6	376	dma-names = "rx", "tx";
8f8658b7 MR	377	status = "disabled";
	378	#address-cells = <1>;
	379	#size-cells = <0>;
	380	};
	381
	382	spi1: spi@01c06000 {
	383	compatible = "allwinner,sun4i-a10-spi";
	384	reg = <0x01c06000 0x1000>;
	385	interrupts = <11>;
	386	clocks = <&ahb_gates 21>, <&spi1_clk>;
	387	clock-names = "ahb", "mod";
1f9f6a78 MR	388	dmas = <&dma SUN4I_DMA_DEDICATED 9>,
1f9f6a78 MR	389	<&dma SUN4I_DMA_DEDICATED 8>;
fed4c5c6	390	dma-names = "rx", "tx";
8f8658b7 MR	391	status = "disabled";
	392	#address-cells = <1>;
	393	#size-cells = <0>;
	394	};
	395
d3aed1df DL	396	mmc0: mmc@01c0f000 {
	397	compatible = "allwinner,sun5i-a13-mmc";
	398	reg = <0x01c0f000 0x1000>;
d8c3a392 MR	399	clocks = <&ahb_gates 8>,
	400	<&mmc0_clk 0>,
	401	<&mmc0_clk 1>,
	402	<&mmc0_clk 2>;
	403	clock-names = "ahb",
	404	"mmc",
	405	"output",
	406	"sample";
d3aed1df DL	407	interrupts = <32>;
	408	status = "disabled";
	409	};
	410
	411	mmc2: mmc@01c11000 {
	412	compatible = "allwinner,sun5i-a13-mmc";
	413	reg = <0x01c11000 0x1000>;
d8c3a392 MR	414	clocks = <&ahb_gates 10>,
	415	<&mmc2_clk 0>,
	416	<&mmc2_clk 1>,
	417	<&mmc2_clk 2>;
	418	clock-names = "ahb",
	419	"mmc",
	420	"output",
	421	"sample";
d3aed1df DL	422	interrupts = <34>;
	423	status = "disabled";
	424	};
	425
06c7d52f RB	426	usbphy: phy@01c13400 {
	427	#phy-cells = <1>;
	428	compatible = "allwinner,sun5i-a13-usb-phy";
	429	reg = <0x01c13400 0x10 0x01c14800 0x4>;
	430	reg-names = "phy_ctrl", "pmu1";
	431	clocks = <&usb_clk 8>;
	432	clock-names = "usb_phy";
4dba4185 CYT	433	resets = <&usb_clk 0>, <&usb_clk 1>;
4dba4185 CYT	434	reset-names = "usb0_reset", "usb1_reset";
06c7d52f RB	435	status = "disabled";
	436	};
	437
	438	ehci0: usb@01c14000 {
	439	compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
	440	reg = <0x01c14000 0x100>;
	441	interrupts = <39>;
	442	clocks = <&ahb_gates 1>;
	443	phys = <&usbphy 1>;
	444	phy-names = "usb";
	445	status = "disabled";
	446	};
	447
	448	ohci0: usb@01c14400 {
	449	compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
	450	reg = <0x01c14400 0x100>;
	451	interrupts = <40>;
	452	clocks = <&usb_clk 6>, <&ahb_gates 2>;
	453	phys = <&usbphy 1>;
	454	phy-names = "usb";
	455	status = "disabled";
	456	};
	457
8f8658b7 MR	458	spi2: spi@01c17000 {
	459	compatible = "allwinner,sun4i-a10-spi";
	460	reg = <0x01c17000 0x1000>;
	461	interrupts = <12>;
	462	clocks = <&ahb_gates 22>, <&spi2_clk>;
	463	clock-names = "ahb", "mod";
1f9f6a78 MR	464	dmas = <&dma SUN4I_DMA_DEDICATED 29>,
1f9f6a78 MR	465	<&dma SUN4I_DMA_DEDICATED 28>;
fed4c5c6	466	dma-names = "rx", "tx";
8f8658b7 MR	467	status = "disabled";
	468	#address-cells = <1>;
	469	#size-cells = <0>;
	470	};
	471
69144e3b	472	intc: interrupt-controller@01c20400 {
09504a7d	473	compatible = "allwinner,sun4i-a10-ic";
69144e3b MR	474	reg = <0x01c20400 0x400>;
	475	interrupt-controller;
	476	#interrupt-cells = <1>;
	477	};
	478
e10911e1	479	pio: pinctrl@01c20800 {
9e2dcb2f MR	480	compatible = "allwinner,sun5i-a13-pinctrl";
9e2dcb2f MR	481	reg = <0x01c20800 0x400>;
39138bc6	482	interrupts = <28>;
36386d6e	483	clocks = <&apb0_gates 5>;
e10911e1	484	gpio-controller;
39138bc6	485	interrupt-controller;
7d4ff96d	486	#interrupt-cells = <2>;
9e2dcb2f	487	#size-cells = <0>;
e10911e1	488	#gpio-cells = <3>;
4348cc64 MR	489
	490	uart1_pins_a: uart1@0 {
	491	allwinner,pins = "PE10", "PE11";
	492	allwinner,function = "uart1";
092a0c3b MR	493	allwinner,drive = <SUN4I_PINCTRL_10_MA>;
092a0c3b MR	494	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
4348cc64 MR	495	};
	496
	497	uart1_pins_b: uart1@1 {
	498	allwinner,pins = "PG3", "PG4";
	499	allwinner,function = "uart1";
092a0c3b MR	500	allwinner,drive = <SUN4I_PINCTRL_10_MA>;
092a0c3b MR	501	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
4348cc64	502	};
b4d7c230 MR	503
	504	i2c0_pins_a: i2c0@0 {
	505	allwinner,pins = "PB0", "PB1";
	506	allwinner,function = "i2c0";
092a0c3b MR	507	allwinner,drive = <SUN4I_PINCTRL_10_MA>;
092a0c3b MR	508	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
b4d7c230 MR	509	};
	510
	511	i2c1_pins_a: i2c1@0 {
	512	allwinner,pins = "PB15", "PB16";
	513	allwinner,function = "i2c1";
092a0c3b MR	514	allwinner,drive = <SUN4I_PINCTRL_10_MA>;
092a0c3b MR	515	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
b4d7c230 MR	516	};
	517
	518	i2c2_pins_a: i2c2@0 {
	519	allwinner,pins = "PB17", "PB18";
	520	allwinner,function = "i2c2";
092a0c3b MR	521	allwinner,drive = <SUN4I_PINCTRL_10_MA>;
092a0c3b MR	522	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
b4d7c230	523	};
6da50f13 HG	524
	525	mmc0_pins_a: mmc0@0 {
	526	allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
	527	allwinner,function = "mmc0";
092a0c3b MR	528	allwinner,drive = <SUN4I_PINCTRL_30_MA>;
092a0c3b MR	529	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
6da50f13	530	};
9e2dcb2f	531	};
69144e3b MR	532
69144e3b MR	533	timer@01c20c00 {
b4f26440	534	compatible = "allwinner,sun4i-a10-timer";
69144e3b MR	535	reg = <0x01c20c00 0x90>;
	536	interrupts = <22>;
	537	clocks = <&osc24M>;
	538	};
	539
	540	wdt: watchdog@01c20c90 {
ca5d04d9	541	compatible = "allwinner,sun4i-a10-wdt";
69144e3b MR	542	reg = <0x01c20c90 0x10>;
	543	};
	544
ec011af5 HG	545	lradc: lradc@01c22800 {
	546	compatible = "allwinner,sun4i-a10-lradc-keys";
	547	reg = <0x01c22800 0x100>;
	548	interrupts = <31>;
	549	status = "disabled";
	550	};
	551
2bad969f	552	sid: eeprom@01c23800 {
043d56ee	553	compatible = "allwinner,sun4i-a10-sid";
2bad969f OS	554	reg = <0x01c23800 0x10>;
	555	};
	556
f65c93a0	557	rtp: rtp@01c25000 {
40dd8f3b	558	compatible = "allwinner,sun4i-a10-ts";
f65c93a0 HG	559	reg = <0x01c25000 0x100>;
f65c93a0 HG	560	interrupts = <29>;
41e7afb1	561	#thermal-sensor-cells = <0>;
f65c93a0 HG	562	};
f65c93a0 HG	563
69144e3b MR	564	uart1: serial@01c28400 {
	565	compatible = "snps,dw-apb-uart";
	566	reg = <0x01c28400 0x400>;
	567	interrupts = <2>;
	568	reg-shift = <2>;
	569	reg-io-width = <4>;
	570	clocks = <&apb1_gates 17>;
	571	status = "disabled";
	572	};
	573
	574	uart3: serial@01c28c00 {
	575	compatible = "snps,dw-apb-uart";
	576	reg = <0x01c28c00 0x400>;
	577	interrupts = <4>;
	578	reg-shift = <2>;
	579	reg-io-width = <4>;
	580	clocks = <&apb1_gates 19>;
	581	status = "disabled";
	582	};
f1741fda MR	583
f1741fda MR	584	i2c0: i2c@01c2ac00 {
d275545e	585	compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";
f1741fda MR	586	reg = <0x01c2ac00 0x400>;
	587	interrupts = <7>;
	588	clocks = <&apb1_gates 0>;
f1741fda	589	status = "disabled";
a470342e HG	590	#address-cells = <1>;
a470342e HG	591	#size-cells = <0>;
f1741fda MR	592	};
	593
	594	i2c1: i2c@01c2b000 {
d275545e	595	compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";
f1741fda MR	596	reg = <0x01c2b000 0x400>;
	597	interrupts = <8>;
	598	clocks = <&apb1_gates 1>;
f1741fda	599	status = "disabled";
a470342e HG	600	#address-cells = <1>;
a470342e HG	601	#size-cells = <0>;
f1741fda MR	602	};
	603
	604	i2c2: i2c@01c2b400 {
d275545e	605	compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";
f1741fda MR	606	reg = <0x01c2b400 0x400>;
	607	interrupts = <9>;
	608	clocks = <&apb1_gates 2>;
f1741fda	609	status = "disabled";
a470342e HG	610	#address-cells = <1>;
a470342e HG	611	#size-cells = <0>;
f1741fda	612	};
4411902a MR	613
	614	timer@01c60000 {
	615	compatible = "allwinner,sun5i-a13-hstimer";
	616	reg = <0x01c60000 0x1000>;
	617	interrupts = <82>, <83>;
	618	clocks = <&ahb_gates 28>;
	619	};
9e2dcb2f	620	};
d4da2ebb	621	};