Commit | Line | Data |
---|---|---|
d4da2ebb MR |
1 | /* |
2 | * Copyright 2012 Maxime Ripard | |
3 | * | |
4 | * Maxime Ripard <maxime.ripard@free-electrons.com> | |
5 | * | |
6 | * The code contained herein is licensed under the GNU General Public | |
7 | * License. You may obtain a copy of the GNU General Public License | |
8 | * Version 2 or later at the following locations: | |
9 | * | |
10 | * http://www.opensource.org/licenses/gpl-license.html | |
11 | * http://www.gnu.org/copyleft/gpl.html | |
12 | */ | |
13 | ||
69144e3b | 14 | /include/ "skeleton.dtsi" |
d4da2ebb MR |
15 | |
16 | / { | |
69144e3b MR |
17 | interrupt-parent = <&intc>; |
18 | ||
0cc774ef MR |
19 | aliases { |
20 | serial0 = &uart1; | |
21 | serial1 = &uart3; | |
22 | }; | |
23 | ||
69144e3b | 24 | cpus { |
8b2efa89 AB |
25 | #address-cells = <1>; |
26 | #size-cells = <0>; | |
69144e3b | 27 | cpu@0 { |
14c44aa5 | 28 | device_type = "cpu"; |
69144e3b | 29 | compatible = "arm,cortex-a8"; |
14c44aa5 | 30 | reg = <0x0>; |
69144e3b MR |
31 | }; |
32 | }; | |
33 | ||
d4da2ebb MR |
34 | memory { |
35 | reg = <0x40000000 0x20000000>; | |
36 | }; | |
9e2dcb2f | 37 | |
69144e3b MR |
38 | clocks { |
39 | #address-cells = <1>; | |
40 | #size-cells = <1>; | |
41 | ranges; | |
42 | ||
43 | /* | |
44 | * This is a dummy clock, to be used as placeholder on | |
45 | * other mux clocks when a specific parent clock is not | |
46 | * yet implemented. It should be dropped when the driver | |
47 | * is complete. | |
48 | */ | |
49 | dummy: dummy { | |
50 | #clock-cells = <0>; | |
51 | compatible = "fixed-clock"; | |
52 | clock-frequency = <0>; | |
53 | }; | |
54 | ||
3dce8324 | 55 | osc24M: clk@01c20050 { |
69144e3b MR |
56 | #clock-cells = <0>; |
57 | compatible = "allwinner,sun4i-osc-clk"; | |
58 | reg = <0x01c20050 0x4>; | |
92fd6e06 | 59 | clock-frequency = <24000000>; |
3dce8324 | 60 | clock-output-names = "osc24M"; |
69144e3b MR |
61 | }; |
62 | ||
3dce8324 | 63 | osc32k: clk@0 { |
69144e3b MR |
64 | #clock-cells = <0>; |
65 | compatible = "fixed-clock"; | |
66 | clock-frequency = <32768>; | |
3dce8324 | 67 | clock-output-names = "osc32k"; |
69144e3b MR |
68 | }; |
69 | ||
3dce8324 | 70 | pll1: clk@01c20000 { |
69144e3b MR |
71 | #clock-cells = <0>; |
72 | compatible = "allwinner,sun4i-pll1-clk"; | |
73 | reg = <0x01c20000 0x4>; | |
74 | clocks = <&osc24M>; | |
3dce8324 | 75 | clock-output-names = "pll1"; |
69144e3b MR |
76 | }; |
77 | ||
3dce8324 | 78 | pll4: clk@01c20018 { |
ec5589f7 EL |
79 | #clock-cells = <0>; |
80 | compatible = "allwinner,sun4i-pll1-clk"; | |
81 | reg = <0x01c20018 0x4>; | |
82 | clocks = <&osc24M>; | |
3dce8324 | 83 | clock-output-names = "pll4"; |
ec5589f7 EL |
84 | }; |
85 | ||
3dce8324 | 86 | pll5: clk@01c20020 { |
c3e5e66b EL |
87 | #clock-cells = <1>; |
88 | compatible = "allwinner,sun4i-pll5-clk"; | |
89 | reg = <0x01c20020 0x4>; | |
90 | clocks = <&osc24M>; | |
91 | clock-output-names = "pll5_ddr", "pll5_other"; | |
92 | }; | |
93 | ||
3dce8324 | 94 | pll6: clk@01c20028 { |
c3e5e66b EL |
95 | #clock-cells = <1>; |
96 | compatible = "allwinner,sun4i-pll6-clk"; | |
97 | reg = <0x01c20028 0x4>; | |
98 | clocks = <&osc24M>; | |
99 | clock-output-names = "pll6_sata", "pll6_other", "pll6"; | |
100 | }; | |
101 | ||
69144e3b MR |
102 | /* dummy is 200M */ |
103 | cpu: cpu@01c20054 { | |
104 | #clock-cells = <0>; | |
105 | compatible = "allwinner,sun4i-cpu-clk"; | |
106 | reg = <0x01c20054 0x4>; | |
107 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; | |
3dce8324 | 108 | clock-output-names = "cpu"; |
69144e3b MR |
109 | }; |
110 | ||
111 | axi: axi@01c20054 { | |
112 | #clock-cells = <0>; | |
113 | compatible = "allwinner,sun4i-axi-clk"; | |
114 | reg = <0x01c20054 0x4>; | |
115 | clocks = <&cpu>; | |
3dce8324 | 116 | clock-output-names = "axi"; |
69144e3b MR |
117 | }; |
118 | ||
3dce8324 | 119 | axi_gates: clk@01c2005c { |
69144e3b MR |
120 | #clock-cells = <1>; |
121 | compatible = "allwinner,sun4i-axi-gates-clk"; | |
122 | reg = <0x01c2005c 0x4>; | |
123 | clocks = <&axi>; | |
124 | clock-output-names = "axi_dram"; | |
125 | }; | |
126 | ||
127 | ahb: ahb@01c20054 { | |
128 | #clock-cells = <0>; | |
129 | compatible = "allwinner,sun4i-ahb-clk"; | |
130 | reg = <0x01c20054 0x4>; | |
131 | clocks = <&axi>; | |
3dce8324 | 132 | clock-output-names = "ahb"; |
69144e3b MR |
133 | }; |
134 | ||
3dce8324 | 135 | ahb_gates: clk@01c20060 { |
69144e3b | 136 | #clock-cells = <1>; |
70be4ee6 | 137 | compatible = "allwinner,sun5i-a13-ahb-gates-clk"; |
69144e3b MR |
138 | reg = <0x01c20060 0x8>; |
139 | clocks = <&ahb>; | |
70be4ee6 MR |
140 | clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci", |
141 | "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0", | |
142 | "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram", | |
143 | "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_stimer", | |
144 | "ahb_ve", "ahb_lcd", "ahb_csi", "ahb_de_be", | |
145 | "ahb_de_fe", "ahb_iep", "ahb_mali400"; | |
69144e3b MR |
146 | }; |
147 | ||
148 | apb0: apb0@01c20054 { | |
149 | #clock-cells = <0>; | |
150 | compatible = "allwinner,sun4i-apb0-clk"; | |
151 | reg = <0x01c20054 0x4>; | |
152 | clocks = <&ahb>; | |
3dce8324 | 153 | clock-output-names = "apb0"; |
69144e3b MR |
154 | }; |
155 | ||
3dce8324 | 156 | apb0_gates: clk@01c20068 { |
69144e3b | 157 | #clock-cells = <1>; |
70be4ee6 | 158 | compatible = "allwinner,sun5i-a13-apb0-gates-clk"; |
69144e3b MR |
159 | reg = <0x01c20068 0x4>; |
160 | clocks = <&apb0>; | |
70be4ee6 | 161 | clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir"; |
69144e3b MR |
162 | }; |
163 | ||
69144e3b MR |
164 | apb1_mux: apb1_mux@01c20058 { |
165 | #clock-cells = <0>; | |
166 | compatible = "allwinner,sun4i-apb1-mux-clk"; | |
167 | reg = <0x01c20058 0x4>; | |
c3e5e66b | 168 | clocks = <&osc24M>, <&pll6 1>, <&osc32k>; |
3dce8324 | 169 | clock-output-names = "apb1_mux"; |
69144e3b MR |
170 | }; |
171 | ||
172 | apb1: apb1@01c20058 { | |
173 | #clock-cells = <0>; | |
174 | compatible = "allwinner,sun4i-apb1-clk"; | |
175 | reg = <0x01c20058 0x4>; | |
176 | clocks = <&apb1_mux>; | |
3dce8324 | 177 | clock-output-names = "apb1"; |
69144e3b MR |
178 | }; |
179 | ||
3dce8324 | 180 | apb1_gates: clk@01c2006c { |
69144e3b | 181 | #clock-cells = <1>; |
70be4ee6 | 182 | compatible = "allwinner,sun5i-a13-apb1-gates-clk"; |
69144e3b MR |
183 | reg = <0x01c2006c 0x4>; |
184 | clocks = <&apb1>; | |
185 | clock-output-names = "apb1_i2c0", "apb1_i2c1", | |
70be4ee6 | 186 | "apb1_i2c2", "apb1_uart1", "apb1_uart3"; |
69144e3b | 187 | }; |
8dc36bff EL |
188 | |
189 | nand_clk: clk@01c20080 { | |
190 | #clock-cells = <0>; | |
191 | compatible = "allwinner,sun4i-mod0-clk"; | |
192 | reg = <0x01c20080 0x4>; | |
193 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
194 | clock-output-names = "nand"; | |
195 | }; | |
196 | ||
197 | ms_clk: clk@01c20084 { | |
198 | #clock-cells = <0>; | |
199 | compatible = "allwinner,sun4i-mod0-clk"; | |
200 | reg = <0x01c20084 0x4>; | |
201 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
202 | clock-output-names = "ms"; | |
203 | }; | |
204 | ||
205 | mmc0_clk: clk@01c20088 { | |
206 | #clock-cells = <0>; | |
207 | compatible = "allwinner,sun4i-mod0-clk"; | |
208 | reg = <0x01c20088 0x4>; | |
209 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
210 | clock-output-names = "mmc0"; | |
211 | }; | |
212 | ||
213 | mmc1_clk: clk@01c2008c { | |
214 | #clock-cells = <0>; | |
215 | compatible = "allwinner,sun4i-mod0-clk"; | |
216 | reg = <0x01c2008c 0x4>; | |
217 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
218 | clock-output-names = "mmc1"; | |
219 | }; | |
220 | ||
221 | mmc2_clk: clk@01c20090 { | |
222 | #clock-cells = <0>; | |
223 | compatible = "allwinner,sun4i-mod0-clk"; | |
224 | reg = <0x01c20090 0x4>; | |
225 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
226 | clock-output-names = "mmc2"; | |
227 | }; | |
228 | ||
229 | ts_clk: clk@01c20098 { | |
230 | #clock-cells = <0>; | |
231 | compatible = "allwinner,sun4i-mod0-clk"; | |
232 | reg = <0x01c20098 0x4>; | |
233 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
234 | clock-output-names = "ts"; | |
235 | }; | |
236 | ||
237 | ss_clk: clk@01c2009c { | |
238 | #clock-cells = <0>; | |
239 | compatible = "allwinner,sun4i-mod0-clk"; | |
240 | reg = <0x01c2009c 0x4>; | |
241 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
242 | clock-output-names = "ss"; | |
243 | }; | |
244 | ||
245 | spi0_clk: clk@01c200a0 { | |
246 | #clock-cells = <0>; | |
247 | compatible = "allwinner,sun4i-mod0-clk"; | |
248 | reg = <0x01c200a0 0x4>; | |
249 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
250 | clock-output-names = "spi0"; | |
251 | }; | |
252 | ||
253 | spi1_clk: clk@01c200a4 { | |
254 | #clock-cells = <0>; | |
255 | compatible = "allwinner,sun4i-mod0-clk"; | |
256 | reg = <0x01c200a4 0x4>; | |
257 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
258 | clock-output-names = "spi1"; | |
259 | }; | |
260 | ||
261 | spi2_clk: clk@01c200a8 { | |
262 | #clock-cells = <0>; | |
263 | compatible = "allwinner,sun4i-mod0-clk"; | |
264 | reg = <0x01c200a8 0x4>; | |
265 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
266 | clock-output-names = "spi2"; | |
267 | }; | |
268 | ||
269 | ir0_clk: clk@01c200b0 { | |
270 | #clock-cells = <0>; | |
271 | compatible = "allwinner,sun4i-mod0-clk"; | |
272 | reg = <0x01c200b0 0x4>; | |
273 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
274 | clock-output-names = "ir0"; | |
275 | }; | |
118c07ae EL |
276 | |
277 | mbus_clk: clk@01c2015c { | |
278 | #clock-cells = <0>; | |
279 | compatible = "allwinner,sun4i-mod0-clk"; | |
280 | reg = <0x01c2015c 0x4>; | |
281 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
282 | clock-output-names = "mbus"; | |
283 | }; | |
69144e3b MR |
284 | }; |
285 | ||
278fe8b8 | 286 | soc@01c00000 { |
69144e3b MR |
287 | compatible = "simple-bus"; |
288 | #address-cells = <1>; | |
289 | #size-cells = <1>; | |
69144e3b MR |
290 | ranges; |
291 | ||
292 | intc: interrupt-controller@01c20400 { | |
6def126d | 293 | compatible = "allwinner,sun4i-ic"; |
69144e3b MR |
294 | reg = <0x01c20400 0x400>; |
295 | interrupt-controller; | |
296 | #interrupt-cells = <1>; | |
297 | }; | |
298 | ||
e10911e1 | 299 | pio: pinctrl@01c20800 { |
9e2dcb2f MR |
300 | compatible = "allwinner,sun5i-a13-pinctrl"; |
301 | reg = <0x01c20800 0x400>; | |
39138bc6 | 302 | interrupts = <28>; |
36386d6e | 303 | clocks = <&apb0_gates 5>; |
e10911e1 | 304 | gpio-controller; |
39138bc6 | 305 | interrupt-controller; |
9e2dcb2f MR |
306 | #address-cells = <1>; |
307 | #size-cells = <0>; | |
e10911e1 | 308 | #gpio-cells = <3>; |
4348cc64 MR |
309 | |
310 | uart1_pins_a: uart1@0 { | |
311 | allwinner,pins = "PE10", "PE11"; | |
312 | allwinner,function = "uart1"; | |
313 | allwinner,drive = <0>; | |
314 | allwinner,pull = <0>; | |
315 | }; | |
316 | ||
317 | uart1_pins_b: uart1@1 { | |
318 | allwinner,pins = "PG3", "PG4"; | |
319 | allwinner,function = "uart1"; | |
320 | allwinner,drive = <0>; | |
321 | allwinner,pull = <0>; | |
322 | }; | |
b4d7c230 MR |
323 | |
324 | i2c0_pins_a: i2c0@0 { | |
325 | allwinner,pins = "PB0", "PB1"; | |
326 | allwinner,function = "i2c0"; | |
327 | allwinner,drive = <0>; | |
328 | allwinner,pull = <0>; | |
329 | }; | |
330 | ||
331 | i2c1_pins_a: i2c1@0 { | |
332 | allwinner,pins = "PB15", "PB16"; | |
333 | allwinner,function = "i2c1"; | |
334 | allwinner,drive = <0>; | |
335 | allwinner,pull = <0>; | |
336 | }; | |
337 | ||
338 | i2c2_pins_a: i2c2@0 { | |
339 | allwinner,pins = "PB17", "PB18"; | |
340 | allwinner,function = "i2c2"; | |
341 | allwinner,drive = <0>; | |
342 | allwinner,pull = <0>; | |
343 | }; | |
9e2dcb2f | 344 | }; |
69144e3b MR |
345 | |
346 | timer@01c20c00 { | |
b6e1a53b | 347 | compatible = "allwinner,sun4i-timer"; |
69144e3b MR |
348 | reg = <0x01c20c00 0x90>; |
349 | interrupts = <22>; | |
350 | clocks = <&osc24M>; | |
351 | }; | |
352 | ||
353 | wdt: watchdog@01c20c90 { | |
0b19b7c2 | 354 | compatible = "allwinner,sun4i-wdt"; |
69144e3b MR |
355 | reg = <0x01c20c90 0x10>; |
356 | }; | |
357 | ||
2bad969f OS |
358 | sid: eeprom@01c23800 { |
359 | compatible = "allwinner,sun4i-sid"; | |
360 | reg = <0x01c23800 0x10>; | |
361 | }; | |
362 | ||
f65c93a0 HG |
363 | rtp: rtp@01c25000 { |
364 | compatible = "allwinner,sun4i-ts"; | |
365 | reg = <0x01c25000 0x100>; | |
366 | interrupts = <29>; | |
367 | }; | |
368 | ||
69144e3b MR |
369 | uart1: serial@01c28400 { |
370 | compatible = "snps,dw-apb-uart"; | |
371 | reg = <0x01c28400 0x400>; | |
372 | interrupts = <2>; | |
373 | reg-shift = <2>; | |
374 | reg-io-width = <4>; | |
375 | clocks = <&apb1_gates 17>; | |
376 | status = "disabled"; | |
377 | }; | |
378 | ||
379 | uart3: serial@01c28c00 { | |
380 | compatible = "snps,dw-apb-uart"; | |
381 | reg = <0x01c28c00 0x400>; | |
382 | interrupts = <4>; | |
383 | reg-shift = <2>; | |
384 | reg-io-width = <4>; | |
385 | clocks = <&apb1_gates 19>; | |
386 | status = "disabled"; | |
387 | }; | |
f1741fda MR |
388 | |
389 | i2c0: i2c@01c2ac00 { | |
390 | compatible = "allwinner,sun4i-i2c"; | |
391 | reg = <0x01c2ac00 0x400>; | |
392 | interrupts = <7>; | |
393 | clocks = <&apb1_gates 0>; | |
394 | clock-frequency = <100000>; | |
395 | status = "disabled"; | |
396 | }; | |
397 | ||
398 | i2c1: i2c@01c2b000 { | |
399 | compatible = "allwinner,sun4i-i2c"; | |
400 | reg = <0x01c2b000 0x400>; | |
401 | interrupts = <8>; | |
402 | clocks = <&apb1_gates 1>; | |
403 | clock-frequency = <100000>; | |
404 | status = "disabled"; | |
405 | }; | |
406 | ||
407 | i2c2: i2c@01c2b400 { | |
408 | compatible = "allwinner,sun4i-i2c"; | |
409 | reg = <0x01c2b400 0x400>; | |
410 | interrupts = <9>; | |
411 | clocks = <&apb1_gates 2>; | |
412 | clock-frequency = <100000>; | |
413 | status = "disabled"; | |
414 | }; | |
4411902a MR |
415 | |
416 | timer@01c60000 { | |
417 | compatible = "allwinner,sun5i-a13-hstimer"; | |
418 | reg = <0x01c60000 0x1000>; | |
419 | interrupts = <82>, <83>; | |
420 | clocks = <&ahb_gates 28>; | |
421 | }; | |
9e2dcb2f | 422 | }; |
d4da2ebb | 423 | }; |