projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| d4da2ebb MR |
1 | /* |
| 2 | * Copyright 2012 Maxime Ripard | |
| 3 | * | |
| 4 | * Maxime Ripard <maxime.ripard@free-electrons.com> | |
| 5 | * | |
| 6 | * The code contained herein is licensed under the GNU General Public | |
| 7 | * License. You may obtain a copy of the GNU General Public License | |
| 8 | * Version 2 or later at the following locations: | |
| 9 | * | |
| 10 | * http://www.opensource.org/licenses/gpl-license.html | |
| 11 | * http://www.gnu.org/copyleft/gpl.html | |
| 12 | */ | |
| 13 | ||
| 69144e3b | 14 | /include/ "skeleton.dtsi" |
| d4da2ebb MR |
15 | |
| 16 | / { | |
| 69144e3b MR |
17 | interrupt-parent = <&intc>; |
| 18 | ||
| 0cc774ef MR |
19 | aliases { |
| 20 | serial0 = &uart1; | |
| 21 | serial1 = &uart3; | |
| 22 | }; | |
| 23 | ||
| 69144e3b | 24 | cpus { |
| 8b2efa89 AB |
25 | #address-cells = <1>; |
| 26 | #size-cells = <0>; | |
| 69144e3b | 27 | cpu@0 { |
| 14c44aa5 | 28 | device_type = "cpu"; |
| 69144e3b | 29 | compatible = "arm,cortex-a8"; |
| 14c44aa5 | 30 | reg = <0x0>; |
| 69144e3b MR |
31 | }; |
| 32 | }; | |
| 33 | ||
| d4da2ebb MR |
34 | memory { |
| 35 | reg = <0x40000000 0x20000000>; | |
| 36 | }; | |
| 9e2dcb2f | 37 | |
| 69144e3b MR |
38 | clocks { |
| 39 | #address-cells = <1>; | |
| 40 | #size-cells = <1>; | |
| 41 | ranges; | |
| 42 | ||
| 43 | /* | |
| 44 | * This is a dummy clock, to be used as placeholder on | |
| 45 | * other mux clocks when a specific parent clock is not | |
| 46 | * yet implemented. It should be dropped when the driver | |
| 47 | * is complete. | |
| 48 | */ | |
| 49 | dummy: dummy { | |
| 50 | #clock-cells = <0>; | |
| 51 | compatible = "fixed-clock"; | |
| 52 | clock-frequency = <0>; | |
| 53 | }; | |
| 54 | ||
| 3dce8324 | 55 | osc24M: clk@01c20050 { |
| 69144e3b | 56 | #clock-cells = <0>; |
| bf6534a1 | 57 | compatible = "allwinner,sun4i-a10-osc-clk"; |
| 69144e3b | 58 | reg = <0x01c20050 0x4>; |
| 92fd6e06 | 59 | clock-frequency = <24000000>; |
| 3dce8324 | 60 | clock-output-names = "osc24M"; |
| 69144e3b MR |
61 | }; |
| 62 | ||
| 3dce8324 | 63 | osc32k: clk@0 { |
| 69144e3b MR |
64 | #clock-cells = <0>; |
| 65 | compatible = "fixed-clock"; | |
| 66 | clock-frequency = <32768>; | |
| 3dce8324 | 67 | clock-output-names = "osc32k"; |
| 69144e3b MR |
68 | }; |
| 69 | ||
| 3dce8324 | 70 | pll1: clk@01c20000 { |
| 69144e3b | 71 | #clock-cells = <0>; |
| bf6534a1 | 72 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
| 69144e3b MR |
73 | reg = <0x01c20000 0x4>; |
| 74 | clocks = <&osc24M>; | |
| 3dce8324 | 75 | clock-output-names = "pll1"; |
| 69144e3b MR |
76 | }; |
| 77 | ||
| 3dce8324 | 78 | pll4: clk@01c20018 { |
| ec5589f7 | 79 | #clock-cells = <0>; |
| bf6534a1 | 80 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
| ec5589f7 EL |
81 | reg = <0x01c20018 0x4>; |
| 82 | clocks = <&osc24M>; | |
| 3dce8324 | 83 | clock-output-names = "pll4"; |
| ec5589f7 EL |
84 | }; |
| 85 | ||
| 3dce8324 | 86 | pll5: clk@01c20020 { |
| c3e5e66b | 87 | #clock-cells = <1>; |
| bf6534a1 | 88 | compatible = "allwinner,sun4i-a10-pll5-clk"; |
| c3e5e66b EL |
89 | reg = <0x01c20020 0x4>; |
| 90 | clocks = <&osc24M>; | |
| 91 | clock-output-names = "pll5_ddr", "pll5_other"; | |
| 92 | }; | |
| 93 | ||
| 3dce8324 | 94 | pll6: clk@01c20028 { |
| c3e5e66b | 95 | #clock-cells = <1>; |
| bf6534a1 | 96 | compatible = "allwinner,sun4i-a10-pll6-clk"; |
| c3e5e66b EL |
97 | reg = <0x01c20028 0x4>; |
| 98 | clocks = <&osc24M>; | |
| 99 | clock-output-names = "pll6_sata", "pll6_other", "pll6"; | |
| 100 | }; | |
| 101 | ||
| 69144e3b MR |
102 | /* dummy is 200M */ |
| 103 | cpu: cpu@01c20054 { | |
| 104 | #clock-cells = <0>; | |
| bf6534a1 | 105 | compatible = "allwinner,sun4i-a10-cpu-clk"; |
| 69144e3b MR |
106 | reg = <0x01c20054 0x4>; |
| 107 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; | |
| 3dce8324 | 108 | clock-output-names = "cpu"; |
| 69144e3b MR |
109 | }; |
| 110 | ||
| 111 | axi: axi@01c20054 { | |
| 112 | #clock-cells = <0>; | |
| bf6534a1 | 113 | compatible = "allwinner,sun4i-a10-axi-clk"; |
| 69144e3b MR |
114 | reg = <0x01c20054 0x4>; |
| 115 | clocks = <&cpu>; | |
| 3dce8324 | 116 | clock-output-names = "axi"; |
| 69144e3b MR |
117 | }; |
| 118 | ||
| 3dce8324 | 119 | axi_gates: clk@01c2005c { |
| 69144e3b | 120 | #clock-cells = <1>; |
| bf6534a1 | 121 | compatible = "allwinner,sun4i-a10-axi-gates-clk"; |
| 69144e3b MR |
122 | reg = <0x01c2005c 0x4>; |
| 123 | clocks = <&axi>; | |
| 124 | clock-output-names = "axi_dram"; | |
| 125 | }; | |
| 126 | ||
| 127 | ahb: ahb@01c20054 { | |
| 128 | #clock-cells = <0>; | |
| bf6534a1 | 129 | compatible = "allwinner,sun4i-a10-ahb-clk"; |
| 69144e3b MR |
130 | reg = <0x01c20054 0x4>; |
| 131 | clocks = <&axi>; | |
| 3dce8324 | 132 | clock-output-names = "ahb"; |
| 69144e3b MR |
133 | }; |
| 134 | ||
| 3dce8324 | 135 | ahb_gates: clk@01c20060 { |
| 69144e3b | 136 | #clock-cells = <1>; |
| 70be4ee6 | 137 | compatible = "allwinner,sun5i-a13-ahb-gates-clk"; |
| 69144e3b MR |
138 | reg = <0x01c20060 0x8>; |
| 139 | clocks = <&ahb>; | |
| 70be4ee6 MR |
140 | clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci", |
| 141 | "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0", | |
| 142 | "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram", | |
| 143 | "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_stimer", | |
| 144 | "ahb_ve", "ahb_lcd", "ahb_csi", "ahb_de_be", | |
| 145 | "ahb_de_fe", "ahb_iep", "ahb_mali400"; | |
| 69144e3b MR |
146 | }; |
| 147 | ||
| 148 | apb0: apb0@01c20054 { | |
| 149 | #clock-cells = <0>; | |
| bf6534a1 | 150 | compatible = "allwinner,sun4i-a10-apb0-clk"; |
| 69144e3b MR |
151 | reg = <0x01c20054 0x4>; |
| 152 | clocks = <&ahb>; | |
| 3dce8324 | 153 | clock-output-names = "apb0"; |
| 69144e3b MR |
154 | }; |
| 155 | ||
| 3dce8324 | 156 | apb0_gates: clk@01c20068 { |
| 69144e3b | 157 | #clock-cells = <1>; |
| 70be4ee6 | 158 | compatible = "allwinner,sun5i-a13-apb0-gates-clk"; |
| 69144e3b MR |
159 | reg = <0x01c20068 0x4>; |
| 160 | clocks = <&apb0>; | |
| 70be4ee6 | 161 | clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir"; |
| 69144e3b MR |
162 | }; |
| 163 | ||
| 69144e3b MR |
164 | apb1_mux: apb1_mux@01c20058 { |
| 165 | #clock-cells = <0>; | |
| bf6534a1 | 166 | compatible = "allwinner,sun4i-a10-apb1-mux-clk"; |
| 69144e3b | 167 | reg = <0x01c20058 0x4>; |
| c3e5e66b | 168 | clocks = <&osc24M>, <&pll6 1>, <&osc32k>; |
| 3dce8324 | 169 | clock-output-names = "apb1_mux"; |
| 69144e3b MR |
170 | }; |
| 171 | ||
| 172 | apb1: apb1@01c20058 { | |
| 173 | #clock-cells = <0>; | |
| bf6534a1 | 174 | compatible = "allwinner,sun4i-a10-apb1-clk"; |
| 69144e3b MR |
175 | reg = <0x01c20058 0x4>; |
| 176 | clocks = <&apb1_mux>; | |
| 3dce8324 | 177 | clock-output-names = "apb1"; |
| 69144e3b MR |
178 | }; |
| 179 | ||
| 3dce8324 | 180 | apb1_gates: clk@01c2006c { |
| 69144e3b | 181 | #clock-cells = <1>; |
| 70be4ee6 | 182 | compatible = "allwinner,sun5i-a13-apb1-gates-clk"; |
| 69144e3b MR |
183 | reg = <0x01c2006c 0x4>; |
| 184 | clocks = <&apb1>; | |
| 185 | clock-output-names = "apb1_i2c0", "apb1_i2c1", | |
| 70be4ee6 | 186 | "apb1_i2c2", "apb1_uart1", "apb1_uart3"; |
| 69144e3b | 187 | }; |
| 8dc36bff EL |
188 | |
| 189 | nand_clk: clk@01c20080 { | |
| 190 | #clock-cells = <0>; | |
| bf6534a1 | 191 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 8dc36bff EL |
192 | reg = <0x01c20080 0x4>; |
| 193 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 194 | clock-output-names = "nand"; | |
| 195 | }; | |
| 196 | ||
| 197 | ms_clk: clk@01c20084 { | |
| 198 | #clock-cells = <0>; | |
| bf6534a1 | 199 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 8dc36bff EL |
200 | reg = <0x01c20084 0x4>; |
| 201 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 202 | clock-output-names = "ms"; | |
| 203 | }; | |
| 204 | ||
| 205 | mmc0_clk: clk@01c20088 { | |
| 206 | #clock-cells = <0>; | |
| bf6534a1 | 207 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 8dc36bff EL |
208 | reg = <0x01c20088 0x4>; |
| 209 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 210 | clock-output-names = "mmc0"; | |
| 211 | }; | |
| 212 | ||
| 213 | mmc1_clk: clk@01c2008c { | |
| 214 | #clock-cells = <0>; | |
| bf6534a1 | 215 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 8dc36bff EL |
216 | reg = <0x01c2008c 0x4>; |
| 217 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 218 | clock-output-names = "mmc1"; | |
| 219 | }; | |
| 220 | ||
| 221 | mmc2_clk: clk@01c20090 { | |
| 222 | #clock-cells = <0>; | |
| bf6534a1 | 223 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 8dc36bff EL |
224 | reg = <0x01c20090 0x4>; |
| 225 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 226 | clock-output-names = "mmc2"; | |
| 227 | }; | |
| 228 | ||
| 229 | ts_clk: clk@01c20098 { | |
| 230 | #clock-cells = <0>; | |
| bf6534a1 | 231 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 8dc36bff EL |
232 | reg = <0x01c20098 0x4>; |
| 233 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 234 | clock-output-names = "ts"; | |
| 235 | }; | |
| 236 | ||
| 237 | ss_clk: clk@01c2009c { | |
| 238 | #clock-cells = <0>; | |
| bf6534a1 | 239 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 8dc36bff EL |
240 | reg = <0x01c2009c 0x4>; |
| 241 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 242 | clock-output-names = "ss"; | |
| 243 | }; | |
| 244 | ||
| 245 | spi0_clk: clk@01c200a0 { | |
| 246 | #clock-cells = <0>; | |
| bf6534a1 | 247 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 8dc36bff EL |
248 | reg = <0x01c200a0 0x4>; |
| 249 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 250 | clock-output-names = "spi0"; | |
| 251 | }; | |
| 252 | ||
| 253 | spi1_clk: clk@01c200a4 { | |
| 254 | #clock-cells = <0>; | |
| bf6534a1 | 255 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 8dc36bff EL |
256 | reg = <0x01c200a4 0x4>; |
| 257 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 258 | clock-output-names = "spi1"; | |
| 259 | }; | |
| 260 | ||
| 261 | spi2_clk: clk@01c200a8 { | |
| 262 | #clock-cells = <0>; | |
| bf6534a1 | 263 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 8dc36bff EL |
264 | reg = <0x01c200a8 0x4>; |
| 265 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 266 | clock-output-names = "spi2"; | |
| 267 | }; | |
| 268 | ||
| 269 | ir0_clk: clk@01c200b0 { | |
| 270 | #clock-cells = <0>; | |
| bf6534a1 | 271 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 8dc36bff EL |
272 | reg = <0x01c200b0 0x4>; |
| 273 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 274 | clock-output-names = "ir0"; | |
| 275 | }; | |
| 118c07ae | 276 | |
| 4c5d72f8 RB |
277 | usb_clk: clk@01c200cc { |
| 278 | #clock-cells = <1>; | |
| 279 | #reset-cells = <1>; | |
| 280 | compatible = "allwinner,sun5i-a13-usb-clk"; | |
| 281 | reg = <0x01c200cc 0x4>; | |
| 282 | clocks = <&pll6 1>; | |
| 283 | clock-output-names = "usb_ohci0", "usb_phy"; | |
| 284 | }; | |
| 285 | ||
| 118c07ae EL |
286 | mbus_clk: clk@01c2015c { |
| 287 | #clock-cells = <0>; | |
| bf6534a1 | 288 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 118c07ae EL |
289 | reg = <0x01c2015c 0x4>; |
| 290 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 291 | clock-output-names = "mbus"; | |
| 292 | }; | |
| 69144e3b MR |
293 | }; |
| 294 | ||
| 278fe8b8 | 295 | soc@01c00000 { |
| 69144e3b MR |
296 | compatible = "simple-bus"; |
| 297 | #address-cells = <1>; | |
| 298 | #size-cells = <1>; | |
| 69144e3b MR |
299 | ranges; |
| 300 | ||
| 301 | intc: interrupt-controller@01c20400 { | |
| 6def126d | 302 | compatible = "allwinner,sun4i-ic"; |
| 69144e3b MR |
303 | reg = <0x01c20400 0x400>; |
| 304 | interrupt-controller; | |
| 305 | #interrupt-cells = <1>; | |
| 306 | }; | |
| 307 | ||
| e10911e1 | 308 | pio: pinctrl@01c20800 { |
| 9e2dcb2f MR |
309 | compatible = "allwinner,sun5i-a13-pinctrl"; |
| 310 | reg = <0x01c20800 0x400>; | |
| 39138bc6 | 311 | interrupts = <28>; |
| 36386d6e | 312 | clocks = <&apb0_gates 5>; |
| e10911e1 | 313 | gpio-controller; |
| 39138bc6 | 314 | interrupt-controller; |
| 9e2dcb2f MR |
315 | #address-cells = <1>; |
| 316 | #size-cells = <0>; | |
| e10911e1 | 317 | #gpio-cells = <3>; |
| 4348cc64 MR |
318 | |
| 319 | uart1_pins_a: uart1@0 { | |
| 320 | allwinner,pins = "PE10", "PE11"; | |
| 321 | allwinner,function = "uart1"; | |
| 322 | allwinner,drive = <0>; | |
| 323 | allwinner,pull = <0>; | |
| 324 | }; | |
| 325 | ||
| 326 | uart1_pins_b: uart1@1 { | |
| 327 | allwinner,pins = "PG3", "PG4"; | |
| 328 | allwinner,function = "uart1"; | |
| 329 | allwinner,drive = <0>; | |
| 330 | allwinner,pull = <0>; | |
| 331 | }; | |
| b4d7c230 MR |
332 | |
| 333 | i2c0_pins_a: i2c0@0 { | |
| 334 | allwinner,pins = "PB0", "PB1"; | |
| 335 | allwinner,function = "i2c0"; | |
| 336 | allwinner,drive = <0>; | |
| 337 | allwinner,pull = <0>; | |
| 338 | }; | |
| 339 | ||
| 340 | i2c1_pins_a: i2c1@0 { | |
| 341 | allwinner,pins = "PB15", "PB16"; | |
| 342 | allwinner,function = "i2c1"; | |
| 343 | allwinner,drive = <0>; | |
| 344 | allwinner,pull = <0>; | |
| 345 | }; | |
| 346 | ||
| 347 | i2c2_pins_a: i2c2@0 { | |
| 348 | allwinner,pins = "PB17", "PB18"; | |
| 349 | allwinner,function = "i2c2"; | |
| 350 | allwinner,drive = <0>; | |
| 351 | allwinner,pull = <0>; | |
| 352 | }; | |
| 9e2dcb2f | 353 | }; |
| 69144e3b MR |
354 | |
| 355 | timer@01c20c00 { | |
| b6e1a53b | 356 | compatible = "allwinner,sun4i-timer"; |
| 69144e3b MR |
357 | reg = <0x01c20c00 0x90>; |
| 358 | interrupts = <22>; | |
| 359 | clocks = <&osc24M>; | |
| 360 | }; | |
| 361 | ||
| 362 | wdt: watchdog@01c20c90 { | |
| 0b19b7c2 | 363 | compatible = "allwinner,sun4i-wdt"; |
| 69144e3b MR |
364 | reg = <0x01c20c90 0x10>; |
| 365 | }; | |
| 366 | ||
| 2bad969f OS |
367 | sid: eeprom@01c23800 { |
| 368 | compatible = "allwinner,sun4i-sid"; | |
| 369 | reg = <0x01c23800 0x10>; | |
| 370 | }; | |
| 371 | ||
| f65c93a0 HG |
372 | rtp: rtp@01c25000 { |
| 373 | compatible = "allwinner,sun4i-ts"; | |
| 374 | reg = <0x01c25000 0x100>; | |
| 375 | interrupts = <29>; | |
| 376 | }; | |
| 377 | ||
| 69144e3b MR |
378 | uart1: serial@01c28400 { |
| 379 | compatible = "snps,dw-apb-uart"; | |
| 380 | reg = <0x01c28400 0x400>; | |
| 381 | interrupts = <2>; | |
| 382 | reg-shift = <2>; | |
| 383 | reg-io-width = <4>; | |
| 384 | clocks = <&apb1_gates 17>; | |
| 385 | status = "disabled"; | |
| 386 | }; | |
| 387 | ||
| 388 | uart3: serial@01c28c00 { | |
| 389 | compatible = "snps,dw-apb-uart"; | |
| 390 | reg = <0x01c28c00 0x400>; | |
| 391 | interrupts = <4>; | |
| 392 | reg-shift = <2>; | |
| 393 | reg-io-width = <4>; | |
| 394 | clocks = <&apb1_gates 19>; | |
| 395 | status = "disabled"; | |
| 396 | }; | |
| f1741fda MR |
397 | |
| 398 | i2c0: i2c@01c2ac00 { | |
| 399 | compatible = "allwinner,sun4i-i2c"; | |
| 400 | reg = <0x01c2ac00 0x400>; | |
| 401 | interrupts = <7>; | |
| 402 | clocks = <&apb1_gates 0>; | |
| 403 | clock-frequency = <100000>; | |
| 404 | status = "disabled"; | |
| 405 | }; | |
| 406 | ||
| 407 | i2c1: i2c@01c2b000 { | |
| 408 | compatible = "allwinner,sun4i-i2c"; | |
| 409 | reg = <0x01c2b000 0x400>; | |
| 410 | interrupts = <8>; | |
| 411 | clocks = <&apb1_gates 1>; | |
| 412 | clock-frequency = <100000>; | |
| 413 | status = "disabled"; | |
| 414 | }; | |
| 415 | ||
| 416 | i2c2: i2c@01c2b400 { | |
| 417 | compatible = "allwinner,sun4i-i2c"; | |
| 418 | reg = <0x01c2b400 0x400>; | |
| 419 | interrupts = <9>; | |
| 420 | clocks = <&apb1_gates 2>; | |
| 421 | clock-frequency = <100000>; | |
| 422 | status = "disabled"; | |
| 423 | }; | |
| 4411902a MR |
424 | |
| 425 | timer@01c60000 { | |
| 426 | compatible = "allwinner,sun5i-a13-hstimer"; | |
| 427 | reg = <0x01c60000 0x1000>; | |
| 428 | interrupts = <82>, <83>; | |
| 429 | clocks = <&ahb_gates 28>; | |
| 430 | }; | |
| 9e2dcb2f | 431 | }; |
| d4da2ebb | 432 | }; |