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ARM: dts: sun7i: Add cpu thermal zones to dtsi
[deliverable/linux.git] / arch / arm / boot / dts / sun5i-a13.dtsi
CommitLineData
d4da2ebb
MR		 1/*
2 * Copyright 2012 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
71455701 14#include "skeleton.dtsi"
d4da2ebb 15
1f9f6a78 16#include <dt-bindings/dma/sun4i-a10.h>
092a0c3b 17#include <dt-bindings/pinctrl/sun4i-a10.h>
1f9f6a78 18
d4da2ebb 19/ {
69144e3b
MR		 20 interrupt-parent = <&intc>;
21
0cc774ef
MR		 22 aliases {
23 serial0 = &uart1;
24 serial1 = &uart3;
25 };
26
fd18c7ea
HG		 27 chosen {
28 #address-cells = <1>;
29 #size-cells = <1>;
30 ranges;
31
32 framebuffer@0 {
33 compatible = "allwinner,simple-framebuffer",
34 "simple-framebuffer";
35 allwinner,pipeline = "de_be0-lcd0";
36 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
37 status = "disabled";
38 };
39 };
40
69144e3b 41 cpus {
8b2efa89
AB		 42 #address-cells = <1>;
43 #size-cells = <0>;
882facf7
CYT		 44
45 cpu0: cpu@0 {
14c44aa5 46 device_type = "cpu";
69144e3b 47 compatible = "arm,cortex-a8";
14c44aa5 48 reg = <0x0>;
882facf7
CYT		 49 clocks = <&cpu>;
50 clock-latency = <244144>; /* 8 32k periods */
51 operating-points = <
52 /* kHz uV */
53 1104000 1500000
54 1008000 1400000
55 912000 1350000
56 864000 1300000
57 624000 1200000
58 576000 1200000
59 432000 1200000
60 >;
61 #cooling-cells = <2>;
62 cooling-min-level = <0>;
63 cooling-max-level = <6>;
69144e3b
MR		 64 };
65 };
66
d4da2ebb
MR		 67 memory {
68 reg = <0x40000000 0x20000000>;
69 };
9e2dcb2f 70
69144e3b
MR		 71 clocks {
72 #address-cells = <1>;
73 #size-cells = <1>;
74 ranges;
75
76 /*
77 * This is a dummy clock, to be used as placeholder on
78 * other mux clocks when a specific parent clock is not
79 * yet implemented. It should be dropped when the driver
80 * is complete.
81 */
82 dummy: dummy {
83 #clock-cells = <0>;
84 compatible = "fixed-clock";
85 clock-frequency = <0>;
86 };
87
3dce8324 88 osc24M: clk@01c20050 {
69144e3b 89 #clock-cells = <0>;
bf6534a1 90 compatible = "allwinner,sun4i-a10-osc-clk";
69144e3b 91 reg = <0x01c20050 0x4>;
92fd6e06 92 clock-frequency = <24000000>;
3dce8324 93 clock-output-names = "osc24M";
69144e3b
MR		 94 };
95
3dce8324 96 osc32k: clk@0 {
69144e3b
MR		 97 #clock-cells = <0>;
98 compatible = "fixed-clock";
99 clock-frequency = <32768>;
3dce8324 100 clock-output-names = "osc32k";
69144e3b
MR		 101 };
102
3dce8324 103 pll1: clk@01c20000 {
69144e3b 104 #clock-cells = <0>;
bf6534a1 105 compatible = "allwinner,sun4i-a10-pll1-clk";
69144e3b
MR		 106 reg = <0x01c20000 0x4>;
107 clocks = <&osc24M>;
3dce8324 108 clock-output-names = "pll1";
69144e3b
MR		 109 };
110
3dce8324 111 pll4: clk@01c20018 {
ec5589f7 112 #clock-cells = <0>;
bf6534a1 113 compatible = "allwinner,sun4i-a10-pll1-clk";
ec5589f7
EL		 114 reg = <0x01c20018 0x4>;
115 clocks = <&osc24M>;
3dce8324 116 clock-output-names = "pll4";
ec5589f7
EL		 117 };
118
3dce8324 119 pll5: clk@01c20020 {
c3e5e66b 120 #clock-cells = <1>;
bf6534a1 121 compatible = "allwinner,sun4i-a10-pll5-clk";
c3e5e66b
EL		 122 reg = <0x01c20020 0x4>;
123 clocks = <&osc24M>;
124 clock-output-names = "pll5_ddr", "pll5_other";
125 };
126
3dce8324 127 pll6: clk@01c20028 {
c3e5e66b 128 #clock-cells = <1>;
bf6534a1 129 compatible = "allwinner,sun4i-a10-pll6-clk";
c3e5e66b
EL		 130 reg = <0x01c20028 0x4>;
131 clocks = <&osc24M>;
132 clock-output-names = "pll6_sata", "pll6_other", "pll6";
133 };
134
69144e3b
MR		 135 /* dummy is 200M */
136 cpu: cpu@01c20054 {
137 #clock-cells = <0>;
bf6534a1 138 compatible = "allwinner,sun4i-a10-cpu-clk";
69144e3b
MR		 139 reg = <0x01c20054 0x4>;
140 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
3dce8324 141 clock-output-names = "cpu";
69144e3b
MR		 142 };
143
144 axi: axi@01c20054 {
145 #clock-cells = <0>;
bf6534a1 146 compatible = "allwinner,sun4i-a10-axi-clk";
69144e3b
MR		 147 reg = <0x01c20054 0x4>;
148 clocks = <&cpu>;
3dce8324 149 clock-output-names = "axi";
69144e3b
MR		 150 };
151
3dce8324 152 axi_gates: clk@01c2005c {
69144e3b 153 #clock-cells = <1>;
bf6534a1 154 compatible = "allwinner,sun4i-a10-axi-gates-clk";
69144e3b
MR		 155 reg = <0x01c2005c 0x4>;
156 clocks = <&axi>;
157 clock-output-names = "axi_dram";
158 };
159
160 ahb: ahb@01c20054 {
161 #clock-cells = <0>;
bf6534a1 162 compatible = "allwinner,sun4i-a10-ahb-clk";
69144e3b
MR		 163 reg = <0x01c20054 0x4>;
164 clocks = <&axi>;
3dce8324 165 clock-output-names = "ahb";
69144e3b
MR		 166 };
167
3dce8324 168 ahb_gates: clk@01c20060 {
69144e3b 169 #clock-cells = <1>;
70be4ee6 170 compatible = "allwinner,sun5i-a13-ahb-gates-clk";
69144e3b
MR		 171 reg = <0x01c20060 0x8>;
172 clocks = <&ahb>;
70be4ee6
MR		 173 clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
174 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
175 "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
176 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_stimer",
177 "ahb_ve", "ahb_lcd", "ahb_csi", "ahb_de_be",
178 "ahb_de_fe", "ahb_iep", "ahb_mali400";
69144e3b
MR		 179 };
180
181 apb0: apb0@01c20054 {
182 #clock-cells = <0>;
bf6534a1 183 compatible = "allwinner,sun4i-a10-apb0-clk";
69144e3b
MR		 184 reg = <0x01c20054 0x4>;
185 clocks = <&ahb>;
3dce8324 186 clock-output-names = "apb0";
69144e3b
MR		 187 };
188
3dce8324 189 apb0_gates: clk@01c20068 {
69144e3b 190 #clock-cells = <1>;
70be4ee6 191 compatible = "allwinner,sun5i-a13-apb0-gates-clk";
69144e3b
MR		 192 reg = <0x01c20068 0x4>;
193 clocks = <&apb0>;
70be4ee6 194 clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
69144e3b
MR		 195 };
196
acbcc0f0 197 apb1: clk@01c20058 {
69144e3b 198 #clock-cells = <0>;
bf6534a1 199 compatible = "allwinner,sun4i-a10-apb1-clk";
69144e3b 200 reg = <0x01c20058 0x4>;
acbcc0f0 201 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
3dce8324 202 clock-output-names = "apb1";
69144e3b
MR		 203 };
204
3dce8324 205 apb1_gates: clk@01c2006c {
69144e3b 206 #clock-cells = <1>;
70be4ee6 207 compatible = "allwinner,sun5i-a13-apb1-gates-clk";
69144e3b
MR		 208 reg = <0x01c2006c 0x4>;
209 clocks = <&apb1>;
210 clock-output-names = "apb1_i2c0", "apb1_i2c1",
70be4ee6 211 "apb1_i2c2", "apb1_uart1", "apb1_uart3";
69144e3b 212 };
8dc36bff
EL		 213
214 nand_clk: clk@01c20080 {
215 #clock-cells = <0>;
bf6534a1 216 compatible = "allwinner,sun4i-a10-mod0-clk";
8dc36bff
EL		 217 reg = <0x01c20080 0x4>;
218 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
219 clock-output-names = "nand";
220 };
221
222 ms_clk: clk@01c20084 {
223 #clock-cells = <0>;
bf6534a1 224 compatible = "allwinner,sun4i-a10-mod0-clk";
8dc36bff
EL		 225 reg = <0x01c20084 0x4>;
226 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
227 clock-output-names = "ms";
228 };
229
230 mmc0_clk: clk@01c20088 {
231 #clock-cells = <0>;
bf6534a1 232 compatible = "allwinner,sun4i-a10-mod0-clk";
8dc36bff
EL		 233 reg = <0x01c20088 0x4>;
234 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
235 clock-output-names = "mmc0";
236 };
237
238 mmc1_clk: clk@01c2008c {
239 #clock-cells = <0>;
bf6534a1 240 compatible = "allwinner,sun4i-a10-mod0-clk";
8dc36bff
EL		 241 reg = <0x01c2008c 0x4>;
242 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
243 clock-output-names = "mmc1";
244 };
245
246 mmc2_clk: clk@01c20090 {
247 #clock-cells = <0>;
bf6534a1 248 compatible = "allwinner,sun4i-a10-mod0-clk";
8dc36bff
EL		 249 reg = <0x01c20090 0x4>;
250 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
251 clock-output-names = "mmc2";
252 };
253
254 ts_clk: clk@01c20098 {
255 #clock-cells = <0>;
bf6534a1 256 compatible = "allwinner,sun4i-a10-mod0-clk";
8dc36bff
EL		 257 reg = <0x01c20098 0x4>;
258 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
259 clock-output-names = "ts";
260 };
261
262 ss_clk: clk@01c2009c {
263 #clock-cells = <0>;
bf6534a1 264 compatible = "allwinner,sun4i-a10-mod0-clk";
8dc36bff
EL		 265 reg = <0x01c2009c 0x4>;
266 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
267 clock-output-names = "ss";
268 };
269
270 spi0_clk: clk@01c200a0 {
271 #clock-cells = <0>;
bf6534a1 272 compatible = "allwinner,sun4i-a10-mod0-clk";
8dc36bff
EL		 273 reg = <0x01c200a0 0x4>;
274 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
275 clock-output-names = "spi0";
276 };
277
278 spi1_clk: clk@01c200a4 {
279 #clock-cells = <0>;
bf6534a1 280 compatible = "allwinner,sun4i-a10-mod0-clk";
8dc36bff
EL		 281 reg = <0x01c200a4 0x4>;
282 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
283 clock-output-names = "spi1";
284 };
285
286 spi2_clk: clk@01c200a8 {
287 #clock-cells = <0>;
bf6534a1 288 compatible = "allwinner,sun4i-a10-mod0-clk";
8dc36bff
EL		 289 reg = <0x01c200a8 0x4>;
290 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
291 clock-output-names = "spi2";
292 };
293
294 ir0_clk: clk@01c200b0 {
295 #clock-cells = <0>;
bf6534a1 296 compatible = "allwinner,sun4i-a10-mod0-clk";
8dc36bff
EL		 297 reg = <0x01c200b0 0x4>;
298 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
299 clock-output-names = "ir0";
300 };
118c07ae 301
4c5d72f8
RB		 302 usb_clk: clk@01c200cc {
303 #clock-cells = <1>;
304 #reset-cells = <1>;
305 compatible = "allwinner,sun5i-a13-usb-clk";
306 reg = <0x01c200cc 0x4>;
307 clocks = <&pll6 1>;
308 clock-output-names = "usb_ohci0", "usb_phy";
309 };
310
118c07ae
EL		 311 mbus_clk: clk@01c2015c {
312 #clock-cells = <0>;
7868c5eb 313 compatible = "allwinner,sun5i-a13-mbus-clk";
118c07ae
EL		 314 reg = <0x01c2015c 0x4>;
315 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
316 clock-output-names = "mbus";
317 };
69144e3b
MR		 318 };
319
278fe8b8 320 soc@01c00000 {
69144e3b
MR		 321 compatible = "simple-bus";
322 #address-cells = <1>;
323 #size-cells = <1>;
69144e3b
MR		 324 ranges;
325
6a5775e4
EL		 326 dma: dma-controller@01c02000 {
327 compatible = "allwinner,sun4i-a10-dma";
328 reg = <0x01c02000 0x1000>;
329 interrupts = <27>;
330 clocks = <&ahb_gates 6>;
331 #dma-cells = <2>;
332 };
333
8f8658b7
MR		 334 spi0: spi@01c05000 {
335 compatible = "allwinner,sun4i-a10-spi";
336 reg = <0x01c05000 0x1000>;
337 interrupts = <10>;
338 clocks = <&ahb_gates 20>, <&spi0_clk>;
339 clock-names = "ahb", "mod";
1f9f6a78
MR		 340 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
341 <&dma SUN4I_DMA_DEDICATED 26>;
fed4c5c6 342 dma-names = "rx", "tx";
8f8658b7
MR		 343 status = "disabled";
344 #address-cells = <1>;
345 #size-cells = <0>;
346 };
347
348 spi1: spi@01c06000 {
349 compatible = "allwinner,sun4i-a10-spi";
350 reg = <0x01c06000 0x1000>;
351 interrupts = <11>;
352 clocks = <&ahb_gates 21>, <&spi1_clk>;
353 clock-names = "ahb", "mod";
1f9f6a78
MR		 354 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
355 <&dma SUN4I_DMA_DEDICATED 8>;
fed4c5c6 356 dma-names = "rx", "tx";
8f8658b7
MR		 357 status = "disabled";
358 #address-cells = <1>;
359 #size-cells = <0>;
360 };
361
d3aed1df
DL		 362 mmc0: mmc@01c0f000 {
363 compatible = "allwinner,sun5i-a13-mmc";
364 reg = <0x01c0f000 0x1000>;
365 clocks = <&ahb_gates 8>, <&mmc0_clk>;
366 clock-names = "ahb", "mmc";
367 interrupts = <32>;
368 status = "disabled";
369 };
370
371 mmc2: mmc@01c11000 {
372 compatible = "allwinner,sun5i-a13-mmc";
373 reg = <0x01c11000 0x1000>;
374 clocks = <&ahb_gates 10>, <&mmc2_clk>;
375 clock-names = "ahb", "mmc";
376 interrupts = <34>;
377 status = "disabled";
378 };
379
06c7d52f
RB		 380 usbphy: phy@01c13400 {
381 #phy-cells = <1>;
382 compatible = "allwinner,sun5i-a13-usb-phy";
383 reg = <0x01c13400 0x10 0x01c14800 0x4>;
384 reg-names = "phy_ctrl", "pmu1";
385 clocks = <&usb_clk 8>;
386 clock-names = "usb_phy";
4dba4185
CYT		 387 resets = <&usb_clk 0>, <&usb_clk 1>;
388 reset-names = "usb0_reset", "usb1_reset";
06c7d52f
RB		 389 status = "disabled";
390 };
391
392 ehci0: usb@01c14000 {
393 compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
394 reg = <0x01c14000 0x100>;
395 interrupts = <39>;
396 clocks = <&ahb_gates 1>;
397 phys = <&usbphy 1>;
398 phy-names = "usb";
399 status = "disabled";
400 };
401
402 ohci0: usb@01c14400 {
403 compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
404 reg = <0x01c14400 0x100>;
405 interrupts = <40>;
406 clocks = <&usb_clk 6>, <&ahb_gates 2>;
407 phys = <&usbphy 1>;
408 phy-names = "usb";
409 status = "disabled";
410 };
411
8f8658b7
MR		 412 spi2: spi@01c17000 {
413 compatible = "allwinner,sun4i-a10-spi";
414 reg = <0x01c17000 0x1000>;
415 interrupts = <12>;
416 clocks = <&ahb_gates 22>, <&spi2_clk>;
417 clock-names = "ahb", "mod";
1f9f6a78
MR		 418 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
419 <&dma SUN4I_DMA_DEDICATED 28>;
fed4c5c6 420 dma-names = "rx", "tx";
8f8658b7
MR		 421 status = "disabled";
422 #address-cells = <1>;
423 #size-cells = <0>;
424 };
425
69144e3b 426 intc: interrupt-controller@01c20400 {
09504a7d 427 compatible = "allwinner,sun4i-a10-ic";
69144e3b
MR		 428 reg = <0x01c20400 0x400>;
429 interrupt-controller;
430 #interrupt-cells = <1>;
431 };
432
e10911e1 433 pio: pinctrl@01c20800 {
9e2dcb2f
MR		 434 compatible = "allwinner,sun5i-a13-pinctrl";
435 reg = <0x01c20800 0x400>;
39138bc6 436 interrupts = <28>;
36386d6e 437 clocks = <&apb0_gates 5>;
e10911e1 438 gpio-controller;
39138bc6 439 interrupt-controller;
7d4ff96d 440 #interrupt-cells = <2>;
9e2dcb2f 441 #size-cells = <0>;
e10911e1 442 #gpio-cells = <3>;
4348cc64
MR		 443
444 uart1_pins_a: uart1@0 {
445 allwinner,pins = "PE10", "PE11";
446 allwinner,function = "uart1";
092a0c3b
MR		 447 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
448 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
4348cc64
MR		 449 };
450
451 uart1_pins_b: uart1@1 {
452 allwinner,pins = "PG3", "PG4";
453 allwinner,function = "uart1";
092a0c3b
MR		 454 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
455 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
4348cc64 456 };
b4d7c230
MR		 457
458 i2c0_pins_a: i2c0@0 {
459 allwinner,pins = "PB0", "PB1";
460 allwinner,function = "i2c0";
092a0c3b
MR		 461 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
462 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
b4d7c230
MR		 463 };
464
465 i2c1_pins_a: i2c1@0 {
466 allwinner,pins = "PB15", "PB16";
467 allwinner,function = "i2c1";
092a0c3b
MR		 468 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
469 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
b4d7c230
MR		 470 };
471
472 i2c2_pins_a: i2c2@0 {
473 allwinner,pins = "PB17", "PB18";
474 allwinner,function = "i2c2";
092a0c3b
MR		 475 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
476 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
b4d7c230 477 };
6da50f13
HG		 478
479 mmc0_pins_a: mmc0@0 {
480 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
481 allwinner,function = "mmc0";
092a0c3b
MR		 482 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
483 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
6da50f13 484 };
9e2dcb2f 485 };
69144e3b
MR		 486
487 timer@01c20c00 {
b4f26440 488 compatible = "allwinner,sun4i-a10-timer";
69144e3b
MR		 489 reg = <0x01c20c00 0x90>;
490 interrupts = <22>;
491 clocks = <&osc24M>;
492 };
493
494 wdt: watchdog@01c20c90 {
ca5d04d9 495 compatible = "allwinner,sun4i-a10-wdt";
69144e3b
MR		 496 reg = <0x01c20c90 0x10>;
497 };
498
ec011af5
HG		 499 lradc: lradc@01c22800 {
500 compatible = "allwinner,sun4i-a10-lradc-keys";
501 reg = <0x01c22800 0x100>;
502 interrupts = <31>;
503 status = "disabled";
504 };
505
2bad969f 506 sid: eeprom@01c23800 {
043d56ee 507 compatible = "allwinner,sun4i-a10-sid";
2bad969f
OS		 508 reg = <0x01c23800 0x10>;
509 };
510
f65c93a0 511 rtp: rtp@01c25000 {
40dd8f3b 512 compatible = "allwinner,sun4i-a10-ts";
f65c93a0
HG		 513 reg = <0x01c25000 0x100>;
514 interrupts = <29>;
41e7afb1 515 #thermal-sensor-cells = <0>;
f65c93a0
HG		 516 };
517
69144e3b
MR		 518 uart1: serial@01c28400 {
519 compatible = "snps,dw-apb-uart";
520 reg = <0x01c28400 0x400>;
521 interrupts = <2>;
522 reg-shift = <2>;
523 reg-io-width = <4>;
524 clocks = <&apb1_gates 17>;
525 status = "disabled";
526 };
527
528 uart3: serial@01c28c00 {
529 compatible = "snps,dw-apb-uart";
530 reg = <0x01c28c00 0x400>;
531 interrupts = <4>;
532 reg-shift = <2>;
533 reg-io-width = <4>;
534 clocks = <&apb1_gates 19>;
535 status = "disabled";
536 };
f1741fda
MR		 537
538 i2c0: i2c@01c2ac00 {
d275545e 539 compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";
f1741fda
MR		 540 reg = <0x01c2ac00 0x400>;
541 interrupts = <7>;
542 clocks = <&apb1_gates 0>;
f1741fda 543 status = "disabled";
a470342e
HG		 544 #address-cells = <1>;
545 #size-cells = <0>;
f1741fda
MR		 546 };
547
548 i2c1: i2c@01c2b000 {
d275545e 549 compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";
f1741fda
MR		 550 reg = <0x01c2b000 0x400>;
551 interrupts = <8>;
552 clocks = <&apb1_gates 1>;
f1741fda 553 status = "disabled";
a470342e
HG		 554 #address-cells = <1>;
555 #size-cells = <0>;
f1741fda
MR		 556 };
557
558 i2c2: i2c@01c2b400 {
d275545e 559 compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";
f1741fda
MR		 560 reg = <0x01c2b400 0x400>;
561 interrupts = <9>;
562 clocks = <&apb1_gates 2>;
f1741fda 563 status = "disabled";
a470342e
HG		 564 #address-cells = <1>;
565 #size-cells = <0>;
f1741fda 566 };
4411902a
MR		 567
568 timer@01c60000 {
569 compatible = "allwinner,sun5i-a13-hstimer";
570 reg = <0x01c60000 0x1000>;
571 interrupts = <82>, <83>;
572 clocks = <&ahb_gates 28>;
573 };
9e2dcb2f 574 };
d4da2ebb 575};
Linux kernel - Deliverables
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