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fbfa7367 MR |
1 | /* |
2 | * Copyright 2012-2015 Maxime Ripard | |
3 | * | |
4 | * Maxime Ripard <maxime.ripard@free-electrons.com> | |
5 | * | |
6 | * This file is dual-licensed: you can use it either under the terms | |
7 | * of the GPL or the X11 license, at your option. Note that this dual | |
8 | * licensing only applies to this file, and not this project as a | |
9 | * whole. | |
10 | * | |
11 | * a) This library is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of the | |
14 | * License, or (at your option) any later version. | |
15 | * | |
16 | * This library is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
fbfa7367 MR |
21 | * Or, alternatively, |
22 | * | |
23 | * b) Permission is hereby granted, free of charge, to any person | |
24 | * obtaining a copy of this software and associated documentation | |
25 | * files (the "Software"), to deal in the Software without | |
26 | * restriction, including without limitation the rights to use, | |
27 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
28 | * sell copies of the Software, and to permit persons to whom the | |
29 | * Software is furnished to do so, subject to the following | |
30 | * conditions: | |
31 | * | |
32 | * The above copyright notice and this permission notice shall be | |
33 | * included in all copies or substantial portions of the Software. | |
34 | * | |
35 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
36 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
37 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
38 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
39 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
40 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
41 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
42 | * OTHER DEALINGS IN THE SOFTWARE. | |
43 | */ | |
44 | ||
45 | #include "skeleton.dtsi" | |
46 | ||
ca72f022 | 47 | #include <dt-bindings/clock/sun4i-a10-pll2.h> |
fbfa7367 MR |
48 | #include <dt-bindings/dma/sun4i-a10.h> |
49 | #include <dt-bindings/pinctrl/sun4i-a10.h> | |
50 | ||
51 | / { | |
52 | interrupt-parent = <&intc>; | |
53 | ||
54 | cpus { | |
55 | #address-cells = <1>; | |
56 | #size-cells = <0>; | |
57 | ||
58 | cpu0: cpu@0 { | |
59 | device_type = "cpu"; | |
60 | compatible = "arm,cortex-a8"; | |
61 | reg = <0x0>; | |
62 | clocks = <&cpu>; | |
63 | }; | |
64 | }; | |
65 | ||
66 | clocks { | |
67 | #address-cells = <1>; | |
68 | #size-cells = <1>; | |
69 | ranges; | |
70 | ||
71 | /* | |
72 | * This is a dummy clock, to be used as placeholder on | |
73 | * other mux clocks when a specific parent clock is not | |
74 | * yet implemented. It should be dropped when the driver | |
75 | * is complete. | |
76 | */ | |
77 | dummy: dummy { | |
78 | #clock-cells = <0>; | |
79 | compatible = "fixed-clock"; | |
80 | clock-frequency = <0>; | |
81 | }; | |
82 | ||
83 | osc24M: clk@01c20050 { | |
84 | #clock-cells = <0>; | |
85 | compatible = "allwinner,sun4i-a10-osc-clk"; | |
86 | reg = <0x01c20050 0x4>; | |
87 | clock-frequency = <24000000>; | |
88 | clock-output-names = "osc24M"; | |
89 | }; | |
90 | ||
91 | osc32k: clk@0 { | |
92 | #clock-cells = <0>; | |
93 | compatible = "fixed-clock"; | |
94 | clock-frequency = <32768>; | |
95 | clock-output-names = "osc32k"; | |
96 | }; | |
97 | ||
98 | pll1: clk@01c20000 { | |
99 | #clock-cells = <0>; | |
100 | compatible = "allwinner,sun4i-a10-pll1-clk"; | |
101 | reg = <0x01c20000 0x4>; | |
102 | clocks = <&osc24M>; | |
103 | clock-output-names = "pll1"; | |
104 | }; | |
105 | ||
6f87abb8 MR |
106 | pll2: clk@01c20008 { |
107 | #clock-cells = <1>; | |
108 | compatible = "allwinner,sun5i-a13-pll2-clk"; | |
109 | reg = <0x01c20008 0x8>; | |
110 | clocks = <&osc24M>; | |
111 | clock-output-names = "pll2-1x", "pll2-2x", | |
112 | "pll2-4x", "pll2-8x"; | |
113 | }; | |
114 | ||
fbfa7367 MR |
115 | pll4: clk@01c20018 { |
116 | #clock-cells = <0>; | |
117 | compatible = "allwinner,sun4i-a10-pll1-clk"; | |
118 | reg = <0x01c20018 0x4>; | |
119 | clocks = <&osc24M>; | |
120 | clock-output-names = "pll4"; | |
121 | }; | |
122 | ||
123 | pll5: clk@01c20020 { | |
124 | #clock-cells = <1>; | |
125 | compatible = "allwinner,sun4i-a10-pll5-clk"; | |
126 | reg = <0x01c20020 0x4>; | |
127 | clocks = <&osc24M>; | |
128 | clock-output-names = "pll5_ddr", "pll5_other"; | |
129 | }; | |
130 | ||
131 | pll6: clk@01c20028 { | |
132 | #clock-cells = <1>; | |
133 | compatible = "allwinner,sun4i-a10-pll6-clk"; | |
134 | reg = <0x01c20028 0x4>; | |
135 | clocks = <&osc24M>; | |
136 | clock-output-names = "pll6_sata", "pll6_other", "pll6"; | |
137 | }; | |
138 | ||
139 | /* dummy is 200M */ | |
140 | cpu: cpu@01c20054 { | |
141 | #clock-cells = <0>; | |
142 | compatible = "allwinner,sun4i-a10-cpu-clk"; | |
143 | reg = <0x01c20054 0x4>; | |
144 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; | |
145 | clock-output-names = "cpu"; | |
146 | }; | |
147 | ||
148 | axi: axi@01c20054 { | |
149 | #clock-cells = <0>; | |
150 | compatible = "allwinner,sun4i-a10-axi-clk"; | |
151 | reg = <0x01c20054 0x4>; | |
152 | clocks = <&cpu>; | |
153 | clock-output-names = "axi"; | |
154 | }; | |
155 | ||
156 | ahb: ahb@01c20054 { | |
157 | #clock-cells = <0>; | |
2186df37 | 158 | compatible = "allwinner,sun5i-a13-ahb-clk"; |
fbfa7367 | 159 | reg = <0x01c20054 0x4>; |
2186df37 | 160 | clocks = <&axi>, <&cpu>, <&pll6 1>; |
fbfa7367 | 161 | clock-output-names = "ahb"; |
2186df37 CYT |
162 | /* |
163 | * Use PLL6 as parent, instead of CPU/AXI | |
164 | * which has rate changes due to cpufreq | |
165 | */ | |
166 | assigned-clocks = <&ahb>; | |
167 | assigned-clock-parents = <&pll6 1>; | |
fbfa7367 MR |
168 | }; |
169 | ||
170 | apb0: apb0@01c20054 { | |
171 | #clock-cells = <0>; | |
172 | compatible = "allwinner,sun4i-a10-apb0-clk"; | |
173 | reg = <0x01c20054 0x4>; | |
174 | clocks = <&ahb>; | |
175 | clock-output-names = "apb0"; | |
176 | }; | |
177 | ||
178 | apb1: clk@01c20058 { | |
179 | #clock-cells = <0>; | |
180 | compatible = "allwinner,sun4i-a10-apb1-clk"; | |
181 | reg = <0x01c20058 0x4>; | |
182 | clocks = <&osc24M>, <&pll6 1>, <&osc32k>; | |
183 | clock-output-names = "apb1"; | |
184 | }; | |
185 | ||
186 | axi_gates: clk@01c2005c { | |
187 | #clock-cells = <1>; | |
188 | compatible = "allwinner,sun4i-a10-axi-gates-clk"; | |
189 | reg = <0x01c2005c 0x4>; | |
190 | clocks = <&axi>; | |
dd4de433 | 191 | clock-indices = <0>; |
fbfa7367 MR |
192 | clock-output-names = "axi_dram"; |
193 | }; | |
194 | ||
195 | nand_clk: clk@01c20080 { | |
196 | #clock-cells = <0>; | |
197 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
198 | reg = <0x01c20080 0x4>; | |
199 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
200 | clock-output-names = "nand"; | |
201 | }; | |
202 | ||
203 | ms_clk: clk@01c20084 { | |
204 | #clock-cells = <0>; | |
205 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
206 | reg = <0x01c20084 0x4>; | |
207 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
208 | clock-output-names = "ms"; | |
209 | }; | |
210 | ||
211 | mmc0_clk: clk@01c20088 { | |
212 | #clock-cells = <1>; | |
213 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
214 | reg = <0x01c20088 0x4>; | |
215 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
216 | clock-output-names = "mmc0", | |
217 | "mmc0_output", | |
218 | "mmc0_sample"; | |
219 | }; | |
220 | ||
221 | mmc1_clk: clk@01c2008c { | |
222 | #clock-cells = <1>; | |
223 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
224 | reg = <0x01c2008c 0x4>; | |
225 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
226 | clock-output-names = "mmc1", | |
227 | "mmc1_output", | |
228 | "mmc1_sample"; | |
229 | }; | |
230 | ||
231 | mmc2_clk: clk@01c20090 { | |
232 | #clock-cells = <1>; | |
233 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
234 | reg = <0x01c20090 0x4>; | |
235 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
236 | clock-output-names = "mmc2", | |
237 | "mmc2_output", | |
238 | "mmc2_sample"; | |
239 | }; | |
240 | ||
241 | ts_clk: clk@01c20098 { | |
242 | #clock-cells = <0>; | |
243 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
244 | reg = <0x01c20098 0x4>; | |
245 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
246 | clock-output-names = "ts"; | |
247 | }; | |
248 | ||
249 | ss_clk: clk@01c2009c { | |
250 | #clock-cells = <0>; | |
251 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
252 | reg = <0x01c2009c 0x4>; | |
253 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
254 | clock-output-names = "ss"; | |
255 | }; | |
256 | ||
257 | spi0_clk: clk@01c200a0 { | |
258 | #clock-cells = <0>; | |
259 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
260 | reg = <0x01c200a0 0x4>; | |
261 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
262 | clock-output-names = "spi0"; | |
263 | }; | |
264 | ||
265 | spi1_clk: clk@01c200a4 { | |
266 | #clock-cells = <0>; | |
267 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
268 | reg = <0x01c200a4 0x4>; | |
269 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
270 | clock-output-names = "spi1"; | |
271 | }; | |
272 | ||
273 | spi2_clk: clk@01c200a8 { | |
274 | #clock-cells = <0>; | |
275 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
276 | reg = <0x01c200a8 0x4>; | |
277 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
278 | clock-output-names = "spi2"; | |
279 | }; | |
280 | ||
281 | ir0_clk: clk@01c200b0 { | |
282 | #clock-cells = <0>; | |
283 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
284 | reg = <0x01c200b0 0x4>; | |
285 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
286 | clock-output-names = "ir0"; | |
287 | }; | |
288 | ||
289 | usb_clk: clk@01c200cc { | |
290 | #clock-cells = <1>; | |
8358aada | 291 | #reset-cells = <1>; |
fbfa7367 MR |
292 | compatible = "allwinner,sun5i-a13-usb-clk"; |
293 | reg = <0x01c200cc 0x4>; | |
294 | clocks = <&pll6 1>; | |
295 | clock-output-names = "usb_ohci0", "usb_phy"; | |
296 | }; | |
297 | ||
ca72f022 MR |
298 | codec_clk: clk@01c20140 { |
299 | #clock-cells = <0>; | |
300 | compatible = "allwinner,sun4i-a10-codec-clk"; | |
301 | reg = <0x01c20140 0x4>; | |
302 | clocks = <&pll2 SUN4I_A10_PLL2_1X>; | |
303 | clock-output-names = "codec"; | |
304 | }; | |
305 | ||
fbfa7367 MR |
306 | mbus_clk: clk@01c2015c { |
307 | #clock-cells = <0>; | |
308 | compatible = "allwinner,sun5i-a13-mbus-clk"; | |
309 | reg = <0x01c2015c 0x4>; | |
310 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
311 | clock-output-names = "mbus"; | |
312 | }; | |
313 | }; | |
314 | ||
315 | soc@01c00000 { | |
316 | compatible = "simple-bus"; | |
317 | #address-cells = <1>; | |
318 | #size-cells = <1>; | |
319 | ranges; | |
320 | ||
00f69ba9 MR |
321 | sram-controller@01c00000 { |
322 | compatible = "allwinner,sun4i-a10-sram-controller"; | |
323 | reg = <0x01c00000 0x30>; | |
324 | #address-cells = <1>; | |
325 | #size-cells = <1>; | |
326 | ranges; | |
327 | ||
328 | sram_a: sram@00000000 { | |
329 | compatible = "mmio-sram"; | |
330 | reg = <0x00000000 0xc000>; | |
331 | #address-cells = <1>; | |
332 | #size-cells = <1>; | |
333 | ranges = <0 0x00000000 0xc000>; | |
334 | }; | |
335 | ||
336 | sram_d: sram@00010000 { | |
337 | compatible = "mmio-sram"; | |
338 | reg = <0x00010000 0x1000>; | |
339 | #address-cells = <1>; | |
340 | #size-cells = <1>; | |
341 | ranges = <0 0x00010000 0x1000>; | |
342 | ||
343 | otg_sram: sram-section@0000 { | |
344 | compatible = "allwinner,sun4i-a10-sram-d"; | |
345 | reg = <0x0000 0x1000>; | |
346 | status = "disabled"; | |
347 | }; | |
348 | }; | |
349 | }; | |
350 | ||
fbfa7367 MR |
351 | dma: dma-controller@01c02000 { |
352 | compatible = "allwinner,sun4i-a10-dma"; | |
353 | reg = <0x01c02000 0x1000>; | |
354 | interrupts = <27>; | |
355 | clocks = <&ahb_gates 6>; | |
356 | #dma-cells = <2>; | |
357 | }; | |
358 | ||
359 | spi0: spi@01c05000 { | |
360 | compatible = "allwinner,sun4i-a10-spi"; | |
361 | reg = <0x01c05000 0x1000>; | |
362 | interrupts = <10>; | |
363 | clocks = <&ahb_gates 20>, <&spi0_clk>; | |
364 | clock-names = "ahb", "mod"; | |
365 | dmas = <&dma SUN4I_DMA_DEDICATED 27>, | |
366 | <&dma SUN4I_DMA_DEDICATED 26>; | |
367 | dma-names = "rx", "tx"; | |
368 | status = "disabled"; | |
369 | #address-cells = <1>; | |
370 | #size-cells = <0>; | |
371 | }; | |
372 | ||
373 | spi1: spi@01c06000 { | |
374 | compatible = "allwinner,sun4i-a10-spi"; | |
375 | reg = <0x01c06000 0x1000>; | |
376 | interrupts = <11>; | |
377 | clocks = <&ahb_gates 21>, <&spi1_clk>; | |
378 | clock-names = "ahb", "mod"; | |
379 | dmas = <&dma SUN4I_DMA_DEDICATED 9>, | |
380 | <&dma SUN4I_DMA_DEDICATED 8>; | |
381 | dma-names = "rx", "tx"; | |
382 | status = "disabled"; | |
383 | #address-cells = <1>; | |
384 | #size-cells = <0>; | |
385 | }; | |
386 | ||
387 | mmc0: mmc@01c0f000 { | |
388 | compatible = "allwinner,sun5i-a13-mmc"; | |
389 | reg = <0x01c0f000 0x1000>; | |
390 | clocks = <&ahb_gates 8>, | |
391 | <&mmc0_clk 0>, | |
392 | <&mmc0_clk 1>, | |
393 | <&mmc0_clk 2>; | |
394 | clock-names = "ahb", | |
395 | "mmc", | |
396 | "output", | |
397 | "sample"; | |
398 | interrupts = <32>; | |
399 | status = "disabled"; | |
4c1bb9c3 HG |
400 | #address-cells = <1>; |
401 | #size-cells = <0>; | |
fbfa7367 MR |
402 | }; |
403 | ||
404 | mmc1: mmc@01c10000 { | |
405 | compatible = "allwinner,sun5i-a13-mmc"; | |
406 | reg = <0x01c10000 0x1000>; | |
407 | clocks = <&ahb_gates 9>, | |
408 | <&mmc1_clk 0>, | |
409 | <&mmc1_clk 1>, | |
410 | <&mmc1_clk 2>; | |
411 | clock-names = "ahb", | |
412 | "mmc", | |
413 | "output", | |
414 | "sample"; | |
415 | interrupts = <33>; | |
416 | status = "disabled"; | |
4c1bb9c3 HG |
417 | #address-cells = <1>; |
418 | #size-cells = <0>; | |
fbfa7367 MR |
419 | }; |
420 | ||
421 | mmc2: mmc@01c11000 { | |
422 | compatible = "allwinner,sun5i-a13-mmc"; | |
423 | reg = <0x01c11000 0x1000>; | |
424 | clocks = <&ahb_gates 10>, | |
425 | <&mmc2_clk 0>, | |
426 | <&mmc2_clk 1>, | |
427 | <&mmc2_clk 2>; | |
428 | clock-names = "ahb", | |
429 | "mmc", | |
430 | "output", | |
431 | "sample"; | |
432 | interrupts = <34>; | |
433 | status = "disabled"; | |
4c1bb9c3 HG |
434 | #address-cells = <1>; |
435 | #size-cells = <0>; | |
fbfa7367 MR |
436 | }; |
437 | ||
482f178c HG |
438 | usb_otg: usb@01c13000 { |
439 | compatible = "allwinner,sun4i-a10-musb"; | |
440 | reg = <0x01c13000 0x0400>; | |
441 | clocks = <&ahb_gates 0>; | |
442 | interrupts = <38>; | |
443 | interrupt-names = "mc"; | |
444 | phys = <&usbphy 0>; | |
445 | phy-names = "usb"; | |
446 | extcon = <&usbphy 0>; | |
447 | allwinner,sram = <&otg_sram 1>; | |
448 | status = "disabled"; | |
449 | }; | |
450 | ||
fbfa7367 MR |
451 | usbphy: phy@01c13400 { |
452 | #phy-cells = <1>; | |
453 | compatible = "allwinner,sun5i-a13-usb-phy"; | |
454 | reg = <0x01c13400 0x10 0x01c14800 0x4>; | |
455 | reg-names = "phy_ctrl", "pmu1"; | |
456 | clocks = <&usb_clk 8>; | |
457 | clock-names = "usb_phy"; | |
458 | resets = <&usb_clk 0>, <&usb_clk 1>; | |
459 | reset-names = "usb0_reset", "usb1_reset"; | |
460 | status = "disabled"; | |
461 | }; | |
462 | ||
463 | ehci0: usb@01c14000 { | |
3727ed3b | 464 | compatible = "allwinner,sun5i-a13-ehci", "generic-ehci"; |
fbfa7367 MR |
465 | reg = <0x01c14000 0x100>; |
466 | interrupts = <39>; | |
467 | clocks = <&ahb_gates 1>; | |
468 | phys = <&usbphy 1>; | |
469 | phy-names = "usb"; | |
470 | status = "disabled"; | |
471 | }; | |
472 | ||
473 | ohci0: usb@01c14400 { | |
3727ed3b | 474 | compatible = "allwinner,sun5i-a13-ohci", "generic-ohci"; |
fbfa7367 MR |
475 | reg = <0x01c14400 0x100>; |
476 | interrupts = <40>; | |
477 | clocks = <&usb_clk 6>, <&ahb_gates 2>; | |
478 | phys = <&usbphy 1>; | |
479 | phy-names = "usb"; | |
480 | status = "disabled"; | |
481 | }; | |
482 | ||
483 | spi2: spi@01c17000 { | |
484 | compatible = "allwinner,sun4i-a10-spi"; | |
485 | reg = <0x01c17000 0x1000>; | |
486 | interrupts = <12>; | |
487 | clocks = <&ahb_gates 22>, <&spi2_clk>; | |
488 | clock-names = "ahb", "mod"; | |
489 | dmas = <&dma SUN4I_DMA_DEDICATED 29>, | |
490 | <&dma SUN4I_DMA_DEDICATED 28>; | |
491 | dma-names = "rx", "tx"; | |
492 | status = "disabled"; | |
493 | #address-cells = <1>; | |
494 | #size-cells = <0>; | |
495 | }; | |
496 | ||
497 | intc: interrupt-controller@01c20400 { | |
498 | compatible = "allwinner,sun4i-a10-ic"; | |
499 | reg = <0x01c20400 0x400>; | |
500 | interrupt-controller; | |
501 | #interrupt-cells = <1>; | |
502 | }; | |
503 | ||
504 | pio: pinctrl@01c20800 { | |
505 | reg = <0x01c20800 0x400>; | |
506 | interrupts = <28>; | |
507 | clocks = <&apb0_gates 5>; | |
508 | gpio-controller; | |
509 | interrupt-controller; | |
b03e0816 | 510 | #interrupt-cells = <3>; |
fbfa7367 | 511 | #gpio-cells = <3>; |
51fbba42 MR |
512 | |
513 | i2c0_pins_a: i2c0@0 { | |
514 | allwinner,pins = "PB0", "PB1"; | |
515 | allwinner,function = "i2c0"; | |
516 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
517 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
518 | }; | |
519 | ||
520 | i2c1_pins_a: i2c1@0 { | |
521 | allwinner,pins = "PB15", "PB16"; | |
522 | allwinner,function = "i2c1"; | |
523 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
524 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
525 | }; | |
526 | ||
527 | i2c2_pins_a: i2c2@0 { | |
528 | allwinner,pins = "PB17", "PB18"; | |
529 | allwinner,function = "i2c2"; | |
530 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
531 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
532 | }; | |
533 | ||
534 | mmc0_pins_a: mmc0@0 { | |
d8cacaa3 MR |
535 | allwinner,pins = "PF0", "PF1", "PF2", "PF3", |
536 | "PF4", "PF5"; | |
51fbba42 MR |
537 | allwinner,function = "mmc0"; |
538 | allwinner,drive = <SUN4I_PINCTRL_30_MA>; | |
539 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
540 | }; | |
e1fe9f8c HG |
541 | |
542 | mmc2_pins_a: mmc2@0 { | |
543 | allwinner,pins = "PC6", "PC7", "PC8", "PC9", | |
544 | "PC10", "PC11", "PC12", "PC13", | |
545 | "PC14", "PC15"; | |
546 | allwinner,function = "mmc2"; | |
547 | allwinner,drive = <SUN4I_PINCTRL_30_MA>; | |
548 | allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; | |
549 | }; | |
6ef8c8bf MR |
550 | |
551 | uart3_pins_a: uart3@0 { | |
552 | allwinner,pins = "PG9", "PG10"; | |
553 | allwinner,function = "uart3"; | |
eeea0fa3 MR |
554 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
555 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
556 | }; | |
557 | ||
558 | uart3_pins_cts_rts_a: uart3-cts-rts@0 { | |
559 | allwinner,pins = "PG11", "PG12"; | |
560 | allwinner,function = "uart3"; | |
6ef8c8bf MR |
561 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
562 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
563 | }; | |
bb390193 HG |
564 | |
565 | pwm0_pins: pwm0 { | |
566 | allwinner,pins = "PB2"; | |
567 | allwinner,function = "pwm"; | |
568 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
569 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
570 | }; | |
fbfa7367 MR |
571 | }; |
572 | ||
573 | timer@01c20c00 { | |
574 | compatible = "allwinner,sun4i-a10-timer"; | |
575 | reg = <0x01c20c00 0x90>; | |
576 | interrupts = <22>; | |
577 | clocks = <&osc24M>; | |
578 | }; | |
579 | ||
580 | wdt: watchdog@01c20c90 { | |
581 | compatible = "allwinner,sun4i-a10-wdt"; | |
582 | reg = <0x01c20c90 0x10>; | |
583 | }; | |
584 | ||
585 | lradc: lradc@01c22800 { | |
586 | compatible = "allwinner,sun4i-a10-lradc-keys"; | |
587 | reg = <0x01c22800 0x100>; | |
588 | interrupts = <31>; | |
589 | status = "disabled"; | |
590 | }; | |
591 | ||
44cdcfc2 MR |
592 | codec: codec@01c22c00 { |
593 | #sound-dai-cells = <0>; | |
594 | compatible = "allwinner,sun4i-a10-codec"; | |
595 | reg = <0x01c22c00 0x40>; | |
596 | interrupts = <30>; | |
597 | clocks = <&apb0_gates 0>, <&codec_clk>; | |
598 | clock-names = "apb", "codec"; | |
599 | dmas = <&dma SUN4I_DMA_NORMAL 19>, | |
600 | <&dma SUN4I_DMA_NORMAL 19>; | |
601 | dma-names = "rx", "tx"; | |
602 | status = "disabled"; | |
603 | }; | |
604 | ||
fbfa7367 MR |
605 | sid: eeprom@01c23800 { |
606 | compatible = "allwinner,sun4i-a10-sid"; | |
607 | reg = <0x01c23800 0x10>; | |
608 | }; | |
609 | ||
610 | rtp: rtp@01c25000 { | |
8bf1b9b3 | 611 | compatible = "allwinner,sun5i-a13-ts"; |
fbfa7367 MR |
612 | reg = <0x01c25000 0x100>; |
613 | interrupts = <29>; | |
614 | #thermal-sensor-cells = <0>; | |
615 | }; | |
616 | ||
617 | uart1: serial@01c28400 { | |
618 | compatible = "snps,dw-apb-uart"; | |
619 | reg = <0x01c28400 0x400>; | |
620 | interrupts = <2>; | |
621 | reg-shift = <2>; | |
622 | reg-io-width = <4>; | |
623 | clocks = <&apb1_gates 17>; | |
624 | status = "disabled"; | |
625 | }; | |
626 | ||
627 | uart3: serial@01c28c00 { | |
628 | compatible = "snps,dw-apb-uart"; | |
629 | reg = <0x01c28c00 0x400>; | |
630 | interrupts = <4>; | |
631 | reg-shift = <2>; | |
632 | reg-io-width = <4>; | |
633 | clocks = <&apb1_gates 19>; | |
634 | status = "disabled"; | |
635 | }; | |
636 | ||
637 | i2c0: i2c@01c2ac00 { | |
638 | compatible = "allwinner,sun4i-a10-i2c"; | |
639 | reg = <0x01c2ac00 0x400>; | |
640 | interrupts = <7>; | |
641 | clocks = <&apb1_gates 0>; | |
642 | status = "disabled"; | |
643 | #address-cells = <1>; | |
644 | #size-cells = <0>; | |
645 | }; | |
646 | ||
647 | i2c1: i2c@01c2b000 { | |
648 | compatible = "allwinner,sun4i-a10-i2c"; | |
649 | reg = <0x01c2b000 0x400>; | |
650 | interrupts = <8>; | |
651 | clocks = <&apb1_gates 1>; | |
652 | status = "disabled"; | |
653 | #address-cells = <1>; | |
654 | #size-cells = <0>; | |
655 | }; | |
656 | ||
657 | i2c2: i2c@01c2b400 { | |
658 | compatible = "allwinner,sun4i-a10-i2c"; | |
659 | reg = <0x01c2b400 0x400>; | |
660 | interrupts = <9>; | |
661 | clocks = <&apb1_gates 2>; | |
662 | status = "disabled"; | |
663 | #address-cells = <1>; | |
664 | #size-cells = <0>; | |
665 | }; | |
666 | ||
667 | timer@01c60000 { | |
668 | compatible = "allwinner,sun5i-a13-hstimer"; | |
669 | reg = <0x01c60000 0x1000>; | |
670 | interrupts = <82>, <83>; | |
671 | clocks = <&ahb_gates 28>; | |
672 | }; | |
673 | }; | |
674 | }; |