Commit | Line | Data |
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8aed3b31 MR |
1 | /* |
2 | * Copyright 2013 Maxime Ripard | |
3 | * | |
4 | * Maxime Ripard <maxime.ripard@free-electrons.com> | |
5 | * | |
6 | * The code contained herein is licensed under the GNU General Public | |
7 | * License. You may obtain a copy of the GNU General Public License | |
8 | * Version 2 or later at the following locations: | |
9 | * | |
10 | * http://www.opensource.org/licenses/gpl-license.html | |
11 | * http://www.gnu.org/copyleft/gpl.html | |
12 | */ | |
13 | ||
14 | /include/ "skeleton.dtsi" | |
15 | ||
16 | / { | |
17 | interrupt-parent = <&gic>; | |
18 | ||
54428d40 MR |
19 | aliases { |
20 | serial0 = &uart0; | |
21 | serial1 = &uart1; | |
22 | serial2 = &uart2; | |
23 | serial3 = &uart3; | |
24 | serial4 = &uart4; | |
25 | serial5 = &uart5; | |
e5073fde | 26 | ethernet0 = &gmac; |
54428d40 MR |
27 | }; |
28 | ||
29 | ||
8aed3b31 | 30 | cpus { |
ce78e353 | 31 | enable-method = "allwinner,sun6i-a31"; |
8aed3b31 MR |
32 | #address-cells = <1>; |
33 | #size-cells = <0>; | |
34 | ||
35 | cpu@0 { | |
36 | compatible = "arm,cortex-a7"; | |
37 | device_type = "cpu"; | |
38 | reg = <0>; | |
39 | }; | |
40 | ||
41 | cpu@1 { | |
42 | compatible = "arm,cortex-a7"; | |
43 | device_type = "cpu"; | |
44 | reg = <1>; | |
45 | }; | |
46 | ||
47 | cpu@2 { | |
48 | compatible = "arm,cortex-a7"; | |
49 | device_type = "cpu"; | |
50 | reg = <2>; | |
51 | }; | |
52 | ||
53 | cpu@3 { | |
54 | compatible = "arm,cortex-a7"; | |
55 | device_type = "cpu"; | |
56 | reg = <3>; | |
57 | }; | |
58 | }; | |
59 | ||
60 | memory { | |
61 | reg = <0x40000000 0x80000000>; | |
62 | }; | |
63 | ||
b5a10b76 MR |
64 | pmu { |
65 | compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu"; | |
66 | interrupts = <0 120 4>, | |
67 | <0 121 4>, | |
68 | <0 122 4>, | |
69 | <0 123 4>; | |
70 | }; | |
71 | ||
8aed3b31 MR |
72 | clocks { |
73 | #address-cells = <1>; | |
98096560 MR |
74 | #size-cells = <1>; |
75 | ranges; | |
8aed3b31 | 76 | |
98096560 | 77 | osc24M: osc24M { |
8aed3b31 MR |
78 | #clock-cells = <0>; |
79 | compatible = "fixed-clock"; | |
80 | clock-frequency = <24000000>; | |
81 | }; | |
98096560 | 82 | |
7b5b2909 | 83 | osc32k: clk@0 { |
98096560 MR |
84 | #clock-cells = <0>; |
85 | compatible = "fixed-clock"; | |
86 | clock-frequency = <32768>; | |
7b5b2909 | 87 | clock-output-names = "osc32k"; |
98096560 MR |
88 | }; |
89 | ||
7b5b2909 | 90 | pll1: clk@01c20000 { |
98096560 MR |
91 | #clock-cells = <0>; |
92 | compatible = "allwinner,sun6i-a31-pll1-clk"; | |
93 | reg = <0x01c20000 0x4>; | |
94 | clocks = <&osc24M>; | |
7b5b2909 | 95 | clock-output-names = "pll1"; |
98096560 MR |
96 | }; |
97 | ||
b0a09c75 | 98 | pll6: clk@01c20028 { |
98096560 | 99 | #clock-cells = <0>; |
b0a09c75 MR |
100 | compatible = "allwinner,sun6i-a31-pll6-clk"; |
101 | reg = <0x01c20028 0x4>; | |
102 | clocks = <&osc24M>; | |
103 | clock-output-names = "pll6"; | |
98096560 MR |
104 | }; |
105 | ||
106 | cpu: cpu@01c20050 { | |
107 | #clock-cells = <0>; | |
bf6534a1 | 108 | compatible = "allwinner,sun4i-a10-cpu-clk"; |
98096560 MR |
109 | reg = <0x01c20050 0x4>; |
110 | ||
111 | /* | |
112 | * PLL1 is listed twice here. | |
113 | * While it looks suspicious, it's actually documented | |
114 | * that way both in the datasheet and in the code from | |
115 | * Allwinner. | |
116 | */ | |
117 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; | |
7b5b2909 | 118 | clock-output-names = "cpu"; |
98096560 MR |
119 | }; |
120 | ||
121 | axi: axi@01c20050 { | |
122 | #clock-cells = <0>; | |
bf6534a1 | 123 | compatible = "allwinner,sun4i-a10-axi-clk"; |
98096560 MR |
124 | reg = <0x01c20050 0x4>; |
125 | clocks = <&cpu>; | |
7b5b2909 | 126 | clock-output-names = "axi"; |
98096560 MR |
127 | }; |
128 | ||
129 | ahb1_mux: ahb1_mux@01c20054 { | |
130 | #clock-cells = <0>; | |
131 | compatible = "allwinner,sun6i-a31-ahb1-mux-clk"; | |
132 | reg = <0x01c20054 0x4>; | |
133 | clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>; | |
7b5b2909 | 134 | clock-output-names = "ahb1_mux"; |
98096560 MR |
135 | }; |
136 | ||
137 | ahb1: ahb1@01c20054 { | |
138 | #clock-cells = <0>; | |
bf6534a1 | 139 | compatible = "allwinner,sun4i-a10-ahb-clk"; |
98096560 MR |
140 | reg = <0x01c20054 0x4>; |
141 | clocks = <&ahb1_mux>; | |
7b5b2909 | 142 | clock-output-names = "ahb1"; |
98096560 MR |
143 | }; |
144 | ||
7b5b2909 | 145 | ahb1_gates: clk@01c20060 { |
98096560 MR |
146 | #clock-cells = <1>; |
147 | compatible = "allwinner,sun6i-a31-ahb1-gates-clk"; | |
148 | reg = <0x01c20060 0x8>; | |
149 | clocks = <&ahb1>; | |
150 | clock-output-names = "ahb1_mipidsi", "ahb1_ss", | |
151 | "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1", | |
152 | "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1", | |
153 | "ahb1_nand0", "ahb1_sdram", | |
154 | "ahb1_gmac", "ahb1_ts", "ahb1_hstimer", | |
155 | "ahb1_spi0", "ahb1_spi1", "ahb1_spi2", | |
156 | "ahb1_spi3", "ahb1_otg", "ahb1_ehci0", | |
157 | "ahb1_ehci1", "ahb1_ohci0", | |
158 | "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve", | |
159 | "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi", | |
160 | "ahb1_hdmi", "ahb1_de0", "ahb1_de1", | |
161 | "ahb1_fe0", "ahb1_fe1", "ahb1_mp", | |
162 | "ahb1_gpu", "ahb1_deu0", "ahb1_deu1", | |
163 | "ahb1_drc0", "ahb1_drc1"; | |
164 | }; | |
165 | ||
166 | apb1: apb1@01c20054 { | |
167 | #clock-cells = <0>; | |
bf6534a1 | 168 | compatible = "allwinner,sun4i-a10-apb0-clk"; |
98096560 MR |
169 | reg = <0x01c20054 0x4>; |
170 | clocks = <&ahb1>; | |
7b5b2909 | 171 | clock-output-names = "apb1"; |
98096560 MR |
172 | }; |
173 | ||
7b5b2909 | 174 | apb1_gates: clk@01c20068 { |
98096560 MR |
175 | #clock-cells = <1>; |
176 | compatible = "allwinner,sun6i-a31-apb1-gates-clk"; | |
177 | reg = <0x01c20068 0x4>; | |
178 | clocks = <&apb1>; | |
179 | clock-output-names = "apb1_codec", "apb1_digital_mic", | |
180 | "apb1_pio", "apb1_daudio0", | |
181 | "apb1_daudio1"; | |
182 | }; | |
183 | ||
184 | apb2_mux: apb2_mux@01c20058 { | |
185 | #clock-cells = <0>; | |
bf6534a1 | 186 | compatible = "allwinner,sun4i-a10-apb1-mux-clk"; |
98096560 MR |
187 | reg = <0x01c20058 0x4>; |
188 | clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>; | |
7b5b2909 | 189 | clock-output-names = "apb2_mux"; |
98096560 MR |
190 | }; |
191 | ||
192 | apb2: apb2@01c20058 { | |
193 | #clock-cells = <0>; | |
194 | compatible = "allwinner,sun6i-a31-apb2-div-clk"; | |
195 | reg = <0x01c20058 0x4>; | |
196 | clocks = <&apb2_mux>; | |
7b5b2909 | 197 | clock-output-names = "apb2"; |
98096560 MR |
198 | }; |
199 | ||
7b5b2909 | 200 | apb2_gates: clk@01c2006c { |
98096560 MR |
201 | #clock-cells = <1>; |
202 | compatible = "allwinner,sun6i-a31-apb2-gates-clk"; | |
439d9f58 | 203 | reg = <0x01c2006c 0x4>; |
98096560 MR |
204 | clocks = <&apb2>; |
205 | clock-output-names = "apb2_i2c0", "apb2_i2c1", | |
206 | "apb2_i2c2", "apb2_i2c3", "apb2_uart0", | |
207 | "apb2_uart1", "apb2_uart2", "apb2_uart3", | |
208 | "apb2_uart4", "apb2_uart5"; | |
209 | }; | |
b0a09c75 | 210 | |
adc54c85 HG |
211 | mmc0_clk: clk@01c20088 { |
212 | #clock-cells = <0>; | |
213 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
214 | reg = <0x01c20088 0x4>; | |
215 | clocks = <&osc24M>, <&pll6>; | |
216 | clock-output-names = "mmc0"; | |
217 | }; | |
218 | ||
219 | mmc1_clk: clk@01c2008c { | |
220 | #clock-cells = <0>; | |
221 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
222 | reg = <0x01c2008c 0x4>; | |
223 | clocks = <&osc24M>, <&pll6>; | |
224 | clock-output-names = "mmc1"; | |
225 | }; | |
226 | ||
227 | mmc2_clk: clk@01c20090 { | |
228 | #clock-cells = <0>; | |
229 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
230 | reg = <0x01c20090 0x4>; | |
231 | clocks = <&osc24M>, <&pll6>; | |
232 | clock-output-names = "mmc2"; | |
233 | }; | |
234 | ||
235 | mmc3_clk: clk@01c20094 { | |
236 | #clock-cells = <0>; | |
237 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
238 | reg = <0x01c20094 0x4>; | |
239 | clocks = <&osc24M>, <&pll6>; | |
240 | clock-output-names = "mmc3"; | |
241 | }; | |
242 | ||
b0a09c75 MR |
243 | spi0_clk: clk@01c200a0 { |
244 | #clock-cells = <0>; | |
225b0216 | 245 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
b0a09c75 MR |
246 | reg = <0x01c200a0 0x4>; |
247 | clocks = <&osc24M>, <&pll6>; | |
248 | clock-output-names = "spi0"; | |
249 | }; | |
250 | ||
251 | spi1_clk: clk@01c200a4 { | |
252 | #clock-cells = <0>; | |
225b0216 | 253 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
b0a09c75 MR |
254 | reg = <0x01c200a4 0x4>; |
255 | clocks = <&osc24M>, <&pll6>; | |
256 | clock-output-names = "spi1"; | |
257 | }; | |
258 | ||
259 | spi2_clk: clk@01c200a8 { | |
260 | #clock-cells = <0>; | |
225b0216 | 261 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
b0a09c75 MR |
262 | reg = <0x01c200a8 0x4>; |
263 | clocks = <&osc24M>, <&pll6>; | |
264 | clock-output-names = "spi2"; | |
265 | }; | |
266 | ||
267 | spi3_clk: clk@01c200ac { | |
268 | #clock-cells = <0>; | |
225b0216 | 269 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
b0a09c75 MR |
270 | reg = <0x01c200ac 0x4>; |
271 | clocks = <&osc24M>, <&pll6>; | |
272 | clock-output-names = "spi3"; | |
273 | }; | |
94a1cd14 MR |
274 | |
275 | usb_clk: clk@01c200cc { | |
276 | #clock-cells = <1>; | |
277 | #reset-cells = <1>; | |
278 | compatible = "allwinner,sun6i-a31-usb-clk"; | |
279 | reg = <0x01c200cc 0x4>; | |
280 | clocks = <&osc24M>; | |
281 | clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2", | |
282 | "usb_ohci0", "usb_ohci1", | |
283 | "usb_ohci2"; | |
284 | }; | |
ed29861a CYT |
285 | |
286 | /* | |
287 | * The following two are dummy clocks, placeholders used in the gmac_tx | |
288 | * clock. The gmac driver will choose one parent depending on the PHY | |
289 | * interface mode, using clk_set_rate auto-reparenting. | |
290 | * The actual TX clock rate is not controlled by the gmac_tx clock. | |
291 | */ | |
292 | mii_phy_tx_clk: clk@1 { | |
293 | #clock-cells = <0>; | |
294 | compatible = "fixed-clock"; | |
295 | clock-frequency = <25000000>; | |
296 | clock-output-names = "mii_phy_tx"; | |
297 | }; | |
298 | ||
299 | gmac_int_tx_clk: clk@2 { | |
300 | #clock-cells = <0>; | |
301 | compatible = "fixed-clock"; | |
302 | clock-frequency = <125000000>; | |
303 | clock-output-names = "gmac_int_tx"; | |
304 | }; | |
305 | ||
306 | gmac_tx_clk: clk@01c200d0 { | |
307 | #clock-cells = <0>; | |
308 | compatible = "allwinner,sun7i-a20-gmac-clk"; | |
309 | reg = <0x01c200d0 0x4>; | |
310 | clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; | |
311 | clock-output-names = "gmac_tx"; | |
312 | }; | |
8aed3b31 MR |
313 | }; |
314 | ||
315 | soc@01c00000 { | |
316 | compatible = "simple-bus"; | |
317 | #address-cells = <1>; | |
318 | #size-cells = <1>; | |
319 | ranges; | |
320 | ||
d2d878c4 MR |
321 | dma: dma-controller@01c02000 { |
322 | compatible = "allwinner,sun6i-a31-dma"; | |
323 | reg = <0x01c02000 0x1000>; | |
324 | interrupts = <0 50 4>; | |
325 | clocks = <&ahb1_gates 6>; | |
326 | resets = <&ahb1_rst 6>; | |
327 | #dma-cells = <1>; | |
328 | }; | |
329 | ||
5b753f0e HG |
330 | mmc0: mmc@01c0f000 { |
331 | compatible = "allwinner,sun5i-a13-mmc"; | |
332 | reg = <0x01c0f000 0x1000>; | |
333 | clocks = <&ahb1_gates 8>, <&mmc0_clk>; | |
334 | clock-names = "ahb", "mmc"; | |
335 | resets = <&ahb1_rst 8>; | |
336 | reset-names = "ahb"; | |
337 | interrupts = <0 60 4>; | |
338 | status = "disabled"; | |
339 | }; | |
340 | ||
341 | mmc1: mmc@01c10000 { | |
342 | compatible = "allwinner,sun5i-a13-mmc"; | |
343 | reg = <0x01c10000 0x1000>; | |
344 | clocks = <&ahb1_gates 9>, <&mmc1_clk>; | |
345 | clock-names = "ahb", "mmc"; | |
346 | resets = <&ahb1_rst 9>; | |
347 | reset-names = "ahb"; | |
348 | interrupts = <0 61 4>; | |
349 | status = "disabled"; | |
350 | }; | |
351 | ||
352 | mmc2: mmc@01c11000 { | |
353 | compatible = "allwinner,sun5i-a13-mmc"; | |
354 | reg = <0x01c11000 0x1000>; | |
355 | clocks = <&ahb1_gates 10>, <&mmc2_clk>; | |
356 | clock-names = "ahb", "mmc"; | |
357 | resets = <&ahb1_rst 10>; | |
358 | reset-names = "ahb"; | |
359 | interrupts = <0 62 4>; | |
360 | status = "disabled"; | |
361 | }; | |
362 | ||
363 | mmc3: mmc@01c12000 { | |
364 | compatible = "allwinner,sun5i-a13-mmc"; | |
365 | reg = <0x01c12000 0x1000>; | |
366 | clocks = <&ahb1_gates 11>, <&mmc3_clk>; | |
367 | clock-names = "ahb", "mmc"; | |
368 | resets = <&ahb1_rst 11>; | |
369 | reset-names = "ahb"; | |
370 | interrupts = <0 63 4>; | |
371 | status = "disabled"; | |
372 | }; | |
373 | ||
ef964085 MR |
374 | usbphy: phy@01c19400 { |
375 | compatible = "allwinner,sun6i-a31-usb-phy"; | |
376 | reg = <0x01c19400 0x10>, | |
377 | <0x01c1a800 0x4>, | |
378 | <0x01c1b800 0x4>; | |
379 | reg-names = "phy_ctrl", | |
380 | "pmu1", | |
381 | "pmu2"; | |
382 | clocks = <&usb_clk 8>, | |
383 | <&usb_clk 9>, | |
384 | <&usb_clk 10>; | |
385 | clock-names = "usb0_phy", | |
386 | "usb1_phy", | |
387 | "usb2_phy"; | |
388 | resets = <&usb_clk 0>, | |
389 | <&usb_clk 1>, | |
390 | <&usb_clk 2>; | |
391 | reset-names = "usb0_reset", | |
392 | "usb1_reset", | |
393 | "usb2_reset"; | |
394 | status = "disabled"; | |
395 | #phy-cells = <1>; | |
396 | }; | |
397 | ||
398 | ehci0: usb@01c1a000 { | |
399 | compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; | |
400 | reg = <0x01c1a000 0x100>; | |
401 | interrupts = <0 72 4>; | |
402 | clocks = <&ahb1_gates 26>; | |
403 | resets = <&ahb1_rst 26>; | |
404 | phys = <&usbphy 1>; | |
405 | phy-names = "usb"; | |
406 | status = "disabled"; | |
407 | }; | |
408 | ||
409 | ohci0: usb@01c1a400 { | |
410 | compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; | |
411 | reg = <0x01c1a400 0x100>; | |
412 | interrupts = <0 73 4>; | |
413 | clocks = <&ahb1_gates 29>, <&usb_clk 16>; | |
414 | resets = <&ahb1_rst 29>; | |
415 | phys = <&usbphy 1>; | |
416 | phy-names = "usb"; | |
417 | status = "disabled"; | |
418 | }; | |
419 | ||
420 | ehci1: usb@01c1b000 { | |
421 | compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; | |
422 | reg = <0x01c1b000 0x100>; | |
423 | interrupts = <0 74 4>; | |
424 | clocks = <&ahb1_gates 27>; | |
425 | resets = <&ahb1_rst 27>; | |
426 | phys = <&usbphy 2>; | |
427 | phy-names = "usb"; | |
428 | status = "disabled"; | |
429 | }; | |
430 | ||
431 | ohci1: usb@01c1b400 { | |
432 | compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; | |
433 | reg = <0x01c1b400 0x100>; | |
434 | interrupts = <0 75 4>; | |
435 | clocks = <&ahb1_gates 30>, <&usb_clk 17>; | |
436 | resets = <&ahb1_rst 30>; | |
437 | phys = <&usbphy 2>; | |
438 | phy-names = "usb"; | |
439 | status = "disabled"; | |
440 | }; | |
441 | ||
b294ebbc | 442 | ohci2: usb@01c1c400 { |
ef964085 MR |
443 | compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; |
444 | reg = <0x01c1c400 0x100>; | |
445 | interrupts = <0 77 4>; | |
446 | clocks = <&ahb1_gates 31>, <&usb_clk 18>; | |
447 | resets = <&ahb1_rst 31>; | |
448 | status = "disabled"; | |
449 | }; | |
450 | ||
140e1721 MR |
451 | pio: pinctrl@01c20800 { |
452 | compatible = "allwinner,sun6i-a31-pinctrl"; | |
453 | reg = <0x01c20800 0x400>; | |
6f97dc8d MR |
454 | interrupts = <0 11 4>, |
455 | <0 15 4>, | |
456 | <0 16 4>, | |
457 | <0 17 4>; | |
98096560 | 458 | clocks = <&apb1_gates 5>; |
140e1721 MR |
459 | gpio-controller; |
460 | interrupt-controller; | |
7d4ff96d | 461 | #interrupt-cells = <2>; |
140e1721 MR |
462 | #size-cells = <0>; |
463 | #gpio-cells = <3>; | |
ab4238cd MR |
464 | |
465 | uart0_pins_a: uart0@0 { | |
466 | allwinner,pins = "PH20", "PH21"; | |
467 | allwinner,function = "uart0"; | |
468 | allwinner,drive = <0>; | |
469 | allwinner,pull = <0>; | |
470 | }; | |
8be188b8 MR |
471 | |
472 | i2c0_pins_a: i2c0@0 { | |
473 | allwinner,pins = "PH14", "PH15"; | |
474 | allwinner,function = "i2c0"; | |
475 | allwinner,drive = <0>; | |
476 | allwinner,pull = <0>; | |
477 | }; | |
478 | ||
479 | i2c1_pins_a: i2c1@0 { | |
480 | allwinner,pins = "PH16", "PH17"; | |
481 | allwinner,function = "i2c1"; | |
482 | allwinner,drive = <0>; | |
483 | allwinner,pull = <0>; | |
484 | }; | |
485 | ||
486 | i2c2_pins_a: i2c2@0 { | |
487 | allwinner,pins = "PH18", "PH19"; | |
488 | allwinner,function = "i2c2"; | |
489 | allwinner,drive = <0>; | |
490 | allwinner,pull = <0>; | |
491 | }; | |
9797eb83 HG |
492 | |
493 | mmc0_pins_a: mmc0@0 { | |
494 | allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; | |
495 | allwinner,function = "mmc0"; | |
496 | allwinner,drive = <2>; | |
497 | allwinner,pull = <0>; | |
498 | }; | |
ee39a3e3 CYT |
499 | |
500 | gmac_pins_mii_a: gmac_mii@0 { | |
501 | allwinner,pins = "PA0", "PA1", "PA2", "PA3", | |
502 | "PA8", "PA9", "PA11", | |
503 | "PA12", "PA13", "PA14", "PA19", | |
504 | "PA20", "PA21", "PA22", "PA23", | |
505 | "PA24", "PA26", "PA27"; | |
506 | allwinner,function = "gmac"; | |
507 | allwinner,drive = <0>; | |
508 | allwinner,pull = <0>; | |
509 | }; | |
510 | ||
511 | gmac_pins_gmii_a: gmac_gmii@0 { | |
512 | allwinner,pins = "PA0", "PA1", "PA2", "PA3", | |
513 | "PA4", "PA5", "PA6", "PA7", | |
514 | "PA8", "PA9", "PA10", "PA11", | |
515 | "PA12", "PA13", "PA14", "PA15", | |
516 | "PA16", "PA17", "PA18", "PA19", | |
517 | "PA20", "PA21", "PA22", "PA23", | |
518 | "PA24", "PA25", "PA26", "PA27"; | |
519 | allwinner,function = "gmac"; | |
520 | /* | |
521 | * data lines in GMII mode run at 125MHz and | |
522 | * might need a higher signal drive strength | |
523 | */ | |
524 | allwinner,drive = <2>; | |
525 | allwinner,pull = <0>; | |
526 | }; | |
527 | ||
528 | gmac_pins_rgmii_a: gmac_rgmii@0 { | |
529 | allwinner,pins = "PA0", "PA1", "PA2", "PA3", | |
530 | "PA9", "PA10", "PA11", | |
531 | "PA12", "PA13", "PA14", "PA19", | |
532 | "PA20", "PA25", "PA26", "PA27"; | |
533 | allwinner,function = "gmac"; | |
534 | /* | |
535 | * data lines in RGMII mode use DDR mode | |
536 | * and need a higher signal drive strength | |
537 | */ | |
538 | allwinner,drive = <3>; | |
539 | allwinner,pull = <0>; | |
540 | }; | |
140e1721 MR |
541 | }; |
542 | ||
24a661e9 MR |
543 | ahb1_rst: reset@01c202c0 { |
544 | #reset-cells = <1>; | |
545 | compatible = "allwinner,sun6i-a31-ahb1-reset"; | |
546 | reg = <0x01c202c0 0xc>; | |
547 | }; | |
548 | ||
549 | apb1_rst: reset@01c202d0 { | |
550 | #reset-cells = <1>; | |
551 | compatible = "allwinner,sun6i-a31-clock-reset"; | |
552 | reg = <0x01c202d0 0x4>; | |
553 | }; | |
554 | ||
555 | apb2_rst: reset@01c202d8 { | |
556 | #reset-cells = <1>; | |
557 | compatible = "allwinner,sun6i-a31-clock-reset"; | |
558 | reg = <0x01c202d8 0x4>; | |
559 | }; | |
560 | ||
8aed3b31 | 561 | timer@01c20c00 { |
b4f26440 | 562 | compatible = "allwinner,sun4i-a10-timer"; |
8aed3b31 | 563 | reg = <0x01c20c00 0xa0>; |
6f97dc8d MR |
564 | interrupts = <0 18 4>, |
565 | <0 19 4>, | |
566 | <0 20 4>, | |
567 | <0 21 4>, | |
568 | <0 22 4>; | |
98096560 | 569 | clocks = <&osc24M>; |
8aed3b31 MR |
570 | }; |
571 | ||
572 | wdt1: watchdog@01c20ca0 { | |
ca5d04d9 | 573 | compatible = "allwinner,sun6i-a31-wdt"; |
8aed3b31 MR |
574 | reg = <0x01c20ca0 0x20>; |
575 | }; | |
576 | ||
577 | uart0: serial@01c28000 { | |
578 | compatible = "snps,dw-apb-uart"; | |
579 | reg = <0x01c28000 0x400>; | |
6f97dc8d | 580 | interrupts = <0 0 4>; |
8aed3b31 MR |
581 | reg-shift = <2>; |
582 | reg-io-width = <4>; | |
98096560 | 583 | clocks = <&apb2_gates 16>; |
24a661e9 | 584 | resets = <&apb2_rst 16>; |
d2d878c4 MR |
585 | dmas = <&dma 6>, <&dma 6>; |
586 | dma-names = "rx", "tx"; | |
8aed3b31 MR |
587 | status = "disabled"; |
588 | }; | |
589 | ||
590 | uart1: serial@01c28400 { | |
591 | compatible = "snps,dw-apb-uart"; | |
592 | reg = <0x01c28400 0x400>; | |
6f97dc8d | 593 | interrupts = <0 1 4>; |
8aed3b31 MR |
594 | reg-shift = <2>; |
595 | reg-io-width = <4>; | |
98096560 | 596 | clocks = <&apb2_gates 17>; |
24a661e9 | 597 | resets = <&apb2_rst 17>; |
d2d878c4 MR |
598 | dmas = <&dma 7>, <&dma 7>; |
599 | dma-names = "rx", "tx"; | |
8aed3b31 MR |
600 | status = "disabled"; |
601 | }; | |
602 | ||
603 | uart2: serial@01c28800 { | |
604 | compatible = "snps,dw-apb-uart"; | |
605 | reg = <0x01c28800 0x400>; | |
6f97dc8d | 606 | interrupts = <0 2 4>; |
8aed3b31 MR |
607 | reg-shift = <2>; |
608 | reg-io-width = <4>; | |
98096560 | 609 | clocks = <&apb2_gates 18>; |
24a661e9 | 610 | resets = <&apb2_rst 18>; |
d2d878c4 MR |
611 | dmas = <&dma 8>, <&dma 8>; |
612 | dma-names = "rx", "tx"; | |
8aed3b31 MR |
613 | status = "disabled"; |
614 | }; | |
615 | ||
616 | uart3: serial@01c28c00 { | |
617 | compatible = "snps,dw-apb-uart"; | |
618 | reg = <0x01c28c00 0x400>; | |
6f97dc8d | 619 | interrupts = <0 3 4>; |
8aed3b31 MR |
620 | reg-shift = <2>; |
621 | reg-io-width = <4>; | |
98096560 | 622 | clocks = <&apb2_gates 19>; |
24a661e9 | 623 | resets = <&apb2_rst 19>; |
d2d878c4 MR |
624 | dmas = <&dma 9>, <&dma 9>; |
625 | dma-names = "rx", "tx"; | |
8aed3b31 MR |
626 | status = "disabled"; |
627 | }; | |
628 | ||
629 | uart4: serial@01c29000 { | |
630 | compatible = "snps,dw-apb-uart"; | |
631 | reg = <0x01c29000 0x400>; | |
6f97dc8d | 632 | interrupts = <0 4 4>; |
8aed3b31 MR |
633 | reg-shift = <2>; |
634 | reg-io-width = <4>; | |
98096560 | 635 | clocks = <&apb2_gates 20>; |
24a661e9 | 636 | resets = <&apb2_rst 20>; |
d2d878c4 MR |
637 | dmas = <&dma 10>, <&dma 10>; |
638 | dma-names = "rx", "tx"; | |
8aed3b31 MR |
639 | status = "disabled"; |
640 | }; | |
641 | ||
642 | uart5: serial@01c29400 { | |
643 | compatible = "snps,dw-apb-uart"; | |
644 | reg = <0x01c29400 0x400>; | |
6f97dc8d | 645 | interrupts = <0 5 4>; |
8aed3b31 MR |
646 | reg-shift = <2>; |
647 | reg-io-width = <4>; | |
98096560 | 648 | clocks = <&apb2_gates 21>; |
24a661e9 | 649 | resets = <&apb2_rst 21>; |
d2d878c4 MR |
650 | dmas = <&dma 22>, <&dma 22>; |
651 | dma-names = "rx", "tx"; | |
8aed3b31 MR |
652 | status = "disabled"; |
653 | }; | |
654 | ||
96c7cc9b MR |
655 | i2c0: i2c@01c2ac00 { |
656 | compatible = "allwinner,sun6i-a31-i2c"; | |
657 | reg = <0x01c2ac00 0x400>; | |
658 | interrupts = <0 6 4>; | |
659 | clocks = <&apb2_gates 0>; | |
660 | clock-frequency = <100000>; | |
661 | resets = <&apb2_rst 0>; | |
662 | status = "disabled"; | |
495bccf3 CYT |
663 | #address-cells = <1>; |
664 | #size-cells = <0>; | |
96c7cc9b MR |
665 | }; |
666 | ||
667 | i2c1: i2c@01c2b000 { | |
668 | compatible = "allwinner,sun6i-a31-i2c"; | |
669 | reg = <0x01c2b000 0x400>; | |
670 | interrupts = <0 7 4>; | |
671 | clocks = <&apb2_gates 1>; | |
672 | clock-frequency = <100000>; | |
673 | resets = <&apb2_rst 1>; | |
674 | status = "disabled"; | |
495bccf3 CYT |
675 | #address-cells = <1>; |
676 | #size-cells = <0>; | |
96c7cc9b MR |
677 | }; |
678 | ||
679 | i2c2: i2c@01c2b400 { | |
680 | compatible = "allwinner,sun6i-a31-i2c"; | |
681 | reg = <0x01c2b400 0x400>; | |
682 | interrupts = <0 8 4>; | |
683 | clocks = <&apb2_gates 2>; | |
684 | clock-frequency = <100000>; | |
685 | resets = <&apb2_rst 2>; | |
686 | status = "disabled"; | |
495bccf3 CYT |
687 | #address-cells = <1>; |
688 | #size-cells = <0>; | |
96c7cc9b MR |
689 | }; |
690 | ||
691 | i2c3: i2c@01c2b800 { | |
692 | compatible = "allwinner,sun6i-a31-i2c"; | |
693 | reg = <0x01c2b800 0x400>; | |
694 | interrupts = <0 9 4>; | |
695 | clocks = <&apb2_gates 3>; | |
696 | clock-frequency = <100000>; | |
697 | resets = <&apb2_rst 3>; | |
698 | status = "disabled"; | |
495bccf3 CYT |
699 | #address-cells = <1>; |
700 | #size-cells = <0>; | |
96c7cc9b MR |
701 | }; |
702 | ||
3dca65f8 CYT |
703 | gmac: ethernet@01c30000 { |
704 | compatible = "allwinner,sun7i-a20-gmac"; | |
705 | reg = <0x01c30000 0x1054>; | |
706 | interrupts = <0 82 4>; | |
707 | interrupt-names = "macirq"; | |
708 | clocks = <&ahb1_gates 17>, <&gmac_tx_clk>; | |
709 | clock-names = "stmmaceth", "allwinner_gmac_tx"; | |
710 | resets = <&ahb1_rst 17>; | |
711 | reset-names = "stmmaceth"; | |
712 | snps,pbl = <2>; | |
713 | snps,fixed-burst; | |
714 | snps,force_sf_dma_mode; | |
715 | status = "disabled"; | |
716 | #address-cells = <1>; | |
717 | #size-cells = <0>; | |
718 | }; | |
719 | ||
8cffcb0c MR |
720 | timer@01c60000 { |
721 | compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer"; | |
722 | reg = <0x01c60000 0x1000>; | |
723 | interrupts = <0 51 4>, | |
724 | <0 52 4>, | |
725 | <0 53 4>, | |
726 | <0 54 4>; | |
727 | clocks = <&ahb1_gates 19>; | |
728 | resets = <&ahb1_rst 19>; | |
729 | }; | |
730 | ||
0d6efe33 MR |
731 | spi0: spi@01c68000 { |
732 | compatible = "allwinner,sun6i-a31-spi"; | |
733 | reg = <0x01c68000 0x1000>; | |
734 | interrupts = <0 65 4>; | |
735 | clocks = <&ahb1_gates 20>, <&spi0_clk>; | |
736 | clock-names = "ahb", "mod"; | |
d2d878c4 MR |
737 | dmas = <&dma 23>, <&dma 23>; |
738 | dma-names = "rx", "tx"; | |
0d6efe33 MR |
739 | resets = <&ahb1_rst 20>; |
740 | status = "disabled"; | |
741 | }; | |
742 | ||
743 | spi1: spi@01c69000 { | |
744 | compatible = "allwinner,sun6i-a31-spi"; | |
745 | reg = <0x01c69000 0x1000>; | |
746 | interrupts = <0 66 4>; | |
747 | clocks = <&ahb1_gates 21>, <&spi1_clk>; | |
748 | clock-names = "ahb", "mod"; | |
d2d878c4 MR |
749 | dmas = <&dma 24>, <&dma 24>; |
750 | dma-names = "rx", "tx"; | |
0d6efe33 MR |
751 | resets = <&ahb1_rst 21>; |
752 | status = "disabled"; | |
753 | }; | |
754 | ||
755 | spi2: spi@01c6a000 { | |
756 | compatible = "allwinner,sun6i-a31-spi"; | |
757 | reg = <0x01c6a000 0x1000>; | |
758 | interrupts = <0 67 4>; | |
759 | clocks = <&ahb1_gates 22>, <&spi2_clk>; | |
760 | clock-names = "ahb", "mod"; | |
d2d878c4 MR |
761 | dmas = <&dma 25>, <&dma 25>; |
762 | dma-names = "rx", "tx"; | |
0d6efe33 MR |
763 | resets = <&ahb1_rst 22>; |
764 | status = "disabled"; | |
765 | }; | |
766 | ||
767 | spi3: spi@01c6b000 { | |
768 | compatible = "allwinner,sun6i-a31-spi"; | |
769 | reg = <0x01c6b000 0x1000>; | |
770 | interrupts = <0 68 4>; | |
771 | clocks = <&ahb1_gates 23>, <&spi3_clk>; | |
772 | clock-names = "ahb", "mod"; | |
d2d878c4 MR |
773 | dmas = <&dma 26>, <&dma 26>; |
774 | dma-names = "rx", "tx"; | |
0d6efe33 MR |
775 | resets = <&ahb1_rst 23>; |
776 | status = "disabled"; | |
777 | }; | |
778 | ||
8aed3b31 MR |
779 | gic: interrupt-controller@01c81000 { |
780 | compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; | |
781 | reg = <0x01c81000 0x1000>, | |
782 | <0x01c82000 0x1000>, | |
783 | <0x01c84000 0x2000>, | |
784 | <0x01c86000 0x2000>; | |
785 | interrupt-controller; | |
786 | #interrupt-cells = <3>; | |
787 | interrupts = <1 9 0xf04>; | |
788 | }; | |
81ee429f | 789 | |
28240d27 MR |
790 | nmi_intc: interrupt-controller@01f00c0c { |
791 | compatible = "allwinner,sun6i-a31-sc-nmi"; | |
792 | interrupt-controller; | |
793 | #interrupt-cells = <2>; | |
794 | reg = <0x01f00c0c 0x38>; | |
795 | interrupts = <0 32 4>; | |
796 | }; | |
797 | ||
a42ea603 HG |
798 | prcm@01f01400 { |
799 | compatible = "allwinner,sun6i-a31-prcm"; | |
800 | reg = <0x01f01400 0x200>; | |
cc08f5e9 BB |
801 | |
802 | ar100: ar100_clk { | |
803 | compatible = "allwinner,sun6i-a31-ar100-clk"; | |
804 | #clock-cells = <0>; | |
805 | clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>; | |
806 | clock-output-names = "ar100"; | |
807 | }; | |
808 | ||
809 | ahb0: ahb0_clk { | |
810 | compatible = "fixed-factor-clock"; | |
811 | #clock-cells = <0>; | |
812 | clock-div = <1>; | |
813 | clock-mult = <1>; | |
814 | clocks = <&ar100>; | |
815 | clock-output-names = "ahb0"; | |
816 | }; | |
817 | ||
818 | apb0: apb0_clk { | |
819 | compatible = "allwinner,sun6i-a31-apb0-clk"; | |
820 | #clock-cells = <0>; | |
821 | clocks = <&ahb0>; | |
822 | clock-output-names = "apb0"; | |
823 | }; | |
824 | ||
825 | apb0_gates: apb0_gates_clk { | |
826 | compatible = "allwinner,sun6i-a31-apb0-gates-clk"; | |
827 | #clock-cells = <1>; | |
828 | clocks = <&apb0>; | |
829 | clock-output-names = "apb0_pio", "apb0_ir", | |
830 | "apb0_timer", "apb0_p2wi", | |
831 | "apb0_uart", "apb0_1wire", | |
832 | "apb0_i2c"; | |
833 | }; | |
834 | ||
835 | apb0_rst: apb0_rst { | |
836 | compatible = "allwinner,sun6i-a31-clock-reset"; | |
837 | #reset-cells = <1>; | |
838 | }; | |
a42ea603 HG |
839 | }; |
840 | ||
81ee429f MR |
841 | cpucfg@01f01c00 { |
842 | compatible = "allwinner,sun6i-a31-cpuconfig"; | |
843 | reg = <0x01f01c00 0x300>; | |
844 | }; | |
209394ae BB |
845 | |
846 | r_pio: pinctrl@01f02c00 { | |
847 | compatible = "allwinner,sun6i-a31-r-pinctrl"; | |
848 | reg = <0x01f02c00 0x400>; | |
849 | interrupts = <0 45 4>, | |
850 | <0 46 4>; | |
851 | clocks = <&apb0_gates 0>; | |
852 | resets = <&apb0_rst 0>; | |
853 | gpio-controller; | |
854 | interrupt-controller; | |
7d4ff96d | 855 | #interrupt-cells = <2>; |
209394ae BB |
856 | #size-cells = <0>; |
857 | #gpio-cells = <3>; | |
858 | }; | |
8aed3b31 MR |
859 | }; |
860 | }; |