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8aed3b31 MR |
1 | /* |
2 | * Copyright 2013 Maxime Ripard | |
3 | * | |
4 | * Maxime Ripard <maxime.ripard@free-electrons.com> | |
5 | * | |
6c3ba724 MR |
6 | * This file is dual-licensed: you can use it either under the terms |
7 | * of the GPL or the X11 license, at your option. Note that this dual | |
8 | * licensing only applies to this file, and not this project as a | |
9 | * whole. | |
8aed3b31 | 10 | * |
5186d83a | 11 | * a) This file is free software; you can redistribute it and/or |
6c3ba724 MR |
12 | * modify it under the terms of the GNU General Public License as |
13 | * published by the Free Software Foundation; either version 2 of the | |
14 | * License, or (at your option) any later version. | |
15 | * | |
5186d83a | 16 | * This file is distributed in the hope that it will be useful, |
6c3ba724 MR |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
6c3ba724 MR |
21 | * Or, alternatively, |
22 | * | |
23 | * b) Permission is hereby granted, free of charge, to any person | |
24 | * obtaining a copy of this software and associated documentation | |
25 | * files (the "Software"), to deal in the Software without | |
26 | * restriction, including without limitation the rights to use, | |
27 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
28 | * sell copies of the Software, and to permit persons to whom the | |
29 | * Software is furnished to do so, subject to the following | |
30 | * conditions: | |
31 | * | |
32 | * The above copyright notice and this permission notice shall be | |
33 | * included in all copies or substantial portions of the Software. | |
34 | * | |
35 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
36 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
37 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
38 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
39 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
40 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
41 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
42 | * OTHER DEALINGS IN THE SOFTWARE. | |
8aed3b31 MR |
43 | */ |
44 | ||
71455701 | 45 | #include "skeleton.dtsi" |
8aed3b31 | 46 | |
19882b84 | 47 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
eb58b40f | 48 | #include <dt-bindings/thermal/thermal.h> |
19882b84 | 49 | |
78a9f0db | 50 | #include <dt-bindings/clock/sun6i-a31-ccu.h> |
092a0c3b | 51 | #include <dt-bindings/pinctrl/sun4i-a10.h> |
78a9f0db | 52 | #include <dt-bindings/reset/sun6i-a31-ccu.h> |
8aed3b31 MR |
53 | |
54 | / { | |
55 | interrupt-parent = <&gic>; | |
56 | ||
54428d40 | 57 | aliases { |
e5073fde | 58 | ethernet0 = &gmac; |
54428d40 MR |
59 | }; |
60 | ||
e53a8b22 HG |
61 | chosen { |
62 | #address-cells = <1>; | |
63 | #size-cells = <1>; | |
64 | ranges; | |
65 | ||
c0949308 | 66 | simplefb_hdmi: framebuffer@0 { |
d8cacaa3 MR |
67 | compatible = "allwinner,simple-framebuffer", |
68 | "simple-framebuffer"; | |
a9f8cda3 | 69 | allwinner,pipeline = "de_be0-lcd0-hdmi"; |
78a9f0db CYT |
70 | clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>, |
71 | <&ccu CLK_AHB1_HDMI>, <&ccu CLK_DRAM_BE0>, | |
72 | <&ccu CLK_IEP_DRC0>, <&ccu CLK_BE0>, | |
73 | <&ccu CLK_LCD0_CH1>, <&ccu CLK_HDMI>; | |
e53a8b22 HG |
74 | status = "disabled"; |
75 | }; | |
fd18c7ea | 76 | |
c0949308 | 77 | simplefb_lcd: framebuffer@1 { |
fd18c7ea HG |
78 | compatible = "allwinner,simple-framebuffer", |
79 | "simple-framebuffer"; | |
80 | allwinner,pipeline = "de_be0-lcd0"; | |
78a9f0db CYT |
81 | clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>, |
82 | <&ccu CLK_DRAM_BE0>, <&ccu CLK_IEP_DRC0>, | |
83 | <&ccu CLK_BE0>, <&ccu CLK_LCD0_CH0>; | |
fd18c7ea HG |
84 | status = "disabled"; |
85 | }; | |
e53a8b22 | 86 | }; |
54428d40 | 87 | |
121b96cd MR |
88 | timer { |
89 | compatible = "arm,armv7-timer"; | |
90 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
91 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
92 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
93 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; | |
94 | clock-frequency = <24000000>; | |
95 | arm,cpu-registers-not-fw-configured; | |
e53a8b22 | 96 | }; |
54428d40 | 97 | |
8aed3b31 | 98 | cpus { |
ce78e353 | 99 | enable-method = "allwinner,sun6i-a31"; |
8aed3b31 MR |
100 | #address-cells = <1>; |
101 | #size-cells = <0>; | |
102 | ||
3a2bc642 | 103 | cpu0: cpu@0 { |
8aed3b31 MR |
104 | compatible = "arm,cortex-a7"; |
105 | device_type = "cpu"; | |
106 | reg = <0>; | |
78a9f0db | 107 | clocks = <&ccu CLK_CPU>; |
3a2bc642 CYT |
108 | clock-latency = <244144>; /* 8 32k periods */ |
109 | operating-points = < | |
8358aada | 110 | /* kHz uV */ |
3a2bc642 | 111 | 1008000 1200000 |
8358aada MR |
112 | 864000 1200000 |
113 | 720000 1100000 | |
114 | 480000 1000000 | |
3a2bc642 CYT |
115 | >; |
116 | #cooling-cells = <2>; | |
117 | cooling-min-level = <0>; | |
118 | cooling-max-level = <3>; | |
8aed3b31 MR |
119 | }; |
120 | ||
121 | cpu@1 { | |
122 | compatible = "arm,cortex-a7"; | |
123 | device_type = "cpu"; | |
124 | reg = <1>; | |
125 | }; | |
126 | ||
127 | cpu@2 { | |
128 | compatible = "arm,cortex-a7"; | |
129 | device_type = "cpu"; | |
130 | reg = <2>; | |
131 | }; | |
132 | ||
133 | cpu@3 { | |
134 | compatible = "arm,cortex-a7"; | |
135 | device_type = "cpu"; | |
136 | reg = <3>; | |
137 | }; | |
138 | }; | |
139 | ||
eb58b40f CYT |
140 | thermal-zones { |
141 | cpu_thermal { | |
142 | /* milliseconds */ | |
143 | polling-delay-passive = <250>; | |
144 | polling-delay = <1000>; | |
145 | thermal-sensors = <&rtp>; | |
146 | ||
147 | cooling-maps { | |
148 | map0 { | |
149 | trip = <&cpu_alert0>; | |
150 | cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
151 | }; | |
152 | }; | |
153 | ||
154 | trips { | |
155 | cpu_alert0: cpu_alert0 { | |
156 | /* milliCelsius */ | |
157 | temperature = <70000>; | |
158 | hysteresis = <2000>; | |
159 | type = "passive"; | |
160 | }; | |
161 | ||
162 | cpu_crit: cpu_crit { | |
163 | /* milliCelsius */ | |
164 | temperature = <100000>; | |
165 | hysteresis = <2000>; | |
166 | type = "critical"; | |
167 | }; | |
168 | }; | |
169 | }; | |
170 | }; | |
171 | ||
8aed3b31 MR |
172 | memory { |
173 | reg = <0x40000000 0x80000000>; | |
174 | }; | |
175 | ||
b5a10b76 MR |
176 | pmu { |
177 | compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu"; | |
19882b84 MR |
178 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, |
179 | <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, | |
180 | <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, | |
181 | <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; | |
b5a10b76 MR |
182 | }; |
183 | ||
8aed3b31 MR |
184 | clocks { |
185 | #address-cells = <1>; | |
98096560 MR |
186 | #size-cells = <1>; |
187 | ranges; | |
8aed3b31 | 188 | |
98096560 | 189 | osc24M: osc24M { |
8aed3b31 MR |
190 | #clock-cells = <0>; |
191 | compatible = "fixed-clock"; | |
192 | clock-frequency = <24000000>; | |
193 | }; | |
98096560 | 194 | |
7b5b2909 | 195 | osc32k: clk@0 { |
98096560 MR |
196 | #clock-cells = <0>; |
197 | compatible = "fixed-clock"; | |
198 | clock-frequency = <32768>; | |
7b5b2909 | 199 | clock-output-names = "osc32k"; |
98096560 MR |
200 | }; |
201 | ||
ed29861a | 202 | /* |
d8cacaa3 MR |
203 | * The following two are dummy clocks, placeholders |
204 | * used in the gmac_tx clock. The gmac driver will | |
205 | * choose one parent depending on the PHY interface | |
206 | * mode, using clk_set_rate auto-reparenting. | |
207 | * | |
208 | * The actual TX clock rate is not controlled by the | |
209 | * gmac_tx clock. | |
ed29861a CYT |
210 | */ |
211 | mii_phy_tx_clk: clk@1 { | |
212 | #clock-cells = <0>; | |
213 | compatible = "fixed-clock"; | |
214 | clock-frequency = <25000000>; | |
215 | clock-output-names = "mii_phy_tx"; | |
216 | }; | |
217 | ||
218 | gmac_int_tx_clk: clk@2 { | |
219 | #clock-cells = <0>; | |
220 | compatible = "fixed-clock"; | |
221 | clock-frequency = <125000000>; | |
222 | clock-output-names = "gmac_int_tx"; | |
223 | }; | |
224 | ||
225 | gmac_tx_clk: clk@01c200d0 { | |
226 | #clock-cells = <0>; | |
227 | compatible = "allwinner,sun7i-a20-gmac-clk"; | |
228 | reg = <0x01c200d0 0x4>; | |
229 | clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; | |
230 | clock-output-names = "gmac_tx"; | |
231 | }; | |
8aed3b31 MR |
232 | }; |
233 | ||
234 | soc@01c00000 { | |
235 | compatible = "simple-bus"; | |
236 | #address-cells = <1>; | |
237 | #size-cells = <1>; | |
238 | ranges; | |
239 | ||
d2d878c4 MR |
240 | dma: dma-controller@01c02000 { |
241 | compatible = "allwinner,sun6i-a31-dma"; | |
242 | reg = <0x01c02000 0x1000>; | |
19882b84 | 243 | interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; |
78a9f0db CYT |
244 | clocks = <&ccu CLK_AHB1_DMA>; |
245 | resets = <&ccu RST_AHB1_DMA>; | |
d2d878c4 MR |
246 | #dma-cells = <1>; |
247 | }; | |
248 | ||
5b753f0e HG |
249 | mmc0: mmc@01c0f000 { |
250 | compatible = "allwinner,sun5i-a13-mmc"; | |
251 | reg = <0x01c0f000 0x1000>; | |
78a9f0db CYT |
252 | clocks = <&ccu CLK_AHB1_MMC0>, |
253 | <&ccu CLK_MMC0>, | |
254 | <&ccu CLK_MMC0_OUTPUT>, | |
255 | <&ccu CLK_MMC0_SAMPLE>; | |
d8c3a392 MR |
256 | clock-names = "ahb", |
257 | "mmc", | |
258 | "output", | |
259 | "sample"; | |
78a9f0db | 260 | resets = <&ccu RST_AHB1_MMC0>; |
5b753f0e | 261 | reset-names = "ahb"; |
19882b84 | 262 | interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; |
5b753f0e | 263 | status = "disabled"; |
4c1bb9c3 HG |
264 | #address-cells = <1>; |
265 | #size-cells = <0>; | |
5b753f0e HG |
266 | }; |
267 | ||
268 | mmc1: mmc@01c10000 { | |
269 | compatible = "allwinner,sun5i-a13-mmc"; | |
270 | reg = <0x01c10000 0x1000>; | |
78a9f0db CYT |
271 | clocks = <&ccu CLK_AHB1_MMC1>, |
272 | <&ccu CLK_MMC1>, | |
273 | <&ccu CLK_MMC1_OUTPUT>, | |
274 | <&ccu CLK_MMC1_SAMPLE>; | |
d8c3a392 MR |
275 | clock-names = "ahb", |
276 | "mmc", | |
277 | "output", | |
278 | "sample"; | |
78a9f0db | 279 | resets = <&ccu RST_AHB1_MMC1>; |
5b753f0e | 280 | reset-names = "ahb"; |
19882b84 | 281 | interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; |
5b753f0e | 282 | status = "disabled"; |
4c1bb9c3 HG |
283 | #address-cells = <1>; |
284 | #size-cells = <0>; | |
5b753f0e HG |
285 | }; |
286 | ||
287 | mmc2: mmc@01c11000 { | |
288 | compatible = "allwinner,sun5i-a13-mmc"; | |
289 | reg = <0x01c11000 0x1000>; | |
78a9f0db CYT |
290 | clocks = <&ccu CLK_AHB1_MMC2>, |
291 | <&ccu CLK_MMC2>, | |
292 | <&ccu CLK_MMC2_OUTPUT>, | |
293 | <&ccu CLK_MMC2_SAMPLE>; | |
d8c3a392 MR |
294 | clock-names = "ahb", |
295 | "mmc", | |
296 | "output", | |
297 | "sample"; | |
78a9f0db | 298 | resets = <&ccu RST_AHB1_MMC2>; |
5b753f0e | 299 | reset-names = "ahb"; |
19882b84 | 300 | interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; |
5b753f0e | 301 | status = "disabled"; |
4c1bb9c3 HG |
302 | #address-cells = <1>; |
303 | #size-cells = <0>; | |
5b753f0e HG |
304 | }; |
305 | ||
306 | mmc3: mmc@01c12000 { | |
307 | compatible = "allwinner,sun5i-a13-mmc"; | |
308 | reg = <0x01c12000 0x1000>; | |
78a9f0db CYT |
309 | clocks = <&ccu CLK_AHB1_MMC3>, |
310 | <&ccu CLK_MMC3>, | |
311 | <&ccu CLK_MMC3_OUTPUT>, | |
312 | <&ccu CLK_MMC3_SAMPLE>; | |
d8c3a392 MR |
313 | clock-names = "ahb", |
314 | "mmc", | |
315 | "output", | |
316 | "sample"; | |
78a9f0db | 317 | resets = <&ccu RST_AHB1_MMC3>; |
5b753f0e | 318 | reset-names = "ahb"; |
19882b84 | 319 | interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; |
5b753f0e | 320 | status = "disabled"; |
4c1bb9c3 HG |
321 | #address-cells = <1>; |
322 | #size-cells = <0>; | |
5b753f0e HG |
323 | }; |
324 | ||
d208eaf2 HG |
325 | usb_otg: usb@01c19000 { |
326 | compatible = "allwinner,sun6i-a31-musb"; | |
327 | reg = <0x01c19000 0x0400>; | |
78a9f0db CYT |
328 | clocks = <&ccu CLK_AHB1_OTG>; |
329 | resets = <&ccu RST_AHB1_OTG>; | |
d208eaf2 HG |
330 | interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; |
331 | interrupt-names = "mc"; | |
332 | phys = <&usbphy 0>; | |
333 | phy-names = "usb"; | |
334 | extcon = <&usbphy 0>; | |
335 | status = "disabled"; | |
336 | }; | |
337 | ||
ef964085 MR |
338 | usbphy: phy@01c19400 { |
339 | compatible = "allwinner,sun6i-a31-usb-phy"; | |
340 | reg = <0x01c19400 0x10>, | |
341 | <0x01c1a800 0x4>, | |
342 | <0x01c1b800 0x4>; | |
343 | reg-names = "phy_ctrl", | |
344 | "pmu1", | |
345 | "pmu2"; | |
78a9f0db CYT |
346 | clocks = <&ccu CLK_USB_PHY0>, |
347 | <&ccu CLK_USB_PHY1>, | |
348 | <&ccu CLK_USB_PHY2>; | |
ef964085 MR |
349 | clock-names = "usb0_phy", |
350 | "usb1_phy", | |
351 | "usb2_phy"; | |
78a9f0db CYT |
352 | resets = <&ccu RST_USB_PHY0>, |
353 | <&ccu RST_USB_PHY1>, | |
354 | <&ccu RST_USB_PHY2>; | |
ef964085 MR |
355 | reset-names = "usb0_reset", |
356 | "usb1_reset", | |
357 | "usb2_reset"; | |
358 | status = "disabled"; | |
359 | #phy-cells = <1>; | |
360 | }; | |
361 | ||
362 | ehci0: usb@01c1a000 { | |
363 | compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; | |
364 | reg = <0x01c1a000 0x100>; | |
19882b84 | 365 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
78a9f0db CYT |
366 | clocks = <&ccu CLK_AHB1_EHCI0>; |
367 | resets = <&ccu RST_AHB1_EHCI0>; | |
ef964085 MR |
368 | phys = <&usbphy 1>; |
369 | phy-names = "usb"; | |
370 | status = "disabled"; | |
371 | }; | |
372 | ||
373 | ohci0: usb@01c1a400 { | |
374 | compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; | |
375 | reg = <0x01c1a400 0x100>; | |
19882b84 | 376 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
78a9f0db CYT |
377 | clocks = <&ccu CLK_AHB1_OHCI0>, <&ccu CLK_USB_OHCI0>; |
378 | resets = <&ccu RST_AHB1_OHCI0>; | |
ef964085 MR |
379 | phys = <&usbphy 1>; |
380 | phy-names = "usb"; | |
381 | status = "disabled"; | |
382 | }; | |
383 | ||
384 | ehci1: usb@01c1b000 { | |
385 | compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; | |
386 | reg = <0x01c1b000 0x100>; | |
19882b84 | 387 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
78a9f0db CYT |
388 | clocks = <&ccu CLK_AHB1_EHCI1>; |
389 | resets = <&ccu RST_AHB1_EHCI1>; | |
ef964085 MR |
390 | phys = <&usbphy 2>; |
391 | phy-names = "usb"; | |
392 | status = "disabled"; | |
393 | }; | |
394 | ||
395 | ohci1: usb@01c1b400 { | |
396 | compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; | |
397 | reg = <0x01c1b400 0x100>; | |
19882b84 | 398 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
78a9f0db CYT |
399 | clocks = <&ccu CLK_AHB1_OHCI1>, <&ccu CLK_USB_OHCI1>; |
400 | resets = <&ccu RST_AHB1_OHCI1>; | |
ef964085 MR |
401 | phys = <&usbphy 2>; |
402 | phy-names = "usb"; | |
403 | status = "disabled"; | |
404 | }; | |
405 | ||
b294ebbc | 406 | ohci2: usb@01c1c400 { |
ef964085 MR |
407 | compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; |
408 | reg = <0x01c1c400 0x100>; | |
19882b84 | 409 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
78a9f0db CYT |
410 | clocks = <&ccu CLK_AHB1_OHCI2>, <&ccu CLK_USB_OHCI2>; |
411 | resets = <&ccu RST_AHB1_OHCI2>; | |
ef964085 MR |
412 | status = "disabled"; |
413 | }; | |
414 | ||
78a9f0db CYT |
415 | ccu: clock@01c20000 { |
416 | compatible = "allwinner,sun6i-a31-ccu"; | |
417 | reg = <0x01c20000 0x400>; | |
418 | clocks = <&osc24M>, <&osc32k>; | |
419 | clock-names = "hosc", "losc"; | |
420 | #clock-cells = <1>; | |
421 | #reset-cells = <1>; | |
422 | }; | |
423 | ||
140e1721 MR |
424 | pio: pinctrl@01c20800 { |
425 | compatible = "allwinner,sun6i-a31-pinctrl"; | |
426 | reg = <0x01c20800 0x400>; | |
19882b84 MR |
427 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, |
428 | <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, | |
429 | <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, | |
430 | <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | |
78a9f0db | 431 | clocks = <&ccu CLK_APB1_PIO>; |
140e1721 MR |
432 | gpio-controller; |
433 | interrupt-controller; | |
b03e0816 | 434 | #interrupt-cells = <3>; |
140e1721 | 435 | #gpio-cells = <3>; |
ab4238cd MR |
436 | |
437 | uart0_pins_a: uart0@0 { | |
438 | allwinner,pins = "PH20", "PH21"; | |
439 | allwinner,function = "uart0"; | |
092a0c3b MR |
440 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
441 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
ab4238cd | 442 | }; |
8be188b8 MR |
443 | |
444 | i2c0_pins_a: i2c0@0 { | |
445 | allwinner,pins = "PH14", "PH15"; | |
446 | allwinner,function = "i2c0"; | |
092a0c3b MR |
447 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
448 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
8be188b8 MR |
449 | }; |
450 | ||
451 | i2c1_pins_a: i2c1@0 { | |
452 | allwinner,pins = "PH16", "PH17"; | |
453 | allwinner,function = "i2c1"; | |
092a0c3b MR |
454 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
455 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
8be188b8 MR |
456 | }; |
457 | ||
458 | i2c2_pins_a: i2c2@0 { | |
459 | allwinner,pins = "PH18", "PH19"; | |
460 | allwinner,function = "i2c2"; | |
092a0c3b MR |
461 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
462 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
8be188b8 | 463 | }; |
9797eb83 HG |
464 | |
465 | mmc0_pins_a: mmc0@0 { | |
d8cacaa3 MR |
466 | allwinner,pins = "PF0", "PF1", "PF2", |
467 | "PF3", "PF4", "PF5"; | |
9797eb83 | 468 | allwinner,function = "mmc0"; |
092a0c3b MR |
469 | allwinner,drive = <SUN4I_PINCTRL_30_MA>; |
470 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
9797eb83 | 471 | }; |
ee39a3e3 | 472 | |
878c4ded CYT |
473 | mmc1_pins_a: mmc1@0 { |
474 | allwinner,pins = "PG0", "PG1", "PG2", "PG3", | |
475 | "PG4", "PG5"; | |
476 | allwinner,function = "mmc1"; | |
477 | allwinner,drive = <SUN4I_PINCTRL_30_MA>; | |
478 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
479 | }; | |
480 | ||
5edab366 HG |
481 | mmc2_pins_a: mmc2@0 { |
482 | allwinner,pins = "PC6", "PC7", "PC8", "PC9", | |
483 | "PC10", "PC11"; | |
484 | allwinner,function = "mmc2"; | |
485 | allwinner,drive = <SUN4I_PINCTRL_30_MA>; | |
486 | allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; | |
487 | }; | |
488 | ||
489 | mmc2_8bit_emmc_pins: mmc2@1 { | |
4917c46c CYT |
490 | allwinner,pins = "PC6", "PC7", "PC8", "PC9", |
491 | "PC10", "PC11", "PC12", | |
492 | "PC13", "PC14", "PC15", | |
493 | "PC24"; | |
494 | allwinner,function = "mmc2"; | |
495 | allwinner,drive = <SUN4I_PINCTRL_30_MA>; | |
496 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
497 | }; | |
498 | ||
a22f8b22 CYT |
499 | mmc3_8bit_emmc_pins: mmc3@1 { |
500 | allwinner,pins = "PC6", "PC7", "PC8", "PC9", | |
501 | "PC10", "PC11", "PC12", | |
502 | "PC13", "PC14", "PC15", | |
503 | "PC24"; | |
504 | allwinner,function = "mmc3"; | |
505 | allwinner,drive = <SUN4I_PINCTRL_40_MA>; | |
506 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
507 | }; | |
508 | ||
ee39a3e3 CYT |
509 | gmac_pins_mii_a: gmac_mii@0 { |
510 | allwinner,pins = "PA0", "PA1", "PA2", "PA3", | |
511 | "PA8", "PA9", "PA11", | |
512 | "PA12", "PA13", "PA14", "PA19", | |
513 | "PA20", "PA21", "PA22", "PA23", | |
514 | "PA24", "PA26", "PA27"; | |
515 | allwinner,function = "gmac"; | |
092a0c3b MR |
516 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
517 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
ee39a3e3 CYT |
518 | }; |
519 | ||
520 | gmac_pins_gmii_a: gmac_gmii@0 { | |
521 | allwinner,pins = "PA0", "PA1", "PA2", "PA3", | |
522 | "PA4", "PA5", "PA6", "PA7", | |
523 | "PA8", "PA9", "PA10", "PA11", | |
524 | "PA12", "PA13", "PA14", "PA15", | |
525 | "PA16", "PA17", "PA18", "PA19", | |
526 | "PA20", "PA21", "PA22", "PA23", | |
527 | "PA24", "PA25", "PA26", "PA27"; | |
528 | allwinner,function = "gmac"; | |
529 | /* | |
530 | * data lines in GMII mode run at 125MHz and | |
531 | * might need a higher signal drive strength | |
532 | */ | |
092a0c3b MR |
533 | allwinner,drive = <SUN4I_PINCTRL_30_MA>; |
534 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
ee39a3e3 CYT |
535 | }; |
536 | ||
537 | gmac_pins_rgmii_a: gmac_rgmii@0 { | |
538 | allwinner,pins = "PA0", "PA1", "PA2", "PA3", | |
539 | "PA9", "PA10", "PA11", | |
540 | "PA12", "PA13", "PA14", "PA19", | |
541 | "PA20", "PA25", "PA26", "PA27"; | |
542 | allwinner,function = "gmac"; | |
543 | /* | |
544 | * data lines in RGMII mode use DDR mode | |
545 | * and need a higher signal drive strength | |
546 | */ | |
092a0c3b MR |
547 | allwinner,drive = <SUN4I_PINCTRL_40_MA>; |
548 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
ee39a3e3 | 549 | }; |
140e1721 MR |
550 | }; |
551 | ||
8aed3b31 | 552 | timer@01c20c00 { |
b4f26440 | 553 | compatible = "allwinner,sun4i-a10-timer"; |
8aed3b31 | 554 | reg = <0x01c20c00 0xa0>; |
19882b84 MR |
555 | interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, |
556 | <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, | |
557 | <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, | |
558 | <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, | |
559 | <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; | |
98096560 | 560 | clocks = <&osc24M>; |
8aed3b31 MR |
561 | }; |
562 | ||
563 | wdt1: watchdog@01c20ca0 { | |
ca5d04d9 | 564 | compatible = "allwinner,sun6i-a31-wdt"; |
8aed3b31 MR |
565 | reg = <0x01c20ca0 0x20>; |
566 | }; | |
61d2595c CYT |
567 | |
568 | lradc: lradc@01c22800 { | |
569 | compatible = "allwinner,sun4i-a10-lradc-keys"; | |
570 | reg = <0x01c22800 0x100>; | |
571 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; | |
572 | status = "disabled"; | |
573 | }; | |
8aed3b31 | 574 | |
4ec45cd3 CYT |
575 | rtp: rtp@01c25000 { |
576 | compatible = "allwinner,sun6i-a31-ts"; | |
577 | reg = <0x01c25000 0x100>; | |
578 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; | |
579 | #thermal-sensor-cells = <0>; | |
580 | }; | |
581 | ||
8aed3b31 MR |
582 | uart0: serial@01c28000 { |
583 | compatible = "snps,dw-apb-uart"; | |
584 | reg = <0x01c28000 0x400>; | |
19882b84 | 585 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; |
8aed3b31 MR |
586 | reg-shift = <2>; |
587 | reg-io-width = <4>; | |
78a9f0db CYT |
588 | clocks = <&ccu CLK_APB2_UART0>; |
589 | resets = <&ccu RST_APB2_UART0>; | |
d2d878c4 MR |
590 | dmas = <&dma 6>, <&dma 6>; |
591 | dma-names = "rx", "tx"; | |
8aed3b31 MR |
592 | status = "disabled"; |
593 | }; | |
594 | ||
595 | uart1: serial@01c28400 { | |
596 | compatible = "snps,dw-apb-uart"; | |
597 | reg = <0x01c28400 0x400>; | |
19882b84 | 598 | interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; |
8aed3b31 MR |
599 | reg-shift = <2>; |
600 | reg-io-width = <4>; | |
78a9f0db CYT |
601 | clocks = <&ccu CLK_APB2_UART1>; |
602 | resets = <&ccu RST_APB2_UART1>; | |
d2d878c4 MR |
603 | dmas = <&dma 7>, <&dma 7>; |
604 | dma-names = "rx", "tx"; | |
8aed3b31 MR |
605 | status = "disabled"; |
606 | }; | |
607 | ||
608 | uart2: serial@01c28800 { | |
609 | compatible = "snps,dw-apb-uart"; | |
610 | reg = <0x01c28800 0x400>; | |
19882b84 | 611 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
8aed3b31 MR |
612 | reg-shift = <2>; |
613 | reg-io-width = <4>; | |
78a9f0db CYT |
614 | clocks = <&ccu CLK_APB2_UART2>; |
615 | resets = <&ccu RST_APB2_UART2>; | |
d2d878c4 MR |
616 | dmas = <&dma 8>, <&dma 8>; |
617 | dma-names = "rx", "tx"; | |
8aed3b31 MR |
618 | status = "disabled"; |
619 | }; | |
620 | ||
621 | uart3: serial@01c28c00 { | |
622 | compatible = "snps,dw-apb-uart"; | |
623 | reg = <0x01c28c00 0x400>; | |
19882b84 | 624 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; |
8aed3b31 MR |
625 | reg-shift = <2>; |
626 | reg-io-width = <4>; | |
78a9f0db CYT |
627 | clocks = <&ccu CLK_APB2_UART3>; |
628 | resets = <&ccu RST_APB2_UART3>; | |
d2d878c4 MR |
629 | dmas = <&dma 9>, <&dma 9>; |
630 | dma-names = "rx", "tx"; | |
8aed3b31 MR |
631 | status = "disabled"; |
632 | }; | |
633 | ||
634 | uart4: serial@01c29000 { | |
635 | compatible = "snps,dw-apb-uart"; | |
636 | reg = <0x01c29000 0x400>; | |
19882b84 | 637 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; |
8aed3b31 MR |
638 | reg-shift = <2>; |
639 | reg-io-width = <4>; | |
78a9f0db CYT |
640 | clocks = <&ccu CLK_APB2_UART4>; |
641 | resets = <&ccu RST_APB2_UART4>; | |
d2d878c4 MR |
642 | dmas = <&dma 10>, <&dma 10>; |
643 | dma-names = "rx", "tx"; | |
8aed3b31 MR |
644 | status = "disabled"; |
645 | }; | |
646 | ||
647 | uart5: serial@01c29400 { | |
648 | compatible = "snps,dw-apb-uart"; | |
649 | reg = <0x01c29400 0x400>; | |
19882b84 | 650 | interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; |
8aed3b31 MR |
651 | reg-shift = <2>; |
652 | reg-io-width = <4>; | |
78a9f0db CYT |
653 | clocks = <&ccu CLK_APB2_UART5>; |
654 | resets = <&ccu RST_APB2_UART5>; | |
d2d878c4 MR |
655 | dmas = <&dma 22>, <&dma 22>; |
656 | dma-names = "rx", "tx"; | |
8aed3b31 MR |
657 | status = "disabled"; |
658 | }; | |
659 | ||
96c7cc9b MR |
660 | i2c0: i2c@01c2ac00 { |
661 | compatible = "allwinner,sun6i-a31-i2c"; | |
662 | reg = <0x01c2ac00 0x400>; | |
19882b84 | 663 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
78a9f0db CYT |
664 | clocks = <&ccu CLK_APB2_I2C0>; |
665 | resets = <&ccu RST_APB2_I2C0>; | |
96c7cc9b | 666 | status = "disabled"; |
495bccf3 CYT |
667 | #address-cells = <1>; |
668 | #size-cells = <0>; | |
96c7cc9b MR |
669 | }; |
670 | ||
671 | i2c1: i2c@01c2b000 { | |
672 | compatible = "allwinner,sun6i-a31-i2c"; | |
673 | reg = <0x01c2b000 0x400>; | |
19882b84 | 674 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
78a9f0db CYT |
675 | clocks = <&ccu CLK_APB2_I2C1>; |
676 | resets = <&ccu RST_APB2_I2C1>; | |
96c7cc9b | 677 | status = "disabled"; |
495bccf3 CYT |
678 | #address-cells = <1>; |
679 | #size-cells = <0>; | |
96c7cc9b MR |
680 | }; |
681 | ||
682 | i2c2: i2c@01c2b400 { | |
683 | compatible = "allwinner,sun6i-a31-i2c"; | |
684 | reg = <0x01c2b400 0x400>; | |
19882b84 | 685 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; |
78a9f0db CYT |
686 | clocks = <&ccu CLK_APB2_I2C2>; |
687 | resets = <&ccu RST_APB2_I2C2>; | |
96c7cc9b | 688 | status = "disabled"; |
495bccf3 CYT |
689 | #address-cells = <1>; |
690 | #size-cells = <0>; | |
96c7cc9b MR |
691 | }; |
692 | ||
693 | i2c3: i2c@01c2b800 { | |
694 | compatible = "allwinner,sun6i-a31-i2c"; | |
695 | reg = <0x01c2b800 0x400>; | |
19882b84 | 696 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
78a9f0db CYT |
697 | clocks = <&ccu CLK_APB2_I2C3>; |
698 | resets = <&ccu RST_APB2_I2C3>; | |
96c7cc9b | 699 | status = "disabled"; |
495bccf3 CYT |
700 | #address-cells = <1>; |
701 | #size-cells = <0>; | |
96c7cc9b MR |
702 | }; |
703 | ||
3dca65f8 CYT |
704 | gmac: ethernet@01c30000 { |
705 | compatible = "allwinner,sun7i-a20-gmac"; | |
706 | reg = <0x01c30000 0x1054>; | |
19882b84 | 707 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
3dca65f8 | 708 | interrupt-names = "macirq"; |
78a9f0db | 709 | clocks = <&ccu CLK_AHB1_EMAC>, <&gmac_tx_clk>; |
3dca65f8 | 710 | clock-names = "stmmaceth", "allwinner_gmac_tx"; |
78a9f0db | 711 | resets = <&ccu RST_AHB1_EMAC>; |
3dca65f8 CYT |
712 | reset-names = "stmmaceth"; |
713 | snps,pbl = <2>; | |
714 | snps,fixed-burst; | |
715 | snps,force_sf_dma_mode; | |
716 | status = "disabled"; | |
717 | #address-cells = <1>; | |
718 | #size-cells = <0>; | |
719 | }; | |
720 | ||
14fee74c CYT |
721 | crypto: crypto-engine@01c15000 { |
722 | compatible = "allwinner,sun4i-a10-crypto"; | |
723 | reg = <0x01c15000 0x1000>; | |
724 | interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; | |
78a9f0db | 725 | clocks = <&ccu CLK_AHB1_SS>, <&ccu CLK_SS>; |
14fee74c | 726 | clock-names = "ahb", "mod"; |
78a9f0db | 727 | resets = <&ccu RST_AHB1_SS>; |
14fee74c CYT |
728 | reset-names = "ahb"; |
729 | }; | |
730 | ||
8cffcb0c | 731 | timer@01c60000 { |
d8cacaa3 MR |
732 | compatible = "allwinner,sun6i-a31-hstimer", |
733 | "allwinner,sun7i-a20-hstimer"; | |
8cffcb0c | 734 | reg = <0x01c60000 0x1000>; |
19882b84 MR |
735 | interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, |
736 | <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, | |
737 | <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, | |
738 | <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; | |
78a9f0db CYT |
739 | clocks = <&ccu CLK_AHB1_HSTIMER>; |
740 | resets = <&ccu RST_AHB1_HSTIMER>; | |
8cffcb0c MR |
741 | }; |
742 | ||
0d6efe33 MR |
743 | spi0: spi@01c68000 { |
744 | compatible = "allwinner,sun6i-a31-spi"; | |
745 | reg = <0x01c68000 0x1000>; | |
19882b84 | 746 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
78a9f0db | 747 | clocks = <&ccu CLK_AHB1_SPI0>, <&ccu CLK_SPI0>; |
0d6efe33 | 748 | clock-names = "ahb", "mod"; |
d2d878c4 MR |
749 | dmas = <&dma 23>, <&dma 23>; |
750 | dma-names = "rx", "tx"; | |
78a9f0db | 751 | resets = <&ccu RST_AHB1_SPI0>; |
0d6efe33 MR |
752 | status = "disabled"; |
753 | }; | |
754 | ||
755 | spi1: spi@01c69000 { | |
756 | compatible = "allwinner,sun6i-a31-spi"; | |
757 | reg = <0x01c69000 0x1000>; | |
19882b84 | 758 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; |
78a9f0db | 759 | clocks = <&ccu CLK_AHB1_SPI1>, <&ccu CLK_SPI1>; |
0d6efe33 | 760 | clock-names = "ahb", "mod"; |
d2d878c4 MR |
761 | dmas = <&dma 24>, <&dma 24>; |
762 | dma-names = "rx", "tx"; | |
78a9f0db | 763 | resets = <&ccu RST_AHB1_SPI1>; |
0d6efe33 MR |
764 | status = "disabled"; |
765 | }; | |
766 | ||
767 | spi2: spi@01c6a000 { | |
768 | compatible = "allwinner,sun6i-a31-spi"; | |
769 | reg = <0x01c6a000 0x1000>; | |
19882b84 | 770 | interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; |
78a9f0db | 771 | clocks = <&ccu CLK_AHB1_SPI2>, <&ccu CLK_SPI2>; |
0d6efe33 | 772 | clock-names = "ahb", "mod"; |
d2d878c4 MR |
773 | dmas = <&dma 25>, <&dma 25>; |
774 | dma-names = "rx", "tx"; | |
78a9f0db | 775 | resets = <&ccu RST_AHB1_SPI2>; |
0d6efe33 MR |
776 | status = "disabled"; |
777 | }; | |
778 | ||
779 | spi3: spi@01c6b000 { | |
780 | compatible = "allwinner,sun6i-a31-spi"; | |
781 | reg = <0x01c6b000 0x1000>; | |
19882b84 | 782 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; |
78a9f0db | 783 | clocks = <&ccu CLK_AHB1_SPI3>, <&ccu CLK_SPI3>; |
0d6efe33 | 784 | clock-names = "ahb", "mod"; |
d2d878c4 MR |
785 | dmas = <&dma 26>, <&dma 26>; |
786 | dma-names = "rx", "tx"; | |
78a9f0db | 787 | resets = <&ccu RST_AHB1_SPI3>; |
0d6efe33 MR |
788 | status = "disabled"; |
789 | }; | |
790 | ||
8aed3b31 MR |
791 | gic: interrupt-controller@01c81000 { |
792 | compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; | |
793 | reg = <0x01c81000 0x1000>, | |
794 | <0x01c82000 0x1000>, | |
795 | <0x01c84000 0x2000>, | |
796 | <0x01c86000 0x2000>; | |
797 | interrupt-controller; | |
798 | #interrupt-cells = <3>; | |
19882b84 | 799 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
8aed3b31 | 800 | }; |
81ee429f | 801 | |
5e700435 CYT |
802 | rtc: rtc@01f00000 { |
803 | compatible = "allwinner,sun6i-a31-rtc"; | |
804 | reg = <0x01f00000 0x54>; | |
19882b84 MR |
805 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, |
806 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; | |
5e700435 CYT |
807 | }; |
808 | ||
28240d27 MR |
809 | nmi_intc: interrupt-controller@01f00c0c { |
810 | compatible = "allwinner,sun6i-a31-sc-nmi"; | |
811 | interrupt-controller; | |
812 | #interrupt-cells = <2>; | |
813 | reg = <0x01f00c0c 0x38>; | |
19882b84 | 814 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
28240d27 MR |
815 | }; |
816 | ||
a42ea603 HG |
817 | prcm@01f01400 { |
818 | compatible = "allwinner,sun6i-a31-prcm"; | |
819 | reg = <0x01f01400 0x200>; | |
cc08f5e9 BB |
820 | |
821 | ar100: ar100_clk { | |
822 | compatible = "allwinner,sun6i-a31-ar100-clk"; | |
823 | #clock-cells = <0>; | |
78a9f0db CYT |
824 | clocks = <&osc32k>, <&osc24M>, |
825 | <&ccu CLK_PLL_PERIPH>, | |
826 | <&ccu CLK_PLL_PERIPH>; | |
cc08f5e9 BB |
827 | clock-output-names = "ar100"; |
828 | }; | |
829 | ||
830 | ahb0: ahb0_clk { | |
831 | compatible = "fixed-factor-clock"; | |
832 | #clock-cells = <0>; | |
833 | clock-div = <1>; | |
834 | clock-mult = <1>; | |
835 | clocks = <&ar100>; | |
836 | clock-output-names = "ahb0"; | |
837 | }; | |
838 | ||
839 | apb0: apb0_clk { | |
840 | compatible = "allwinner,sun6i-a31-apb0-clk"; | |
841 | #clock-cells = <0>; | |
842 | clocks = <&ahb0>; | |
843 | clock-output-names = "apb0"; | |
844 | }; | |
845 | ||
846 | apb0_gates: apb0_gates_clk { | |
847 | compatible = "allwinner,sun6i-a31-apb0-gates-clk"; | |
848 | #clock-cells = <1>; | |
849 | clocks = <&apb0>; | |
850 | clock-output-names = "apb0_pio", "apb0_ir", | |
851 | "apb0_timer", "apb0_p2wi", | |
852 | "apb0_uart", "apb0_1wire", | |
853 | "apb0_i2c"; | |
854 | }; | |
855 | ||
9b5c6e06 HG |
856 | ir_clk: ir_clk { |
857 | #clock-cells = <0>; | |
858 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
859 | clocks = <&osc32k>, <&osc24M>; | |
860 | clock-output-names = "ir"; | |
861 | }; | |
862 | ||
cc08f5e9 BB |
863 | apb0_rst: apb0_rst { |
864 | compatible = "allwinner,sun6i-a31-clock-reset"; | |
865 | #reset-cells = <1>; | |
866 | }; | |
a42ea603 HG |
867 | }; |
868 | ||
81ee429f MR |
869 | cpucfg@01f01c00 { |
870 | compatible = "allwinner,sun6i-a31-cpuconfig"; | |
871 | reg = <0x01f01c00 0x300>; | |
872 | }; | |
209394ae | 873 | |
4ac367b4 HG |
874 | ir: ir@01f02000 { |
875 | compatible = "allwinner,sun5i-a13-ir"; | |
876 | clocks = <&apb0_gates 1>, <&ir_clk>; | |
877 | clock-names = "apb", "ir"; | |
878 | resets = <&apb0_rst 1>; | |
19882b84 | 879 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
4ac367b4 HG |
880 | reg = <0x01f02000 0x40>; |
881 | status = "disabled"; | |
882 | }; | |
883 | ||
209394ae BB |
884 | r_pio: pinctrl@01f02c00 { |
885 | compatible = "allwinner,sun6i-a31-r-pinctrl"; | |
886 | reg = <0x01f02c00 0x400>; | |
19882b84 MR |
887 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, |
888 | <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; | |
209394ae BB |
889 | clocks = <&apb0_gates 0>; |
890 | resets = <&apb0_rst 0>; | |
891 | gpio-controller; | |
892 | interrupt-controller; | |
6d55d339 | 893 | #interrupt-cells = <3>; |
209394ae BB |
894 | #size-cells = <0>; |
895 | #gpio-cells = <3>; | |
dbbcd881 HG |
896 | |
897 | ir_pins_a: ir@0 { | |
898 | allwinner,pins = "PL4"; | |
899 | allwinner,function = "s_ir"; | |
092a0c3b MR |
900 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
901 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
dbbcd881 | 902 | }; |
fcd60138 BB |
903 | |
904 | p2wi_pins: p2wi { | |
905 | allwinner,pins = "PL0", "PL1"; | |
906 | allwinner,function = "s_p2wi"; | |
907 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
908 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
909 | }; | |
910 | }; | |
911 | ||
912 | p2wi: i2c@01f03400 { | |
913 | compatible = "allwinner,sun6i-a31-p2wi"; | |
914 | reg = <0x01f03400 0x400>; | |
915 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; | |
916 | clocks = <&apb0_gates 3>; | |
917 | clock-frequency = <100000>; | |
918 | resets = <&apb0_rst 3>; | |
919 | pinctrl-names = "default"; | |
920 | pinctrl-0 = <&p2wi_pins>; | |
921 | status = "disabled"; | |
922 | #address-cells = <1>; | |
923 | #size-cells = <0>; | |
209394ae | 924 | }; |
8aed3b31 MR |
925 | }; |
926 | }; |