Commit | Line | Data |
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8aed3b31 MR |
1 | /* |
2 | * Copyright 2013 Maxime Ripard | |
3 | * | |
4 | * Maxime Ripard <maxime.ripard@free-electrons.com> | |
5 | * | |
6 | * The code contained herein is licensed under the GNU General Public | |
7 | * License. You may obtain a copy of the GNU General Public License | |
8 | * Version 2 or later at the following locations: | |
9 | * | |
10 | * http://www.opensource.org/licenses/gpl-license.html | |
11 | * http://www.gnu.org/copyleft/gpl.html | |
12 | */ | |
13 | ||
14 | /include/ "skeleton.dtsi" | |
15 | ||
16 | / { | |
17 | interrupt-parent = <&gic>; | |
18 | ||
54428d40 MR |
19 | aliases { |
20 | serial0 = &uart0; | |
21 | serial1 = &uart1; | |
22 | serial2 = &uart2; | |
23 | serial3 = &uart3; | |
24 | serial4 = &uart4; | |
25 | serial5 = &uart5; | |
26 | }; | |
27 | ||
28 | ||
8aed3b31 MR |
29 | cpus { |
30 | #address-cells = <1>; | |
31 | #size-cells = <0>; | |
32 | ||
33 | cpu@0 { | |
34 | compatible = "arm,cortex-a7"; | |
35 | device_type = "cpu"; | |
36 | reg = <0>; | |
37 | }; | |
38 | ||
39 | cpu@1 { | |
40 | compatible = "arm,cortex-a7"; | |
41 | device_type = "cpu"; | |
42 | reg = <1>; | |
43 | }; | |
44 | ||
45 | cpu@2 { | |
46 | compatible = "arm,cortex-a7"; | |
47 | device_type = "cpu"; | |
48 | reg = <2>; | |
49 | }; | |
50 | ||
51 | cpu@3 { | |
52 | compatible = "arm,cortex-a7"; | |
53 | device_type = "cpu"; | |
54 | reg = <3>; | |
55 | }; | |
56 | }; | |
57 | ||
58 | memory { | |
59 | reg = <0x40000000 0x80000000>; | |
60 | }; | |
61 | ||
62 | clocks { | |
63 | #address-cells = <1>; | |
98096560 MR |
64 | #size-cells = <1>; |
65 | ranges; | |
8aed3b31 | 66 | |
98096560 | 67 | osc24M: osc24M { |
8aed3b31 MR |
68 | #clock-cells = <0>; |
69 | compatible = "fixed-clock"; | |
70 | clock-frequency = <24000000>; | |
71 | }; | |
98096560 | 72 | |
7b5b2909 | 73 | osc32k: clk@0 { |
98096560 MR |
74 | #clock-cells = <0>; |
75 | compatible = "fixed-clock"; | |
76 | clock-frequency = <32768>; | |
7b5b2909 | 77 | clock-output-names = "osc32k"; |
98096560 MR |
78 | }; |
79 | ||
7b5b2909 | 80 | pll1: clk@01c20000 { |
98096560 MR |
81 | #clock-cells = <0>; |
82 | compatible = "allwinner,sun6i-a31-pll1-clk"; | |
83 | reg = <0x01c20000 0x4>; | |
84 | clocks = <&osc24M>; | |
7b5b2909 | 85 | clock-output-names = "pll1"; |
98096560 MR |
86 | }; |
87 | ||
b0a09c75 | 88 | pll6: clk@01c20028 { |
98096560 | 89 | #clock-cells = <0>; |
b0a09c75 MR |
90 | compatible = "allwinner,sun6i-a31-pll6-clk"; |
91 | reg = <0x01c20028 0x4>; | |
92 | clocks = <&osc24M>; | |
93 | clock-output-names = "pll6"; | |
98096560 MR |
94 | }; |
95 | ||
96 | cpu: cpu@01c20050 { | |
97 | #clock-cells = <0>; | |
bf6534a1 | 98 | compatible = "allwinner,sun4i-a10-cpu-clk"; |
98096560 MR |
99 | reg = <0x01c20050 0x4>; |
100 | ||
101 | /* | |
102 | * PLL1 is listed twice here. | |
103 | * While it looks suspicious, it's actually documented | |
104 | * that way both in the datasheet and in the code from | |
105 | * Allwinner. | |
106 | */ | |
107 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; | |
7b5b2909 | 108 | clock-output-names = "cpu"; |
98096560 MR |
109 | }; |
110 | ||
111 | axi: axi@01c20050 { | |
112 | #clock-cells = <0>; | |
bf6534a1 | 113 | compatible = "allwinner,sun4i-a10-axi-clk"; |
98096560 MR |
114 | reg = <0x01c20050 0x4>; |
115 | clocks = <&cpu>; | |
7b5b2909 | 116 | clock-output-names = "axi"; |
98096560 MR |
117 | }; |
118 | ||
119 | ahb1_mux: ahb1_mux@01c20054 { | |
120 | #clock-cells = <0>; | |
121 | compatible = "allwinner,sun6i-a31-ahb1-mux-clk"; | |
122 | reg = <0x01c20054 0x4>; | |
123 | clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>; | |
7b5b2909 | 124 | clock-output-names = "ahb1_mux"; |
98096560 MR |
125 | }; |
126 | ||
127 | ahb1: ahb1@01c20054 { | |
128 | #clock-cells = <0>; | |
bf6534a1 | 129 | compatible = "allwinner,sun4i-a10-ahb-clk"; |
98096560 MR |
130 | reg = <0x01c20054 0x4>; |
131 | clocks = <&ahb1_mux>; | |
7b5b2909 | 132 | clock-output-names = "ahb1"; |
98096560 MR |
133 | }; |
134 | ||
7b5b2909 | 135 | ahb1_gates: clk@01c20060 { |
98096560 MR |
136 | #clock-cells = <1>; |
137 | compatible = "allwinner,sun6i-a31-ahb1-gates-clk"; | |
138 | reg = <0x01c20060 0x8>; | |
139 | clocks = <&ahb1>; | |
140 | clock-output-names = "ahb1_mipidsi", "ahb1_ss", | |
141 | "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1", | |
142 | "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1", | |
143 | "ahb1_nand0", "ahb1_sdram", | |
144 | "ahb1_gmac", "ahb1_ts", "ahb1_hstimer", | |
145 | "ahb1_spi0", "ahb1_spi1", "ahb1_spi2", | |
146 | "ahb1_spi3", "ahb1_otg", "ahb1_ehci0", | |
147 | "ahb1_ehci1", "ahb1_ohci0", | |
148 | "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve", | |
149 | "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi", | |
150 | "ahb1_hdmi", "ahb1_de0", "ahb1_de1", | |
151 | "ahb1_fe0", "ahb1_fe1", "ahb1_mp", | |
152 | "ahb1_gpu", "ahb1_deu0", "ahb1_deu1", | |
153 | "ahb1_drc0", "ahb1_drc1"; | |
154 | }; | |
155 | ||
156 | apb1: apb1@01c20054 { | |
157 | #clock-cells = <0>; | |
bf6534a1 | 158 | compatible = "allwinner,sun4i-a10-apb0-clk"; |
98096560 MR |
159 | reg = <0x01c20054 0x4>; |
160 | clocks = <&ahb1>; | |
7b5b2909 | 161 | clock-output-names = "apb1"; |
98096560 MR |
162 | }; |
163 | ||
7b5b2909 | 164 | apb1_gates: clk@01c20068 { |
98096560 MR |
165 | #clock-cells = <1>; |
166 | compatible = "allwinner,sun6i-a31-apb1-gates-clk"; | |
167 | reg = <0x01c20068 0x4>; | |
168 | clocks = <&apb1>; | |
169 | clock-output-names = "apb1_codec", "apb1_digital_mic", | |
170 | "apb1_pio", "apb1_daudio0", | |
171 | "apb1_daudio1"; | |
172 | }; | |
173 | ||
174 | apb2_mux: apb2_mux@01c20058 { | |
175 | #clock-cells = <0>; | |
bf6534a1 | 176 | compatible = "allwinner,sun4i-a10-apb1-mux-clk"; |
98096560 MR |
177 | reg = <0x01c20058 0x4>; |
178 | clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>; | |
7b5b2909 | 179 | clock-output-names = "apb2_mux"; |
98096560 MR |
180 | }; |
181 | ||
182 | apb2: apb2@01c20058 { | |
183 | #clock-cells = <0>; | |
184 | compatible = "allwinner,sun6i-a31-apb2-div-clk"; | |
185 | reg = <0x01c20058 0x4>; | |
186 | clocks = <&apb2_mux>; | |
7b5b2909 | 187 | clock-output-names = "apb2"; |
98096560 MR |
188 | }; |
189 | ||
7b5b2909 | 190 | apb2_gates: clk@01c2006c { |
98096560 MR |
191 | #clock-cells = <1>; |
192 | compatible = "allwinner,sun6i-a31-apb2-gates-clk"; | |
439d9f58 | 193 | reg = <0x01c2006c 0x4>; |
98096560 MR |
194 | clocks = <&apb2>; |
195 | clock-output-names = "apb2_i2c0", "apb2_i2c1", | |
196 | "apb2_i2c2", "apb2_i2c3", "apb2_uart0", | |
197 | "apb2_uart1", "apb2_uart2", "apb2_uart3", | |
198 | "apb2_uart4", "apb2_uart5"; | |
199 | }; | |
b0a09c75 MR |
200 | |
201 | spi0_clk: clk@01c200a0 { | |
202 | #clock-cells = <0>; | |
203 | compatible = "allwinner,sun4i-mod0-clk"; | |
204 | reg = <0x01c200a0 0x4>; | |
205 | clocks = <&osc24M>, <&pll6>; | |
206 | clock-output-names = "spi0"; | |
207 | }; | |
208 | ||
209 | spi1_clk: clk@01c200a4 { | |
210 | #clock-cells = <0>; | |
211 | compatible = "allwinner,sun4i-mod0-clk"; | |
212 | reg = <0x01c200a4 0x4>; | |
213 | clocks = <&osc24M>, <&pll6>; | |
214 | clock-output-names = "spi1"; | |
215 | }; | |
216 | ||
217 | spi2_clk: clk@01c200a8 { | |
218 | #clock-cells = <0>; | |
219 | compatible = "allwinner,sun4i-mod0-clk"; | |
220 | reg = <0x01c200a8 0x4>; | |
221 | clocks = <&osc24M>, <&pll6>; | |
222 | clock-output-names = "spi2"; | |
223 | }; | |
224 | ||
225 | spi3_clk: clk@01c200ac { | |
226 | #clock-cells = <0>; | |
227 | compatible = "allwinner,sun4i-mod0-clk"; | |
228 | reg = <0x01c200ac 0x4>; | |
229 | clocks = <&osc24M>, <&pll6>; | |
230 | clock-output-names = "spi3"; | |
231 | }; | |
8aed3b31 MR |
232 | }; |
233 | ||
234 | soc@01c00000 { | |
235 | compatible = "simple-bus"; | |
236 | #address-cells = <1>; | |
237 | #size-cells = <1>; | |
238 | ranges; | |
239 | ||
140e1721 MR |
240 | pio: pinctrl@01c20800 { |
241 | compatible = "allwinner,sun6i-a31-pinctrl"; | |
242 | reg = <0x01c20800 0x400>; | |
6f97dc8d MR |
243 | interrupts = <0 11 4>, |
244 | <0 15 4>, | |
245 | <0 16 4>, | |
246 | <0 17 4>; | |
98096560 | 247 | clocks = <&apb1_gates 5>; |
140e1721 MR |
248 | gpio-controller; |
249 | interrupt-controller; | |
250 | #address-cells = <1>; | |
251 | #size-cells = <0>; | |
252 | #gpio-cells = <3>; | |
ab4238cd MR |
253 | |
254 | uart0_pins_a: uart0@0 { | |
255 | allwinner,pins = "PH20", "PH21"; | |
256 | allwinner,function = "uart0"; | |
257 | allwinner,drive = <0>; | |
258 | allwinner,pull = <0>; | |
259 | }; | |
140e1721 MR |
260 | }; |
261 | ||
24a661e9 MR |
262 | ahb1_rst: reset@01c202c0 { |
263 | #reset-cells = <1>; | |
264 | compatible = "allwinner,sun6i-a31-ahb1-reset"; | |
265 | reg = <0x01c202c0 0xc>; | |
266 | }; | |
267 | ||
268 | apb1_rst: reset@01c202d0 { | |
269 | #reset-cells = <1>; | |
270 | compatible = "allwinner,sun6i-a31-clock-reset"; | |
271 | reg = <0x01c202d0 0x4>; | |
272 | }; | |
273 | ||
274 | apb2_rst: reset@01c202d8 { | |
275 | #reset-cells = <1>; | |
276 | compatible = "allwinner,sun6i-a31-clock-reset"; | |
277 | reg = <0x01c202d8 0x4>; | |
278 | }; | |
279 | ||
8aed3b31 MR |
280 | timer@01c20c00 { |
281 | compatible = "allwinner,sun4i-timer"; | |
282 | reg = <0x01c20c00 0xa0>; | |
6f97dc8d MR |
283 | interrupts = <0 18 4>, |
284 | <0 19 4>, | |
285 | <0 20 4>, | |
286 | <0 21 4>, | |
287 | <0 22 4>; | |
98096560 | 288 | clocks = <&osc24M>; |
8aed3b31 MR |
289 | }; |
290 | ||
291 | wdt1: watchdog@01c20ca0 { | |
292 | compatible = "allwinner,sun6i-wdt"; | |
293 | reg = <0x01c20ca0 0x20>; | |
294 | }; | |
295 | ||
296 | uart0: serial@01c28000 { | |
297 | compatible = "snps,dw-apb-uart"; | |
298 | reg = <0x01c28000 0x400>; | |
6f97dc8d | 299 | interrupts = <0 0 4>; |
8aed3b31 MR |
300 | reg-shift = <2>; |
301 | reg-io-width = <4>; | |
98096560 | 302 | clocks = <&apb2_gates 16>; |
24a661e9 | 303 | resets = <&apb2_rst 16>; |
8aed3b31 MR |
304 | status = "disabled"; |
305 | }; | |
306 | ||
307 | uart1: serial@01c28400 { | |
308 | compatible = "snps,dw-apb-uart"; | |
309 | reg = <0x01c28400 0x400>; | |
6f97dc8d | 310 | interrupts = <0 1 4>; |
8aed3b31 MR |
311 | reg-shift = <2>; |
312 | reg-io-width = <4>; | |
98096560 | 313 | clocks = <&apb2_gates 17>; |
24a661e9 | 314 | resets = <&apb2_rst 17>; |
8aed3b31 MR |
315 | status = "disabled"; |
316 | }; | |
317 | ||
318 | uart2: serial@01c28800 { | |
319 | compatible = "snps,dw-apb-uart"; | |
320 | reg = <0x01c28800 0x400>; | |
6f97dc8d | 321 | interrupts = <0 2 4>; |
8aed3b31 MR |
322 | reg-shift = <2>; |
323 | reg-io-width = <4>; | |
98096560 | 324 | clocks = <&apb2_gates 18>; |
24a661e9 | 325 | resets = <&apb2_rst 18>; |
8aed3b31 MR |
326 | status = "disabled"; |
327 | }; | |
328 | ||
329 | uart3: serial@01c28c00 { | |
330 | compatible = "snps,dw-apb-uart"; | |
331 | reg = <0x01c28c00 0x400>; | |
6f97dc8d | 332 | interrupts = <0 3 4>; |
8aed3b31 MR |
333 | reg-shift = <2>; |
334 | reg-io-width = <4>; | |
98096560 | 335 | clocks = <&apb2_gates 19>; |
24a661e9 | 336 | resets = <&apb2_rst 19>; |
8aed3b31 MR |
337 | status = "disabled"; |
338 | }; | |
339 | ||
340 | uart4: serial@01c29000 { | |
341 | compatible = "snps,dw-apb-uart"; | |
342 | reg = <0x01c29000 0x400>; | |
6f97dc8d | 343 | interrupts = <0 4 4>; |
8aed3b31 MR |
344 | reg-shift = <2>; |
345 | reg-io-width = <4>; | |
98096560 | 346 | clocks = <&apb2_gates 20>; |
24a661e9 | 347 | resets = <&apb2_rst 20>; |
8aed3b31 MR |
348 | status = "disabled"; |
349 | }; | |
350 | ||
351 | uart5: serial@01c29400 { | |
352 | compatible = "snps,dw-apb-uart"; | |
353 | reg = <0x01c29400 0x400>; | |
6f97dc8d | 354 | interrupts = <0 5 4>; |
8aed3b31 MR |
355 | reg-shift = <2>; |
356 | reg-io-width = <4>; | |
98096560 | 357 | clocks = <&apb2_gates 21>; |
24a661e9 | 358 | resets = <&apb2_rst 21>; |
8aed3b31 MR |
359 | status = "disabled"; |
360 | }; | |
361 | ||
0d6efe33 MR |
362 | spi0: spi@01c68000 { |
363 | compatible = "allwinner,sun6i-a31-spi"; | |
364 | reg = <0x01c68000 0x1000>; | |
365 | interrupts = <0 65 4>; | |
366 | clocks = <&ahb1_gates 20>, <&spi0_clk>; | |
367 | clock-names = "ahb", "mod"; | |
368 | resets = <&ahb1_rst 20>; | |
369 | status = "disabled"; | |
370 | }; | |
371 | ||
372 | spi1: spi@01c69000 { | |
373 | compatible = "allwinner,sun6i-a31-spi"; | |
374 | reg = <0x01c69000 0x1000>; | |
375 | interrupts = <0 66 4>; | |
376 | clocks = <&ahb1_gates 21>, <&spi1_clk>; | |
377 | clock-names = "ahb", "mod"; | |
378 | resets = <&ahb1_rst 21>; | |
379 | status = "disabled"; | |
380 | }; | |
381 | ||
382 | spi2: spi@01c6a000 { | |
383 | compatible = "allwinner,sun6i-a31-spi"; | |
384 | reg = <0x01c6a000 0x1000>; | |
385 | interrupts = <0 67 4>; | |
386 | clocks = <&ahb1_gates 22>, <&spi2_clk>; | |
387 | clock-names = "ahb", "mod"; | |
388 | resets = <&ahb1_rst 22>; | |
389 | status = "disabled"; | |
390 | }; | |
391 | ||
392 | spi3: spi@01c6b000 { | |
393 | compatible = "allwinner,sun6i-a31-spi"; | |
394 | reg = <0x01c6b000 0x1000>; | |
395 | interrupts = <0 68 4>; | |
396 | clocks = <&ahb1_gates 23>, <&spi3_clk>; | |
397 | clock-names = "ahb", "mod"; | |
398 | resets = <&ahb1_rst 23>; | |
399 | status = "disabled"; | |
400 | }; | |
401 | ||
8aed3b31 MR |
402 | gic: interrupt-controller@01c81000 { |
403 | compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; | |
404 | reg = <0x01c81000 0x1000>, | |
405 | <0x01c82000 0x1000>, | |
406 | <0x01c84000 0x2000>, | |
407 | <0x01c86000 0x2000>; | |
408 | interrupt-controller; | |
409 | #interrupt-cells = <3>; | |
410 | interrupts = <1 9 0xf04>; | |
411 | }; | |
81ee429f MR |
412 | |
413 | cpucfg@01f01c00 { | |
414 | compatible = "allwinner,sun6i-a31-cpuconfig"; | |
415 | reg = <0x01f01c00 0x300>; | |
416 | }; | |
417 | ||
418 | prcm@01f01c00 { | |
419 | compatible = "allwinner,sun6i-a31-prcm"; | |
420 | reg = <0x01f01400 0x200>; | |
421 | }; | |
8aed3b31 MR |
422 | }; |
423 | }; |