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4790ecfa MR |
1 | /* |
2 | * Copyright 2013 Maxime Ripard | |
3 | * | |
4 | * Maxime Ripard <maxime.ripard@free-electrons.com> | |
5 | * | |
394c56ce MR |
6 | * This file is dual-licensed: you can use it either under the terms |
7 | * of the GPL or the X11 license, at your option. Note that this dual | |
8 | * licensing only applies to this file, and not this project as a | |
9 | * whole. | |
4790ecfa | 10 | * |
5186d83a | 11 | * a) This file is free software; you can redistribute it and/or |
394c56ce MR |
12 | * modify it under the terms of the GNU General Public License as |
13 | * published by the Free Software Foundation; either version 2 of the | |
14 | * License, or (at your option) any later version. | |
15 | * | |
5186d83a | 16 | * This file is distributed in the hope that it will be useful, |
394c56ce MR |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
394c56ce MR |
21 | * Or, alternatively, |
22 | * | |
23 | * b) Permission is hereby granted, free of charge, to any person | |
24 | * obtaining a copy of this software and associated documentation | |
25 | * files (the "Software"), to deal in the Software without | |
26 | * restriction, including without limitation the rights to use, | |
27 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
28 | * sell copies of the Software, and to permit persons to whom the | |
29 | * Software is furnished to do so, subject to the following | |
30 | * conditions: | |
31 | * | |
32 | * The above copyright notice and this permission notice shall be | |
33 | * included in all copies or substantial portions of the Software. | |
34 | * | |
35 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
36 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
37 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
38 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
39 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
40 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
41 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
42 | * OTHER DEALINGS IN THE SOFTWARE. | |
4790ecfa MR |
43 | */ |
44 | ||
71455701 | 45 | #include "skeleton.dtsi" |
4790ecfa | 46 | |
19882b84 | 47 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
b6d34248 | 48 | #include <dt-bindings/thermal/thermal.h> |
19882b84 | 49 | |
dbe4dd1e | 50 | #include <dt-bindings/clock/sun4i-a10-pll2.h> |
1f9f6a78 | 51 | #include <dt-bindings/dma/sun4i-a10.h> |
092a0c3b | 52 | #include <dt-bindings/pinctrl/sun4i-a10.h> |
4790ecfa MR |
53 | |
54 | / { | |
55 | interrupt-parent = <&gic>; | |
56 | ||
e751cce9 | 57 | aliases { |
18428f77 | 58 | ethernet0 = &gmac; |
e751cce9 EL |
59 | }; |
60 | ||
8efc5c2b HG |
61 | chosen { |
62 | #address-cells = <1>; | |
63 | #size-cells = <1>; | |
64 | ranges; | |
65 | ||
a9f8cda3 | 66 | framebuffer@0 { |
d8cacaa3 MR |
67 | compatible = "allwinner,simple-framebuffer", |
68 | "simple-framebuffer"; | |
a9f8cda3 | 69 | allwinner,pipeline = "de_be0-lcd0-hdmi"; |
678e75d3 | 70 | clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, |
0b4bf5a5 | 71 | <&ahb_gates 44>, <&dram_gates 26>; |
8efc5c2b HG |
72 | status = "disabled"; |
73 | }; | |
fd18c7ea HG |
74 | |
75 | framebuffer@1 { | |
76 | compatible = "allwinner,simple-framebuffer", | |
77 | "simple-framebuffer"; | |
78 | allwinner,pipeline = "de_be0-lcd0"; | |
0b4bf5a5 CYT |
79 | clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>, |
80 | <&dram_gates 26>; | |
fd18c7ea HG |
81 | status = "disabled"; |
82 | }; | |
83 | ||
84 | framebuffer@2 { | |
85 | compatible = "allwinner,simple-framebuffer", | |
86 | "simple-framebuffer"; | |
87 | allwinner,pipeline = "de_be0-lcd0-tve0"; | |
88 | clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>, | |
0b4bf5a5 | 89 | <&ahb_gates 44>, <&dram_gates 26>; |
fd18c7ea HG |
90 | status = "disabled"; |
91 | }; | |
8efc5c2b HG |
92 | }; |
93 | ||
4790ecfa MR |
94 | cpus { |
95 | #address-cells = <1>; | |
96 | #size-cells = <0>; | |
97 | ||
d96b7161 | 98 | cpu0: cpu@0 { |
4790ecfa MR |
99 | compatible = "arm,cortex-a7"; |
100 | device_type = "cpu"; | |
101 | reg = <0>; | |
d96b7161 CYT |
102 | clocks = <&cpu>; |
103 | clock-latency = <244144>; /* 8 32k periods */ | |
104 | operating-points = < | |
8358aada MR |
105 | /* kHz uV */ |
106 | 960000 1400000 | |
107 | 912000 1400000 | |
108 | 864000 1300000 | |
109 | 720000 1200000 | |
110 | 528000 1100000 | |
111 | 312000 1000000 | |
eaeef1ad | 112 | 144000 1000000 |
d96b7161 CYT |
113 | >; |
114 | #cooling-cells = <2>; | |
115 | cooling-min-level = <0>; | |
370a9b5f | 116 | cooling-max-level = <6>; |
4790ecfa MR |
117 | }; |
118 | ||
119 | cpu@1 { | |
120 | compatible = "arm,cortex-a7"; | |
121 | device_type = "cpu"; | |
122 | reg = <1>; | |
123 | }; | |
124 | }; | |
125 | ||
b6d34248 CYT |
126 | thermal-zones { |
127 | cpu_thermal { | |
128 | /* milliseconds */ | |
129 | polling-delay-passive = <250>; | |
130 | polling-delay = <1000>; | |
131 | thermal-sensors = <&rtp>; | |
132 | ||
133 | cooling-maps { | |
134 | map0 { | |
135 | trip = <&cpu_alert0>; | |
136 | cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
137 | }; | |
138 | }; | |
139 | ||
140 | trips { | |
141 | cpu_alert0: cpu_alert0 { | |
142 | /* milliCelsius */ | |
143 | temperature = <75000>; | |
144 | hysteresis = <2000>; | |
145 | type = "passive"; | |
146 | }; | |
147 | ||
148 | cpu_crit: cpu_crit { | |
149 | /* milliCelsius */ | |
150 | temperature = <100000>; | |
151 | hysteresis = <2000>; | |
152 | type = "critical"; | |
153 | }; | |
154 | }; | |
155 | }; | |
156 | }; | |
157 | ||
4790ecfa MR |
158 | memory { |
159 | reg = <0x40000000 0x80000000>; | |
160 | }; | |
161 | ||
7902763e MZ |
162 | timer { |
163 | compatible = "arm,armv7-timer"; | |
19882b84 MR |
164 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
165 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
166 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
167 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; | |
7902763e MZ |
168 | }; |
169 | ||
e29ea4d3 MR |
170 | pmu { |
171 | compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu"; | |
19882b84 MR |
172 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, |
173 | <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; | |
e29ea4d3 MR |
174 | }; |
175 | ||
4790ecfa MR |
176 | clocks { |
177 | #address-cells = <1>; | |
178 | #size-cells = <1>; | |
179 | ranges; | |
180 | ||
06067a2f | 181 | osc24M: clk@01c20050 { |
4790ecfa | 182 | #clock-cells = <0>; |
bf6534a1 | 183 | compatible = "allwinner,sun4i-a10-osc-clk"; |
de7dc935 | 184 | reg = <0x01c20050 0x4>; |
4790ecfa | 185 | clock-frequency = <24000000>; |
06067a2f | 186 | clock-output-names = "osc24M"; |
4790ecfa MR |
187 | }; |
188 | ||
673fac74 | 189 | osc32k: clk@0 { |
4790ecfa MR |
190 | #clock-cells = <0>; |
191 | compatible = "fixed-clock"; | |
192 | clock-frequency = <32768>; | |
673fac74 | 193 | clock-output-names = "osc32k"; |
4790ecfa | 194 | }; |
de7dc935 | 195 | |
06067a2f | 196 | pll1: clk@01c20000 { |
de7dc935 | 197 | #clock-cells = <0>; |
bf6534a1 | 198 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
de7dc935 MR |
199 | reg = <0x01c20000 0x4>; |
200 | clocks = <&osc24M>; | |
06067a2f | 201 | clock-output-names = "pll1"; |
de7dc935 MR |
202 | }; |
203 | ||
88a86aaa MR |
204 | pll2: clk@01c20008 { |
205 | #clock-cells = <1>; | |
206 | compatible = "allwinner,sun4i-a10-pll2-clk"; | |
207 | reg = <0x01c20008 0x8>; | |
208 | clocks = <&osc24M>; | |
209 | clock-output-names = "pll2-1x", "pll2-2x", | |
210 | "pll2-4x", "pll2-8x"; | |
211 | }; | |
212 | ||
06067a2f | 213 | pll4: clk@01c20018 { |
de7dc935 | 214 | #clock-cells = <0>; |
04ebcb54 | 215 | compatible = "allwinner,sun7i-a20-pll4-clk"; |
ec5589f7 EL |
216 | reg = <0x01c20018 0x4>; |
217 | clocks = <&osc24M>; | |
06067a2f | 218 | clock-output-names = "pll4"; |
ec5589f7 EL |
219 | }; |
220 | ||
06067a2f | 221 | pll5: clk@01c20020 { |
c3e5e66b | 222 | #clock-cells = <1>; |
bf6534a1 | 223 | compatible = "allwinner,sun4i-a10-pll5-clk"; |
c3e5e66b EL |
224 | reg = <0x01c20020 0x4>; |
225 | clocks = <&osc24M>; | |
226 | clock-output-names = "pll5_ddr", "pll5_other"; | |
227 | }; | |
228 | ||
06067a2f | 229 | pll6: clk@01c20028 { |
c3e5e66b | 230 | #clock-cells = <1>; |
bf6534a1 | 231 | compatible = "allwinner,sun4i-a10-pll6-clk"; |
c3e5e66b EL |
232 | reg = <0x01c20028 0x4>; |
233 | clocks = <&osc24M>; | |
2186df37 CYT |
234 | clock-output-names = "pll6_sata", "pll6_other", "pll6", |
235 | "pll6_div_4"; | |
de7dc935 MR |
236 | }; |
237 | ||
04ebcb54 EL |
238 | pll8: clk@01c20040 { |
239 | #clock-cells = <0>; | |
240 | compatible = "allwinner,sun7i-a20-pll4-clk"; | |
241 | reg = <0x01c20040 0x4>; | |
242 | clocks = <&osc24M>; | |
243 | clock-output-names = "pll8"; | |
244 | }; | |
245 | ||
de7dc935 MR |
246 | cpu: cpu@01c20054 { |
247 | #clock-cells = <0>; | |
bf6534a1 | 248 | compatible = "allwinner,sun4i-a10-cpu-clk"; |
de7dc935 | 249 | reg = <0x01c20054 0x4>; |
c3e5e66b | 250 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>; |
06067a2f | 251 | clock-output-names = "cpu"; |
de7dc935 MR |
252 | }; |
253 | ||
254 | axi: axi@01c20054 { | |
255 | #clock-cells = <0>; | |
bf6534a1 | 256 | compatible = "allwinner,sun4i-a10-axi-clk"; |
de7dc935 MR |
257 | reg = <0x01c20054 0x4>; |
258 | clocks = <&cpu>; | |
06067a2f | 259 | clock-output-names = "axi"; |
de7dc935 MR |
260 | }; |
261 | ||
262 | ahb: ahb@01c20054 { | |
263 | #clock-cells = <0>; | |
2186df37 | 264 | compatible = "allwinner,sun5i-a13-ahb-clk"; |
de7dc935 | 265 | reg = <0x01c20054 0x4>; |
2186df37 | 266 | clocks = <&axi>, <&pll6 3>, <&pll6 1>; |
06067a2f | 267 | clock-output-names = "ahb"; |
2186df37 CYT |
268 | /* |
269 | * Use PLL6 as parent, instead of CPU/AXI | |
270 | * which has rate changes due to cpufreq | |
271 | */ | |
272 | assigned-clocks = <&ahb>; | |
273 | assigned-clock-parents = <&pll6 3>; | |
de7dc935 MR |
274 | }; |
275 | ||
06067a2f | 276 | ahb_gates: clk@01c20060 { |
de7dc935 MR |
277 | #clock-cells = <1>; |
278 | compatible = "allwinner,sun7i-a20-ahb-gates-clk"; | |
279 | reg = <0x01c20060 0x8>; | |
280 | clocks = <&ahb>; | |
6bfe30b2 MR |
281 | clock-indices = <0>, <1>, |
282 | <2>, <3>, <4>, | |
283 | <5>, <6>, <7>, <8>, | |
284 | <9>, <10>, <11>, <12>, | |
285 | <13>, <14>, <16>, | |
286 | <17>, <18>, <20>, <21>, | |
287 | <22>, <23>, <25>, | |
288 | <28>, <32>, <33>, <34>, | |
289 | <35>, <36>, <37>, <40>, | |
290 | <41>, <42>, <43>, | |
291 | <44>, <45>, <46>, | |
292 | <47>, <49>, <50>, | |
293 | <52>; | |
de7dc935 MR |
294 | clock-output-names = "ahb_usb0", "ahb_ehci0", |
295 | "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", | |
296 | "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0", | |
297 | "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms", | |
298 | "ahb_nand", "ahb_sdram", "ahb_ace", | |
299 | "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1", | |
300 | "ahb_spi2", "ahb_spi3", "ahb_sata", | |
301 | "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0", | |
302 | "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0", | |
303 | "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0", | |
304 | "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0", | |
305 | "ahb_de_fe1", "ahb_gmac", "ahb_mp", | |
306 | "ahb_mali"; | |
307 | }; | |
308 | ||
309 | apb0: apb0@01c20054 { | |
310 | #clock-cells = <0>; | |
bf6534a1 | 311 | compatible = "allwinner,sun4i-a10-apb0-clk"; |
de7dc935 MR |
312 | reg = <0x01c20054 0x4>; |
313 | clocks = <&ahb>; | |
06067a2f | 314 | clock-output-names = "apb0"; |
de7dc935 MR |
315 | }; |
316 | ||
06067a2f | 317 | apb0_gates: clk@01c20068 { |
de7dc935 MR |
318 | #clock-cells = <1>; |
319 | compatible = "allwinner,sun7i-a20-apb0-gates-clk"; | |
320 | reg = <0x01c20068 0x4>; | |
321 | clocks = <&apb0>; | |
6bfe30b2 MR |
322 | clock-indices = <0>, <1>, |
323 | <2>, <3>, <4>, | |
324 | <5>, <6>, <7>, | |
325 | <8>, <10>; | |
de7dc935 MR |
326 | clock-output-names = "apb0_codec", "apb0_spdif", |
327 | "apb0_ac97", "apb0_iis0", "apb0_iis1", | |
328 | "apb0_pio", "apb0_ir0", "apb0_ir1", | |
329 | "apb0_iis2", "apb0_keypad"; | |
330 | }; | |
331 | ||
acbcc0f0 | 332 | apb1: clk@01c20058 { |
de7dc935 | 333 | #clock-cells = <0>; |
bf6534a1 | 334 | compatible = "allwinner,sun4i-a10-apb1-clk"; |
de7dc935 | 335 | reg = <0x01c20058 0x4>; |
acbcc0f0 | 336 | clocks = <&osc24M>, <&pll6 1>, <&osc32k>; |
06067a2f | 337 | clock-output-names = "apb1"; |
de7dc935 MR |
338 | }; |
339 | ||
06067a2f | 340 | apb1_gates: clk@01c2006c { |
de7dc935 MR |
341 | #clock-cells = <1>; |
342 | compatible = "allwinner,sun7i-a20-apb1-gates-clk"; | |
343 | reg = <0x01c2006c 0x4>; | |
344 | clocks = <&apb1>; | |
6bfe30b2 MR |
345 | clock-indices = <0>, <1>, |
346 | <2>, <3>, <4>, | |
347 | <5>, <6>, <7>, | |
348 | <15>, <16>, <17>, | |
349 | <18>, <19>, <20>, | |
350 | <21>, <22>, <23>; | |
de7dc935 MR |
351 | clock-output-names = "apb1_i2c0", "apb1_i2c1", |
352 | "apb1_i2c2", "apb1_i2c3", "apb1_can", | |
353 | "apb1_scr", "apb1_ps20", "apb1_ps21", | |
354 | "apb1_i2c4", "apb1_uart0", "apb1_uart1", | |
355 | "apb1_uart2", "apb1_uart3", "apb1_uart4", | |
356 | "apb1_uart5", "apb1_uart6", "apb1_uart7"; | |
357 | }; | |
1c92b95b EL |
358 | |
359 | nand_clk: clk@01c20080 { | |
360 | #clock-cells = <0>; | |
bf6534a1 | 361 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
1c92b95b EL |
362 | reg = <0x01c20080 0x4>; |
363 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
364 | clock-output-names = "nand"; | |
365 | }; | |
366 | ||
367 | ms_clk: clk@01c20084 { | |
368 | #clock-cells = <0>; | |
bf6534a1 | 369 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
1c92b95b EL |
370 | reg = <0x01c20084 0x4>; |
371 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
372 | clock-output-names = "ms"; | |
373 | }; | |
374 | ||
375 | mmc0_clk: clk@01c20088 { | |
d8c3a392 MR |
376 | #clock-cells = <1>; |
377 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
1c92b95b EL |
378 | reg = <0x01c20088 0x4>; |
379 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
d8c3a392 MR |
380 | clock-output-names = "mmc0", |
381 | "mmc0_output", | |
382 | "mmc0_sample"; | |
1c92b95b EL |
383 | }; |
384 | ||
385 | mmc1_clk: clk@01c2008c { | |
d8c3a392 MR |
386 | #clock-cells = <1>; |
387 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
1c92b95b EL |
388 | reg = <0x01c2008c 0x4>; |
389 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
d8c3a392 MR |
390 | clock-output-names = "mmc1", |
391 | "mmc1_output", | |
392 | "mmc1_sample"; | |
1c92b95b EL |
393 | }; |
394 | ||
395 | mmc2_clk: clk@01c20090 { | |
d8c3a392 MR |
396 | #clock-cells = <1>; |
397 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
1c92b95b EL |
398 | reg = <0x01c20090 0x4>; |
399 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
d8c3a392 MR |
400 | clock-output-names = "mmc2", |
401 | "mmc2_output", | |
402 | "mmc2_sample"; | |
1c92b95b EL |
403 | }; |
404 | ||
405 | mmc3_clk: clk@01c20094 { | |
d8c3a392 MR |
406 | #clock-cells = <1>; |
407 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
1c92b95b EL |
408 | reg = <0x01c20094 0x4>; |
409 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
d8c3a392 MR |
410 | clock-output-names = "mmc3", |
411 | "mmc3_output", | |
412 | "mmc3_sample"; | |
1c92b95b EL |
413 | }; |
414 | ||
415 | ts_clk: clk@01c20098 { | |
416 | #clock-cells = <0>; | |
bf6534a1 | 417 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
1c92b95b EL |
418 | reg = <0x01c20098 0x4>; |
419 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
420 | clock-output-names = "ts"; | |
421 | }; | |
422 | ||
423 | ss_clk: clk@01c2009c { | |
424 | #clock-cells = <0>; | |
bf6534a1 | 425 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
1c92b95b EL |
426 | reg = <0x01c2009c 0x4>; |
427 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
428 | clock-output-names = "ss"; | |
429 | }; | |
430 | ||
431 | spi0_clk: clk@01c200a0 { | |
432 | #clock-cells = <0>; | |
bf6534a1 | 433 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
1c92b95b EL |
434 | reg = <0x01c200a0 0x4>; |
435 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
436 | clock-output-names = "spi0"; | |
437 | }; | |
438 | ||
439 | spi1_clk: clk@01c200a4 { | |
440 | #clock-cells = <0>; | |
bf6534a1 | 441 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
1c92b95b EL |
442 | reg = <0x01c200a4 0x4>; |
443 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
444 | clock-output-names = "spi1"; | |
445 | }; | |
446 | ||
447 | spi2_clk: clk@01c200a8 { | |
448 | #clock-cells = <0>; | |
bf6534a1 | 449 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
1c92b95b EL |
450 | reg = <0x01c200a8 0x4>; |
451 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
452 | clock-output-names = "spi2"; | |
453 | }; | |
454 | ||
455 | pata_clk: clk@01c200ac { | |
456 | #clock-cells = <0>; | |
bf6534a1 | 457 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
1c92b95b EL |
458 | reg = <0x01c200ac 0x4>; |
459 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
460 | clock-output-names = "pata"; | |
461 | }; | |
462 | ||
463 | ir0_clk: clk@01c200b0 { | |
464 | #clock-cells = <0>; | |
bf6534a1 | 465 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
1c92b95b EL |
466 | reg = <0x01c200b0 0x4>; |
467 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
468 | clock-output-names = "ir0"; | |
469 | }; | |
470 | ||
471 | ir1_clk: clk@01c200b4 { | |
472 | #clock-cells = <0>; | |
bf6534a1 | 473 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
1c92b95b EL |
474 | reg = <0x01c200b4 0x4>; |
475 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
476 | clock-output-names = "ir1"; | |
477 | }; | |
478 | ||
6f1606bf YJ |
479 | keypad_clk: clk@01c200c4 { |
480 | #clock-cells = <0>; | |
481 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
482 | reg = <0x01c200c4 0x4>; | |
483 | clocks = <&osc24M>; | |
484 | clock-output-names = "keypad"; | |
485 | }; | |
486 | ||
434e41b3 RB |
487 | usb_clk: clk@01c200cc { |
488 | #clock-cells = <1>; | |
8358aada | 489 | #reset-cells = <1>; |
434e41b3 RB |
490 | compatible = "allwinner,sun4i-a10-usb-clk"; |
491 | reg = <0x01c200cc 0x4>; | |
492 | clocks = <&pll6 1>; | |
d8cacaa3 MR |
493 | clock-output-names = "usb_ohci0", "usb_ohci1", |
494 | "usb_phy"; | |
434e41b3 RB |
495 | }; |
496 | ||
1c92b95b EL |
497 | spi3_clk: clk@01c200d4 { |
498 | #clock-cells = <0>; | |
bf6534a1 | 499 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
1c92b95b EL |
500 | reg = <0x01c200d4 0x4>; |
501 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
502 | clock-output-names = "spi3"; | |
503 | }; | |
118c07ae | 504 | |
0b4bf5a5 CYT |
505 | dram_gates: clk@01c20100 { |
506 | #clock-cells = <1>; | |
507 | compatible = "allwinner,sun4i-a10-dram-gates-clk"; | |
508 | reg = <0x01c20100 0x4>; | |
509 | clocks = <&pll5 0>; | |
510 | clock-indices = <0>, | |
511 | <1>, <2>, | |
512 | <3>, | |
513 | <4>, | |
514 | <5>, <6>, | |
515 | <15>, | |
516 | <24>, <25>, | |
517 | <26>, <27>, | |
518 | <28>, <29>; | |
519 | clock-output-names = "dram_ve", | |
520 | "dram_csi0", "dram_csi1", | |
521 | "dram_ts", | |
522 | "dram_tvd", | |
523 | "dram_tve0", "dram_tve1", | |
524 | "dram_output", | |
525 | "dram_de_fe1", "dram_de_fe0", | |
526 | "dram_de_be0", "dram_de_be1", | |
527 | "dram_de_mp", "dram_ace"; | |
528 | }; | |
529 | ||
dbe4dd1e MR |
530 | codec_clk: clk@01c20140 { |
531 | #clock-cells = <0>; | |
532 | compatible = "allwinner,sun4i-a10-codec-clk"; | |
533 | reg = <0x01c20140 0x4>; | |
534 | clocks = <&pll2 SUN4I_A10_PLL2_1X>; | |
535 | clock-output-names = "codec"; | |
536 | }; | |
537 | ||
118c07ae EL |
538 | mbus_clk: clk@01c2015c { |
539 | #clock-cells = <0>; | |
7868c5eb | 540 | compatible = "allwinner,sun5i-a13-mbus-clk"; |
118c07ae EL |
541 | reg = <0x01c2015c 0x4>; |
542 | clocks = <&osc24M>, <&pll6 2>, <&pll5 1>; | |
543 | clock-output-names = "mbus"; | |
544 | }; | |
0aff0370 | 545 | |
daed5a81 | 546 | /* |
d8cacaa3 MR |
547 | * The following two are dummy clocks, placeholders |
548 | * used in the gmac_tx clock. The gmac driver will | |
549 | * choose one parent depending on the PHY interface | |
550 | * mode, using clk_set_rate auto-reparenting. | |
551 | * | |
552 | * The actual TX clock rate is not controlled by the | |
553 | * gmac_tx clock. | |
daed5a81 CYT |
554 | */ |
555 | mii_phy_tx_clk: clk@2 { | |
556 | #clock-cells = <0>; | |
557 | compatible = "fixed-clock"; | |
558 | clock-frequency = <25000000>; | |
559 | clock-output-names = "mii_phy_tx"; | |
560 | }; | |
561 | ||
562 | gmac_int_tx_clk: clk@3 { | |
563 | #clock-cells = <0>; | |
564 | compatible = "fixed-clock"; | |
565 | clock-frequency = <125000000>; | |
566 | clock-output-names = "gmac_int_tx"; | |
567 | }; | |
568 | ||
569 | gmac_tx_clk: clk@01c20164 { | |
570 | #clock-cells = <0>; | |
571 | compatible = "allwinner,sun7i-a20-gmac-clk"; | |
572 | reg = <0x01c20164 0x4>; | |
573 | clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; | |
574 | clock-output-names = "gmac_tx"; | |
575 | }; | |
576 | ||
0aff0370 CYT |
577 | /* |
578 | * Dummy clock used by output clocks | |
579 | */ | |
580 | osc24M_32k: clk@1 { | |
581 | #clock-cells = <0>; | |
582 | compatible = "fixed-factor-clock"; | |
583 | clock-div = <750>; | |
584 | clock-mult = <1>; | |
585 | clocks = <&osc24M>; | |
586 | clock-output-names = "osc24M_32k"; | |
587 | }; | |
588 | ||
589 | clk_out_a: clk@01c201f0 { | |
590 | #clock-cells = <0>; | |
591 | compatible = "allwinner,sun7i-a20-out-clk"; | |
592 | reg = <0x01c201f0 0x4>; | |
593 | clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; | |
594 | clock-output-names = "clk_out_a"; | |
595 | }; | |
596 | ||
597 | clk_out_b: clk@01c201f4 { | |
598 | #clock-cells = <0>; | |
599 | compatible = "allwinner,sun7i-a20-out-clk"; | |
600 | reg = <0x01c201f4 0x4>; | |
601 | clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; | |
602 | clock-output-names = "clk_out_b"; | |
603 | }; | |
4790ecfa MR |
604 | }; |
605 | ||
606 | soc@01c00000 { | |
607 | compatible = "simple-bus"; | |
608 | #address-cells = <1>; | |
609 | #size-cells = <1>; | |
610 | ranges; | |
611 | ||
0eb14a8d MR |
612 | sram-controller@01c00000 { |
613 | compatible = "allwinner,sun4i-a10-sram-controller"; | |
614 | reg = <0x01c00000 0x30>; | |
615 | #address-cells = <1>; | |
616 | #size-cells = <1>; | |
617 | ranges; | |
618 | ||
619 | sram_a: sram@00000000 { | |
620 | compatible = "mmio-sram"; | |
621 | reg = <0x00000000 0xc000>; | |
622 | #address-cells = <1>; | |
623 | #size-cells = <1>; | |
624 | ranges = <0 0x00000000 0xc000>; | |
625 | ||
626 | emac_sram: sram-section@8000 { | |
627 | compatible = "allwinner,sun4i-a10-sram-a3-a4"; | |
628 | reg = <0x8000 0x4000>; | |
629 | status = "disabled"; | |
630 | }; | |
631 | }; | |
632 | ||
633 | sram_d: sram@00010000 { | |
634 | compatible = "mmio-sram"; | |
635 | reg = <0x00010000 0x1000>; | |
636 | #address-cells = <1>; | |
637 | #size-cells = <1>; | |
638 | ranges = <0 0x00010000 0x1000>; | |
639 | ||
640 | otg_sram: sram-section@0000 { | |
641 | compatible = "allwinner,sun4i-a10-sram-d"; | |
642 | reg = <0x0000 0x1000>; | |
643 | status = "disabled"; | |
644 | }; | |
645 | }; | |
646 | }; | |
647 | ||
8ff973a2 CC |
648 | nmi_intc: interrupt-controller@01c00030 { |
649 | compatible = "allwinner,sun7i-a20-sc-nmi"; | |
650 | interrupt-controller; | |
651 | #interrupt-cells = <2>; | |
652 | reg = <0x01c00030 0x0c>; | |
19882b84 | 653 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; |
8ff973a2 CC |
654 | }; |
655 | ||
316e0b0e EL |
656 | dma: dma-controller@01c02000 { |
657 | compatible = "allwinner,sun4i-a10-dma"; | |
658 | reg = <0x01c02000 0x1000>; | |
19882b84 | 659 | interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; |
316e0b0e EL |
660 | clocks = <&ahb_gates 6>; |
661 | #dma-cells = <2>; | |
662 | }; | |
663 | ||
36ab3e73 MR |
664 | spi0: spi@01c05000 { |
665 | compatible = "allwinner,sun4i-a10-spi"; | |
666 | reg = <0x01c05000 0x1000>; | |
19882b84 | 667 | interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
36ab3e73 MR |
668 | clocks = <&ahb_gates 20>, <&spi0_clk>; |
669 | clock-names = "ahb", "mod"; | |
1f9f6a78 MR |
670 | dmas = <&dma SUN4I_DMA_DEDICATED 27>, |
671 | <&dma SUN4I_DMA_DEDICATED 26>; | |
ffec7210 | 672 | dma-names = "rx", "tx"; |
36ab3e73 MR |
673 | status = "disabled"; |
674 | #address-cells = <1>; | |
675 | #size-cells = <0>; | |
676 | }; | |
677 | ||
678 | spi1: spi@01c06000 { | |
679 | compatible = "allwinner,sun4i-a10-spi"; | |
680 | reg = <0x01c06000 0x1000>; | |
19882b84 | 681 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
36ab3e73 MR |
682 | clocks = <&ahb_gates 21>, <&spi1_clk>; |
683 | clock-names = "ahb", "mod"; | |
1f9f6a78 MR |
684 | dmas = <&dma SUN4I_DMA_DEDICATED 9>, |
685 | <&dma SUN4I_DMA_DEDICATED 8>; | |
ffec7210 | 686 | dma-names = "rx", "tx"; |
36ab3e73 MR |
687 | status = "disabled"; |
688 | #address-cells = <1>; | |
689 | #size-cells = <0>; | |
690 | }; | |
691 | ||
2e804d03 | 692 | emac: ethernet@01c0b000 { |
1c70e099 | 693 | compatible = "allwinner,sun4i-a10-emac"; |
2e804d03 | 694 | reg = <0x01c0b000 0x1000>; |
19882b84 | 695 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; |
2e804d03 | 696 | clocks = <&ahb_gates 17>; |
0eb14a8d | 697 | allwinner,sram = <&emac_sram 1>; |
2e804d03 MR |
698 | status = "disabled"; |
699 | }; | |
700 | ||
92395f56 | 701 | mdio: mdio@01c0b080 { |
1c70e099 | 702 | compatible = "allwinner,sun4i-a10-mdio"; |
2e804d03 MR |
703 | reg = <0x01c0b080 0x14>; |
704 | status = "disabled"; | |
705 | #address-cells = <1>; | |
706 | #size-cells = <0>; | |
707 | }; | |
708 | ||
dd29ce53 HG |
709 | mmc0: mmc@01c0f000 { |
710 | compatible = "allwinner,sun5i-a13-mmc"; | |
711 | reg = <0x01c0f000 0x1000>; | |
d8c3a392 MR |
712 | clocks = <&ahb_gates 8>, |
713 | <&mmc0_clk 0>, | |
714 | <&mmc0_clk 1>, | |
715 | <&mmc0_clk 2>; | |
716 | clock-names = "ahb", | |
717 | "mmc", | |
718 | "output", | |
719 | "sample"; | |
19882b84 | 720 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
dd29ce53 | 721 | status = "disabled"; |
4c1bb9c3 HG |
722 | #address-cells = <1>; |
723 | #size-cells = <0>; | |
dd29ce53 HG |
724 | }; |
725 | ||
726 | mmc1: mmc@01c10000 { | |
727 | compatible = "allwinner,sun5i-a13-mmc"; | |
728 | reg = <0x01c10000 0x1000>; | |
d8c3a392 MR |
729 | clocks = <&ahb_gates 9>, |
730 | <&mmc1_clk 0>, | |
731 | <&mmc1_clk 1>, | |
732 | <&mmc1_clk 2>; | |
733 | clock-names = "ahb", | |
734 | "mmc", | |
735 | "output", | |
736 | "sample"; | |
19882b84 | 737 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
dd29ce53 | 738 | status = "disabled"; |
4c1bb9c3 HG |
739 | #address-cells = <1>; |
740 | #size-cells = <0>; | |
dd29ce53 HG |
741 | }; |
742 | ||
743 | mmc2: mmc@01c11000 { | |
744 | compatible = "allwinner,sun5i-a13-mmc"; | |
745 | reg = <0x01c11000 0x1000>; | |
d8c3a392 MR |
746 | clocks = <&ahb_gates 10>, |
747 | <&mmc2_clk 0>, | |
748 | <&mmc2_clk 1>, | |
749 | <&mmc2_clk 2>; | |
750 | clock-names = "ahb", | |
751 | "mmc", | |
752 | "output", | |
753 | "sample"; | |
19882b84 | 754 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
dd29ce53 | 755 | status = "disabled"; |
4c1bb9c3 HG |
756 | #address-cells = <1>; |
757 | #size-cells = <0>; | |
dd29ce53 HG |
758 | }; |
759 | ||
760 | mmc3: mmc@01c12000 { | |
761 | compatible = "allwinner,sun5i-a13-mmc"; | |
762 | reg = <0x01c12000 0x1000>; | |
d8c3a392 MR |
763 | clocks = <&ahb_gates 11>, |
764 | <&mmc3_clk 0>, | |
765 | <&mmc3_clk 1>, | |
766 | <&mmc3_clk 2>; | |
767 | clock-names = "ahb", | |
768 | "mmc", | |
769 | "output", | |
770 | "sample"; | |
19882b84 | 771 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
dd29ce53 | 772 | status = "disabled"; |
4c1bb9c3 HG |
773 | #address-cells = <1>; |
774 | #size-cells = <0>; | |
dd29ce53 HG |
775 | }; |
776 | ||
cbb3ff1d RB |
777 | usb_otg: usb@01c13000 { |
778 | compatible = "allwinner,sun4i-a10-musb"; | |
779 | reg = <0x01c13000 0x0400>; | |
780 | clocks = <&ahb_gates 0>; | |
781 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; | |
782 | interrupt-names = "mc"; | |
783 | phys = <&usbphy 0>; | |
784 | phy-names = "usb"; | |
785 | extcon = <&usbphy 0>; | |
786 | allwinner,sram = <&otg_sram 1>; | |
787 | status = "disabled"; | |
788 | }; | |
789 | ||
9debd0a2 RB |
790 | usbphy: phy@01c13400 { |
791 | #phy-cells = <1>; | |
792 | compatible = "allwinner,sun7i-a20-usb-phy"; | |
793 | reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; | |
794 | reg-names = "phy_ctrl", "pmu1", "pmu2"; | |
795 | clocks = <&usb_clk 8>; | |
796 | clock-names = "usb_phy"; | |
134c60ad RB |
797 | resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>; |
798 | reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; | |
9debd0a2 RB |
799 | status = "disabled"; |
800 | }; | |
801 | ||
802 | ehci0: usb@01c14000 { | |
803 | compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; | |
804 | reg = <0x01c14000 0x100>; | |
19882b84 | 805 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; |
9debd0a2 RB |
806 | clocks = <&ahb_gates 1>; |
807 | phys = <&usbphy 1>; | |
808 | phy-names = "usb"; | |
809 | status = "disabled"; | |
810 | }; | |
811 | ||
812 | ohci0: usb@01c14400 { | |
813 | compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; | |
814 | reg = <0x01c14400 0x100>; | |
19882b84 | 815 | interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; |
9debd0a2 RB |
816 | clocks = <&usb_clk 6>, <&ahb_gates 2>; |
817 | phys = <&usbphy 1>; | |
818 | phy-names = "usb"; | |
819 | status = "disabled"; | |
820 | }; | |
821 | ||
110d4e25 LC |
822 | crypto: crypto-engine@01c15000 { |
823 | compatible = "allwinner,sun4i-a10-crypto"; | |
824 | reg = <0x01c15000 0x1000>; | |
825 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; | |
826 | clocks = <&ahb_gates 5>, <&ss_clk>; | |
827 | clock-names = "ahb", "mod"; | |
828 | }; | |
829 | ||
36ab3e73 MR |
830 | spi2: spi@01c17000 { |
831 | compatible = "allwinner,sun4i-a10-spi"; | |
832 | reg = <0x01c17000 0x1000>; | |
19882b84 | 833 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; |
36ab3e73 MR |
834 | clocks = <&ahb_gates 22>, <&spi2_clk>; |
835 | clock-names = "ahb", "mod"; | |
1f9f6a78 MR |
836 | dmas = <&dma SUN4I_DMA_DEDICATED 29>, |
837 | <&dma SUN4I_DMA_DEDICATED 28>; | |
ffec7210 | 838 | dma-names = "rx", "tx"; |
36ab3e73 MR |
839 | status = "disabled"; |
840 | #address-cells = <1>; | |
841 | #size-cells = <0>; | |
842 | }; | |
843 | ||
902febf9 HG |
844 | ahci: sata@01c18000 { |
845 | compatible = "allwinner,sun4i-a10-ahci"; | |
846 | reg = <0x01c18000 0x1000>; | |
19882b84 | 847 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; |
902febf9 HG |
848 | clocks = <&pll6 0>, <&ahb_gates 25>; |
849 | status = "disabled"; | |
850 | }; | |
851 | ||
9debd0a2 RB |
852 | ehci1: usb@01c1c000 { |
853 | compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; | |
854 | reg = <0x01c1c000 0x100>; | |
19882b84 | 855 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; |
9debd0a2 RB |
856 | clocks = <&ahb_gates 3>; |
857 | phys = <&usbphy 2>; | |
858 | phy-names = "usb"; | |
859 | status = "disabled"; | |
860 | }; | |
861 | ||
862 | ohci1: usb@01c1c400 { | |
863 | compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; | |
864 | reg = <0x01c1c400 0x100>; | |
19882b84 | 865 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
9debd0a2 RB |
866 | clocks = <&usb_clk 7>, <&ahb_gates 4>; |
867 | phys = <&usbphy 2>; | |
868 | phy-names = "usb"; | |
869 | status = "disabled"; | |
870 | }; | |
871 | ||
36ab3e73 MR |
872 | spi3: spi@01c1f000 { |
873 | compatible = "allwinner,sun4i-a10-spi"; | |
874 | reg = <0x01c1f000 0x1000>; | |
19882b84 | 875 | interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; |
36ab3e73 MR |
876 | clocks = <&ahb_gates 23>, <&spi3_clk>; |
877 | clock-names = "ahb", "mod"; | |
1f9f6a78 MR |
878 | dmas = <&dma SUN4I_DMA_DEDICATED 31>, |
879 | <&dma SUN4I_DMA_DEDICATED 30>; | |
ffec7210 | 880 | dma-names = "rx", "tx"; |
36ab3e73 | 881 | status = "disabled"; |
2e804d03 MR |
882 | #address-cells = <1>; |
883 | #size-cells = <0>; | |
884 | }; | |
885 | ||
17eac031 MR |
886 | pio: pinctrl@01c20800 { |
887 | compatible = "allwinner,sun7i-a20-pinctrl"; | |
888 | reg = <0x01c20800 0x400>; | |
19882b84 | 889 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; |
de7dc935 | 890 | clocks = <&apb0_gates 5>; |
17eac031 MR |
891 | gpio-controller; |
892 | interrupt-controller; | |
b03e0816 | 893 | #interrupt-cells = <3>; |
17eac031 | 894 | #gpio-cells = <3>; |
9f229ba9 | 895 | |
fd7898a2 AB |
896 | pwm0_pins_a: pwm0@0 { |
897 | allwinner,pins = "PB2"; | |
898 | allwinner,function = "pwm"; | |
092a0c3b MR |
899 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
900 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
fd7898a2 AB |
901 | }; |
902 | ||
903 | pwm1_pins_a: pwm1@0 { | |
904 | allwinner,pins = "PI3"; | |
905 | allwinner,function = "pwm"; | |
092a0c3b MR |
906 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
907 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
fd7898a2 AB |
908 | }; |
909 | ||
9f229ba9 MR |
910 | uart0_pins_a: uart0@0 { |
911 | allwinner,pins = "PB22", "PB23"; | |
912 | allwinner,function = "uart0"; | |
092a0c3b MR |
913 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
914 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
9f229ba9 MR |
915 | }; |
916 | ||
4261ec43 CYT |
917 | uart2_pins_a: uart2@0 { |
918 | allwinner,pins = "PI16", "PI17", "PI18", "PI19"; | |
919 | allwinner,function = "uart2"; | |
092a0c3b MR |
920 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
921 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
4261ec43 CYT |
922 | }; |
923 | ||
7b5bace3 WW |
924 | uart3_pins_a: uart3@0 { |
925 | allwinner,pins = "PG6", "PG7", "PG8", "PG9"; | |
926 | allwinner,function = "uart3"; | |
092a0c3b MR |
927 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
928 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
7b5bace3 WW |
929 | }; |
930 | ||
0510e4b5 HG |
931 | uart3_pins_b: uart3@1 { |
932 | allwinner,pins = "PH0", "PH1"; | |
933 | allwinner,function = "uart3"; | |
092a0c3b MR |
934 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
935 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
0510e4b5 HG |
936 | }; |
937 | ||
7b5bace3 WW |
938 | uart4_pins_a: uart4@0 { |
939 | allwinner,pins = "PG10", "PG11"; | |
940 | allwinner,function = "uart4"; | |
092a0c3b MR |
941 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
942 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
7b5bace3 WW |
943 | }; |
944 | ||
869afa7f MR |
945 | uart4_pins_b: uart4@1 { |
946 | allwinner,pins = "PH4", "PH5"; | |
947 | allwinner,function = "uart4"; | |
948 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
949 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
950 | }; | |
951 | ||
7b5bace3 WW |
952 | uart5_pins_a: uart5@0 { |
953 | allwinner,pins = "PI10", "PI11"; | |
954 | allwinner,function = "uart5"; | |
092a0c3b MR |
955 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
956 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
7b5bace3 WW |
957 | }; |
958 | ||
9f229ba9 MR |
959 | uart6_pins_a: uart6@0 { |
960 | allwinner,pins = "PI12", "PI13"; | |
961 | allwinner,function = "uart6"; | |
092a0c3b MR |
962 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
963 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
9f229ba9 MR |
964 | }; |
965 | ||
966 | uart7_pins_a: uart7@0 { | |
967 | allwinner,pins = "PI20", "PI21"; | |
968 | allwinner,function = "uart7"; | |
092a0c3b MR |
969 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
970 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
9f229ba9 | 971 | }; |
756084c5 | 972 | |
e5496a31 MR |
973 | i2c0_pins_a: i2c0@0 { |
974 | allwinner,pins = "PB0", "PB1"; | |
975 | allwinner,function = "i2c0"; | |
092a0c3b MR |
976 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
977 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
e5496a31 MR |
978 | }; |
979 | ||
980 | i2c1_pins_a: i2c1@0 { | |
981 | allwinner,pins = "PB18", "PB19"; | |
982 | allwinner,function = "i2c1"; | |
092a0c3b MR |
983 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
984 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
e5496a31 MR |
985 | }; |
986 | ||
987 | i2c2_pins_a: i2c2@0 { | |
988 | allwinner,pins = "PB20", "PB21"; | |
989 | allwinner,function = "i2c2"; | |
092a0c3b MR |
990 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
991 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
e5496a31 MR |
992 | }; |
993 | ||
7b5bace3 WW |
994 | i2c3_pins_a: i2c3@0 { |
995 | allwinner,pins = "PI0", "PI1"; | |
996 | allwinner,function = "i2c3"; | |
092a0c3b MR |
997 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
998 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
7b5bace3 WW |
999 | }; |
1000 | ||
756084c5 MR |
1001 | emac_pins_a: emac0@0 { |
1002 | allwinner,pins = "PA0", "PA1", "PA2", | |
1003 | "PA3", "PA4", "PA5", "PA6", | |
1004 | "PA7", "PA8", "PA9", "PA10", | |
1005 | "PA11", "PA12", "PA13", "PA14", | |
1006 | "PA15", "PA16"; | |
1007 | allwinner,function = "emac"; | |
092a0c3b MR |
1008 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
1009 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
756084c5 | 1010 | }; |
f2e0759e CYT |
1011 | |
1012 | clk_out_a_pins_a: clk_out_a@0 { | |
1013 | allwinner,pins = "PI12"; | |
1014 | allwinner,function = "clk_out_a"; | |
092a0c3b MR |
1015 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
1016 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
f2e0759e CYT |
1017 | }; |
1018 | ||
1019 | clk_out_b_pins_a: clk_out_b@0 { | |
1020 | allwinner,pins = "PI13"; | |
1021 | allwinner,function = "clk_out_b"; | |
092a0c3b MR |
1022 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
1023 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
f2e0759e | 1024 | }; |
129ccbcd CYT |
1025 | |
1026 | gmac_pins_mii_a: gmac_mii@0 { | |
1027 | allwinner,pins = "PA0", "PA1", "PA2", | |
1028 | "PA3", "PA4", "PA5", "PA6", | |
1029 | "PA7", "PA8", "PA9", "PA10", | |
1030 | "PA11", "PA12", "PA13", "PA14", | |
1031 | "PA15", "PA16"; | |
1032 | allwinner,function = "gmac"; | |
092a0c3b MR |
1033 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
1034 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
129ccbcd CYT |
1035 | }; |
1036 | ||
1037 | gmac_pins_rgmii_a: gmac_rgmii@0 { | |
1038 | allwinner,pins = "PA0", "PA1", "PA2", | |
1039 | "PA3", "PA4", "PA5", "PA6", | |
1040 | "PA7", "PA8", "PA10", | |
1041 | "PA11", "PA12", "PA13", | |
1042 | "PA15", "PA16"; | |
1043 | allwinner,function = "gmac"; | |
1044 | /* | |
1045 | * data lines in RGMII mode use DDR mode | |
1046 | * and need a higher signal drive strength | |
1047 | */ | |
092a0c3b MR |
1048 | allwinner,drive = <SUN4I_PINCTRL_40_MA>; |
1049 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
129ccbcd | 1050 | }; |
412f2c6f | 1051 | |
2dad53b5 | 1052 | spi0_pins_a: spi0@0 { |
f3022c6c MR |
1053 | allwinner,pins = "PI11", "PI12", "PI13"; |
1054 | allwinner,function = "spi0"; | |
1055 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
1056 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
1057 | }; | |
1058 | ||
1059 | spi0_cs0_pins_a: spi0_cs0@0 { | |
1060 | allwinner,pins = "PI10"; | |
1061 | allwinner,function = "spi0"; | |
1062 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
1063 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
1064 | }; | |
1065 | ||
1066 | spi0_cs1_pins_a: spi0_cs1@0 { | |
1067 | allwinner,pins = "PI14"; | |
2dad53b5 | 1068 | allwinner,function = "spi0"; |
092a0c3b MR |
1069 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
1070 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
2dad53b5 HG |
1071 | }; |
1072 | ||
412f2c6f | 1073 | spi1_pins_a: spi1@0 { |
f3022c6c MR |
1074 | allwinner,pins = "PI17", "PI18", "PI19"; |
1075 | allwinner,function = "spi1"; | |
1076 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
1077 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
1078 | }; | |
1079 | ||
1080 | spi1_cs0_pins_a: spi1_cs0@0 { | |
1081 | allwinner,pins = "PI16"; | |
412f2c6f | 1082 | allwinner,function = "spi1"; |
092a0c3b MR |
1083 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
1084 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
412f2c6f MR |
1085 | }; |
1086 | ||
1087 | spi2_pins_a: spi2@0 { | |
f3022c6c | 1088 | allwinner,pins = "PC20", "PC21", "PC22"; |
412f2c6f | 1089 | allwinner,function = "spi2"; |
092a0c3b MR |
1090 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
1091 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
7b5bace3 WW |
1092 | }; |
1093 | ||
1094 | spi2_pins_b: spi2@1 { | |
f3022c6c MR |
1095 | allwinner,pins = "PB15", "PB16", "PB17"; |
1096 | allwinner,function = "spi2"; | |
1097 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
1098 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
1099 | }; | |
1100 | ||
1101 | spi2_cs0_pins_a: spi2_cs0@0 { | |
1102 | allwinner,pins = "PC19"; | |
1103 | allwinner,function = "spi2"; | |
1104 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
1105 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
1106 | }; | |
1107 | ||
1108 | spi2_cs0_pins_b: spi2_cs0@1 { | |
1109 | allwinner,pins = "PB14"; | |
7b5bace3 | 1110 | allwinner,function = "spi2"; |
092a0c3b MR |
1111 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
1112 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
412f2c6f | 1113 | }; |
11fbedf4 HG |
1114 | |
1115 | mmc0_pins_a: mmc0@0 { | |
d8cacaa3 MR |
1116 | allwinner,pins = "PF0", "PF1", "PF2", |
1117 | "PF3", "PF4", "PF5"; | |
11fbedf4 | 1118 | allwinner,function = "mmc0"; |
092a0c3b MR |
1119 | allwinner,drive = <SUN4I_PINCTRL_30_MA>; |
1120 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
11fbedf4 HG |
1121 | }; |
1122 | ||
1123 | mmc0_cd_pin_reference_design: mmc0_cd_pin@0 { | |
1124 | allwinner,pins = "PH1"; | |
1125 | allwinner,function = "gpio_in"; | |
092a0c3b MR |
1126 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
1127 | allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; | |
11fbedf4 HG |
1128 | }; |
1129 | ||
8fa82326 | 1130 | mmc2_pins_a: mmc2@0 { |
d8cacaa3 MR |
1131 | allwinner,pins = "PC6", "PC7", "PC8", |
1132 | "PC9", "PC10", "PC11"; | |
8fa82326 | 1133 | allwinner,function = "mmc2"; |
092a0c3b MR |
1134 | allwinner,drive = <SUN4I_PINCTRL_30_MA>; |
1135 | allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; | |
8fa82326 HG |
1136 | }; |
1137 | ||
11fbedf4 | 1138 | mmc3_pins_a: mmc3@0 { |
d8cacaa3 MR |
1139 | allwinner,pins = "PI4", "PI5", "PI6", |
1140 | "PI7", "PI8", "PI9"; | |
11fbedf4 | 1141 | allwinner,function = "mmc3"; |
092a0c3b MR |
1142 | allwinner,drive = <SUN4I_PINCTRL_30_MA>; |
1143 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
11fbedf4 | 1144 | }; |
0fc2b7af | 1145 | |
469a22e6 MC |
1146 | ir0_rx_pins_a: ir0@0 { |
1147 | allwinner,pins = "PB4"; | |
0fc2b7af | 1148 | allwinner,function = "ir0"; |
092a0c3b MR |
1149 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
1150 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
0fc2b7af AB |
1151 | }; |
1152 | ||
469a22e6 MC |
1153 | ir0_tx_pins_a: ir0@1 { |
1154 | allwinner,pins = "PB3"; | |
1155 | allwinner,function = "ir0"; | |
1156 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
1157 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
1158 | }; | |
1159 | ||
1160 | ir1_rx_pins_a: ir1@0 { | |
1161 | allwinner,pins = "PB23"; | |
1162 | allwinner,function = "ir1"; | |
1163 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
1164 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
1165 | }; | |
1166 | ||
1167 | ir1_tx_pins_a: ir1@1 { | |
1168 | allwinner,pins = "PB22"; | |
0fc2b7af | 1169 | allwinner,function = "ir1"; |
092a0c3b MR |
1170 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
1171 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
0fc2b7af | 1172 | }; |
1e8d1567 VP |
1173 | |
1174 | ps20_pins_a: ps20@0 { | |
1175 | allwinner,pins = "PI20", "PI21"; | |
1176 | allwinner,function = "ps2"; | |
1177 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
1178 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
1179 | }; | |
1180 | ||
1181 | ps21_pins_a: ps21@0 { | |
1182 | allwinner,pins = "PH12", "PH13"; | |
1183 | allwinner,function = "ps2"; | |
1184 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
1185 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
0fc2b7af | 1186 | }; |
17eac031 MR |
1187 | }; |
1188 | ||
4790ecfa | 1189 | timer@01c20c00 { |
b4f26440 | 1190 | compatible = "allwinner,sun4i-a10-timer"; |
4790ecfa | 1191 | reg = <0x01c20c00 0x90>; |
19882b84 MR |
1192 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, |
1193 | <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, | |
1194 | <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, | |
1195 | <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, | |
1196 | <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, | |
1197 | <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; | |
4790ecfa MR |
1198 | clocks = <&osc24M>; |
1199 | }; | |
1200 | ||
1201 | wdt: watchdog@01c20c90 { | |
ca5d04d9 | 1202 | compatible = "allwinner,sun4i-a10-wdt"; |
4790ecfa MR |
1203 | reg = <0x01c20c90 0x10>; |
1204 | }; | |
1205 | ||
b5d905c7 CC |
1206 | rtc: rtc@01c20d00 { |
1207 | compatible = "allwinner,sun7i-a20-rtc"; | |
1208 | reg = <0x01c20d00 0x20>; | |
19882b84 | 1209 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; |
b5d905c7 CC |
1210 | }; |
1211 | ||
8ec40c25 AB |
1212 | pwm: pwm@01c20e00 { |
1213 | compatible = "allwinner,sun7i-a20-pwm"; | |
1214 | reg = <0x01c20e00 0xc>; | |
1215 | clocks = <&osc24M>; | |
1216 | #pwm-cells = <3>; | |
1217 | status = "disabled"; | |
1218 | }; | |
1219 | ||
c1a0ee3d | 1220 | ir0: ir@01c21800 { |
1715a389 | 1221 | compatible = "allwinner,sun4i-a10-ir"; |
c1a0ee3d AB |
1222 | clocks = <&apb0_gates 6>, <&ir0_clk>; |
1223 | clock-names = "apb", "ir"; | |
19882b84 | 1224 | interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; |
c1a0ee3d AB |
1225 | reg = <0x01c21800 0x40>; |
1226 | status = "disabled"; | |
1227 | }; | |
1228 | ||
1229 | ir1: ir@01c21c00 { | |
1715a389 | 1230 | compatible = "allwinner,sun4i-a10-ir"; |
c1a0ee3d AB |
1231 | clocks = <&apb0_gates 7>, <&ir1_clk>; |
1232 | clock-names = "apb", "ir"; | |
19882b84 | 1233 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
c1a0ee3d AB |
1234 | reg = <0x01c21c00 0x40>; |
1235 | status = "disabled"; | |
1236 | }; | |
1237 | ||
a6a2d644 HG |
1238 | lradc: lradc@01c22800 { |
1239 | compatible = "allwinner,sun4i-a10-lradc-keys"; | |
1240 | reg = <0x01c22800 0x100>; | |
19882b84 | 1241 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
a6a2d644 HG |
1242 | status = "disabled"; |
1243 | }; | |
1244 | ||
d5ce107a EL |
1245 | codec: codec@01c22c00 { |
1246 | #sound-dai-cells = <0>; | |
1247 | compatible = "allwinner,sun7i-a20-codec"; | |
1248 | reg = <0x01c22c00 0x40>; | |
1249 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; | |
1250 | clocks = <&apb0_gates 0>, <&codec_clk>; | |
1251 | clock-names = "apb", "codec"; | |
1252 | dmas = <&dma SUN4I_DMA_NORMAL 19>, | |
1253 | <&dma SUN4I_DMA_NORMAL 19>; | |
1254 | dma-names = "rx", "tx"; | |
1255 | status = "disabled"; | |
1256 | }; | |
1257 | ||
2bad969f OS |
1258 | sid: eeprom@01c23800 { |
1259 | compatible = "allwinner,sun7i-a20-sid"; | |
1260 | reg = <0x01c23800 0x200>; | |
1261 | }; | |
1262 | ||
00f7ed8d | 1263 | rtp: rtp@01c25000 { |
8bf1b9b3 | 1264 | compatible = "allwinner,sun5i-a13-ts"; |
00f7ed8d | 1265 | reg = <0x01c25000 0x100>; |
19882b84 | 1266 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
41e7afb1 | 1267 | #thermal-sensor-cells = <0>; |
00f7ed8d HG |
1268 | }; |
1269 | ||
4790ecfa MR |
1270 | uart0: serial@01c28000 { |
1271 | compatible = "snps,dw-apb-uart"; | |
1272 | reg = <0x01c28000 0x400>; | |
19882b84 | 1273 | interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; |
4790ecfa MR |
1274 | reg-shift = <2>; |
1275 | reg-io-width = <4>; | |
de7dc935 | 1276 | clocks = <&apb1_gates 16>; |
4790ecfa MR |
1277 | status = "disabled"; |
1278 | }; | |
1279 | ||
1280 | uart1: serial@01c28400 { | |
1281 | compatible = "snps,dw-apb-uart"; | |
1282 | reg = <0x01c28400 0x400>; | |
19882b84 | 1283 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
4790ecfa MR |
1284 | reg-shift = <2>; |
1285 | reg-io-width = <4>; | |
de7dc935 | 1286 | clocks = <&apb1_gates 17>; |
4790ecfa MR |
1287 | status = "disabled"; |
1288 | }; | |
1289 | ||
1290 | uart2: serial@01c28800 { | |
1291 | compatible = "snps,dw-apb-uart"; | |
1292 | reg = <0x01c28800 0x400>; | |
19882b84 | 1293 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; |
4790ecfa MR |
1294 | reg-shift = <2>; |
1295 | reg-io-width = <4>; | |
de7dc935 | 1296 | clocks = <&apb1_gates 18>; |
4790ecfa MR |
1297 | status = "disabled"; |
1298 | }; | |
1299 | ||
1300 | uart3: serial@01c28c00 { | |
1301 | compatible = "snps,dw-apb-uart"; | |
1302 | reg = <0x01c28c00 0x400>; | |
19882b84 | 1303 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; |
4790ecfa MR |
1304 | reg-shift = <2>; |
1305 | reg-io-width = <4>; | |
de7dc935 | 1306 | clocks = <&apb1_gates 19>; |
4790ecfa MR |
1307 | status = "disabled"; |
1308 | }; | |
1309 | ||
1310 | uart4: serial@01c29000 { | |
1311 | compatible = "snps,dw-apb-uart"; | |
1312 | reg = <0x01c29000 0x400>; | |
19882b84 | 1313 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
4790ecfa MR |
1314 | reg-shift = <2>; |
1315 | reg-io-width = <4>; | |
de7dc935 | 1316 | clocks = <&apb1_gates 20>; |
4790ecfa MR |
1317 | status = "disabled"; |
1318 | }; | |
1319 | ||
1320 | uart5: serial@01c29400 { | |
1321 | compatible = "snps,dw-apb-uart"; | |
1322 | reg = <0x01c29400 0x400>; | |
19882b84 | 1323 | interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; |
4790ecfa MR |
1324 | reg-shift = <2>; |
1325 | reg-io-width = <4>; | |
de7dc935 | 1326 | clocks = <&apb1_gates 21>; |
4790ecfa MR |
1327 | status = "disabled"; |
1328 | }; | |
1329 | ||
1330 | uart6: serial@01c29800 { | |
1331 | compatible = "snps,dw-apb-uart"; | |
1332 | reg = <0x01c29800 0x400>; | |
19882b84 | 1333 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
4790ecfa MR |
1334 | reg-shift = <2>; |
1335 | reg-io-width = <4>; | |
de7dc935 | 1336 | clocks = <&apb1_gates 22>; |
4790ecfa MR |
1337 | status = "disabled"; |
1338 | }; | |
1339 | ||
1340 | uart7: serial@01c29c00 { | |
1341 | compatible = "snps,dw-apb-uart"; | |
1342 | reg = <0x01c29c00 0x400>; | |
19882b84 | 1343 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
4790ecfa MR |
1344 | reg-shift = <2>; |
1345 | reg-io-width = <4>; | |
de7dc935 | 1346 | clocks = <&apb1_gates 23>; |
4790ecfa MR |
1347 | status = "disabled"; |
1348 | }; | |
1349 | ||
428abbb8 | 1350 | i2c0: i2c@01c2ac00 { |
d8cacaa3 MR |
1351 | compatible = "allwinner,sun7i-a20-i2c", |
1352 | "allwinner,sun4i-a10-i2c"; | |
428abbb8 | 1353 | reg = <0x01c2ac00 0x400>; |
19882b84 | 1354 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
428abbb8 | 1355 | clocks = <&apb1_gates 0>; |
428abbb8 | 1356 | status = "disabled"; |
d1412aed HG |
1357 | #address-cells = <1>; |
1358 | #size-cells = <0>; | |
428abbb8 MR |
1359 | }; |
1360 | ||
1361 | i2c1: i2c@01c2b000 { | |
d8cacaa3 MR |
1362 | compatible = "allwinner,sun7i-a20-i2c", |
1363 | "allwinner,sun4i-a10-i2c"; | |
428abbb8 | 1364 | reg = <0x01c2b000 0x400>; |
19882b84 | 1365 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; |
428abbb8 | 1366 | clocks = <&apb1_gates 1>; |
428abbb8 | 1367 | status = "disabled"; |
d1412aed HG |
1368 | #address-cells = <1>; |
1369 | #size-cells = <0>; | |
428abbb8 MR |
1370 | }; |
1371 | ||
1372 | i2c2: i2c@01c2b400 { | |
d8cacaa3 MR |
1373 | compatible = "allwinner,sun7i-a20-i2c", |
1374 | "allwinner,sun4i-a10-i2c"; | |
428abbb8 | 1375 | reg = <0x01c2b400 0x400>; |
19882b84 | 1376 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
428abbb8 | 1377 | clocks = <&apb1_gates 2>; |
428abbb8 | 1378 | status = "disabled"; |
d1412aed HG |
1379 | #address-cells = <1>; |
1380 | #size-cells = <0>; | |
428abbb8 MR |
1381 | }; |
1382 | ||
1383 | i2c3: i2c@01c2b800 { | |
d8cacaa3 MR |
1384 | compatible = "allwinner,sun7i-a20-i2c", |
1385 | "allwinner,sun4i-a10-i2c"; | |
428abbb8 | 1386 | reg = <0x01c2b800 0x400>; |
19882b84 | 1387 | interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; |
428abbb8 | 1388 | clocks = <&apb1_gates 3>; |
428abbb8 | 1389 | status = "disabled"; |
d1412aed HG |
1390 | #address-cells = <1>; |
1391 | #size-cells = <0>; | |
428abbb8 MR |
1392 | }; |
1393 | ||
a3867045 | 1394 | i2c4: i2c@01c2c000 { |
d8cacaa3 MR |
1395 | compatible = "allwinner,sun7i-a20-i2c", |
1396 | "allwinner,sun4i-a10-i2c"; | |
a3867045 | 1397 | reg = <0x01c2c000 0x400>; |
19882b84 | 1398 | interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; |
428abbb8 | 1399 | clocks = <&apb1_gates 15>; |
428abbb8 | 1400 | status = "disabled"; |
d1412aed HG |
1401 | #address-cells = <1>; |
1402 | #size-cells = <0>; | |
428abbb8 MR |
1403 | }; |
1404 | ||
c40b8d58 CYT |
1405 | gmac: ethernet@01c50000 { |
1406 | compatible = "allwinner,sun7i-a20-gmac"; | |
1407 | reg = <0x01c50000 0x10000>; | |
19882b84 | 1408 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
c40b8d58 CYT |
1409 | interrupt-names = "macirq"; |
1410 | clocks = <&ahb_gates 49>, <&gmac_tx_clk>; | |
1411 | clock-names = "stmmaceth", "allwinner_gmac_tx"; | |
1412 | snps,pbl = <2>; | |
1413 | snps,fixed-burst; | |
1414 | snps,force_sf_dma_mode; | |
1415 | status = "disabled"; | |
1416 | #address-cells = <1>; | |
1417 | #size-cells = <0>; | |
1418 | }; | |
1419 | ||
31f8ad38 MR |
1420 | hstimer@01c60000 { |
1421 | compatible = "allwinner,sun7i-a20-hstimer"; | |
1422 | reg = <0x01c60000 0x1000>; | |
19882b84 MR |
1423 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, |
1424 | <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, | |
1425 | <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, | |
1426 | <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; | |
31f8ad38 MR |
1427 | clocks = <&ahb_gates 28>; |
1428 | }; | |
1429 | ||
4790ecfa MR |
1430 | gic: interrupt-controller@01c81000 { |
1431 | compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; | |
1432 | reg = <0x01c81000 0x1000>, | |
1433 | <0x01c82000 0x1000>, | |
1434 | <0x01c84000 0x2000>, | |
1435 | <0x01c86000 0x2000>; | |
1436 | interrupt-controller; | |
1437 | #interrupt-cells = <3>; | |
19882b84 | 1438 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
4790ecfa | 1439 | }; |
196654ae VP |
1440 | |
1441 | ps20: ps2@01c2a000 { | |
1442 | compatible = "allwinner,sun4i-a10-ps2"; | |
1443 | reg = <0x01c2a000 0x400>; | |
1444 | interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; | |
1445 | clocks = <&apb1_gates 6>; | |
1446 | status = "disabled"; | |
1447 | }; | |
1448 | ||
1449 | ps21: ps2@01c2a400 { | |
1450 | compatible = "allwinner,sun4i-a10-ps2"; | |
1451 | reg = <0x01c2a400 0x400>; | |
1452 | interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; | |
1453 | clocks = <&apb1_gates 7>; | |
1454 | status = "disabled"; | |
4790ecfa MR |
1455 | }; |
1456 | }; | |
1457 | }; |