projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 4790ecfa MR |
1 | /* |
| 2 | * Copyright 2013 Maxime Ripard | |
| 3 | * | |
| 4 | * Maxime Ripard <maxime.ripard@free-electrons.com> | |
| 5 | * | |
| 6 | * The code contained herein is licensed under the GNU General Public | |
| 7 | * License. You may obtain a copy of the GNU General Public License | |
| 8 | * Version 2 or later at the following locations: | |
| 9 | * | |
| 10 | * http://www.opensource.org/licenses/gpl-license.html | |
| 11 | * http://www.gnu.org/copyleft/gpl.html | |
| 12 | */ | |
| 13 | ||
| 14 | /include/ "skeleton.dtsi" | |
| 15 | ||
| 16 | / { | |
| 17 | interrupt-parent = <&gic>; | |
| 18 | ||
| e751cce9 | 19 | aliases { |
| 18428f77 | 20 | ethernet0 = &gmac; |
| 4566b4be MR |
21 | serial0 = &uart0; |
| 22 | serial1 = &uart1; | |
| 23 | serial2 = &uart2; | |
| 24 | serial3 = &uart3; | |
| 25 | serial4 = &uart4; | |
| 26 | serial5 = &uart5; | |
| 27 | serial6 = &uart6; | |
| 28 | serial7 = &uart7; | |
| e751cce9 EL |
29 | }; |
| 30 | ||
| 4790ecfa MR |
31 | cpus { |
| 32 | #address-cells = <1>; | |
| 33 | #size-cells = <0>; | |
| 34 | ||
| 35 | cpu@0 { | |
| 36 | compatible = "arm,cortex-a7"; | |
| 37 | device_type = "cpu"; | |
| 38 | reg = <0>; | |
| 39 | }; | |
| 40 | ||
| 41 | cpu@1 { | |
| 42 | compatible = "arm,cortex-a7"; | |
| 43 | device_type = "cpu"; | |
| 44 | reg = <1>; | |
| 45 | }; | |
| 46 | }; | |
| 47 | ||
| 48 | memory { | |
| 49 | reg = <0x40000000 0x80000000>; | |
| 50 | }; | |
| 51 | ||
| 7902763e MZ |
52 | timer { |
| 53 | compatible = "arm,armv7-timer"; | |
| 54 | interrupts = <1 13 0xf08>, | |
| 55 | <1 14 0xf08>, | |
| 56 | <1 11 0xf08>, | |
| 57 | <1 10 0xf08>; | |
| 58 | }; | |
| 59 | ||
| e29ea4d3 MR |
60 | pmu { |
| 61 | compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu"; | |
| 62 | interrupts = <0 120 4>, | |
| 63 | <0 121 4>; | |
| 64 | }; | |
| 65 | ||
| 4790ecfa MR |
66 | clocks { |
| 67 | #address-cells = <1>; | |
| 68 | #size-cells = <1>; | |
| 69 | ranges; | |
| 70 | ||
| 06067a2f | 71 | osc24M: clk@01c20050 { |
| 4790ecfa | 72 | #clock-cells = <0>; |
| bf6534a1 | 73 | compatible = "allwinner,sun4i-a10-osc-clk"; |
| de7dc935 | 74 | reg = <0x01c20050 0x4>; |
| 4790ecfa | 75 | clock-frequency = <24000000>; |
| 06067a2f | 76 | clock-output-names = "osc24M"; |
| 4790ecfa MR |
77 | }; |
| 78 | ||
| 673fac74 | 79 | osc32k: clk@0 { |
| 4790ecfa MR |
80 | #clock-cells = <0>; |
| 81 | compatible = "fixed-clock"; | |
| 82 | clock-frequency = <32768>; | |
| 673fac74 | 83 | clock-output-names = "osc32k"; |
| 4790ecfa | 84 | }; |
| de7dc935 | 85 | |
| 06067a2f | 86 | pll1: clk@01c20000 { |
| de7dc935 | 87 | #clock-cells = <0>; |
| bf6534a1 | 88 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
| de7dc935 MR |
89 | reg = <0x01c20000 0x4>; |
| 90 | clocks = <&osc24M>; | |
| 06067a2f | 91 | clock-output-names = "pll1"; |
| de7dc935 MR |
92 | }; |
| 93 | ||
| 06067a2f | 94 | pll4: clk@01c20018 { |
| de7dc935 | 95 | #clock-cells = <0>; |
| bf6534a1 | 96 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
| ec5589f7 EL |
97 | reg = <0x01c20018 0x4>; |
| 98 | clocks = <&osc24M>; | |
| 06067a2f | 99 | clock-output-names = "pll4"; |
| ec5589f7 EL |
100 | }; |
| 101 | ||
| 06067a2f | 102 | pll5: clk@01c20020 { |
| c3e5e66b | 103 | #clock-cells = <1>; |
| bf6534a1 | 104 | compatible = "allwinner,sun4i-a10-pll5-clk"; |
| c3e5e66b EL |
105 | reg = <0x01c20020 0x4>; |
| 106 | clocks = <&osc24M>; | |
| 107 | clock-output-names = "pll5_ddr", "pll5_other"; | |
| 108 | }; | |
| 109 | ||
| 06067a2f | 110 | pll6: clk@01c20028 { |
| c3e5e66b | 111 | #clock-cells = <1>; |
| bf6534a1 | 112 | compatible = "allwinner,sun4i-a10-pll6-clk"; |
| c3e5e66b EL |
113 | reg = <0x01c20028 0x4>; |
| 114 | clocks = <&osc24M>; | |
| 115 | clock-output-names = "pll6_sata", "pll6_other", "pll6"; | |
| de7dc935 MR |
116 | }; |
| 117 | ||
| 118 | cpu: cpu@01c20054 { | |
| 119 | #clock-cells = <0>; | |
| bf6534a1 | 120 | compatible = "allwinner,sun4i-a10-cpu-clk"; |
| de7dc935 | 121 | reg = <0x01c20054 0x4>; |
| c3e5e66b | 122 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>; |
| 06067a2f | 123 | clock-output-names = "cpu"; |
| de7dc935 MR |
124 | }; |
| 125 | ||
| 126 | axi: axi@01c20054 { | |
| 127 | #clock-cells = <0>; | |
| bf6534a1 | 128 | compatible = "allwinner,sun4i-a10-axi-clk"; |
| de7dc935 MR |
129 | reg = <0x01c20054 0x4>; |
| 130 | clocks = <&cpu>; | |
| 06067a2f | 131 | clock-output-names = "axi"; |
| de7dc935 MR |
132 | }; |
| 133 | ||
| 134 | ahb: ahb@01c20054 { | |
| 135 | #clock-cells = <0>; | |
| bf6534a1 | 136 | compatible = "allwinner,sun4i-a10-ahb-clk"; |
| de7dc935 MR |
137 | reg = <0x01c20054 0x4>; |
| 138 | clocks = <&axi>; | |
| 06067a2f | 139 | clock-output-names = "ahb"; |
| de7dc935 MR |
140 | }; |
| 141 | ||
| 06067a2f | 142 | ahb_gates: clk@01c20060 { |
| de7dc935 MR |
143 | #clock-cells = <1>; |
| 144 | compatible = "allwinner,sun7i-a20-ahb-gates-clk"; | |
| 145 | reg = <0x01c20060 0x8>; | |
| 146 | clocks = <&ahb>; | |
| 147 | clock-output-names = "ahb_usb0", "ahb_ehci0", | |
| 148 | "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", | |
| 149 | "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0", | |
| 150 | "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms", | |
| 151 | "ahb_nand", "ahb_sdram", "ahb_ace", | |
| 152 | "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1", | |
| 153 | "ahb_spi2", "ahb_spi3", "ahb_sata", | |
| 154 | "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0", | |
| 155 | "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0", | |
| 156 | "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0", | |
| 157 | "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0", | |
| 158 | "ahb_de_fe1", "ahb_gmac", "ahb_mp", | |
| 159 | "ahb_mali"; | |
| 160 | }; | |
| 161 | ||
| 162 | apb0: apb0@01c20054 { | |
| 163 | #clock-cells = <0>; | |
| bf6534a1 | 164 | compatible = "allwinner,sun4i-a10-apb0-clk"; |
| de7dc935 MR |
165 | reg = <0x01c20054 0x4>; |
| 166 | clocks = <&ahb>; | |
| 06067a2f | 167 | clock-output-names = "apb0"; |
| de7dc935 MR |
168 | }; |
| 169 | ||
| 06067a2f | 170 | apb0_gates: clk@01c20068 { |
| de7dc935 MR |
171 | #clock-cells = <1>; |
| 172 | compatible = "allwinner,sun7i-a20-apb0-gates-clk"; | |
| 173 | reg = <0x01c20068 0x4>; | |
| 174 | clocks = <&apb0>; | |
| 175 | clock-output-names = "apb0_codec", "apb0_spdif", | |
| 176 | "apb0_ac97", "apb0_iis0", "apb0_iis1", | |
| 177 | "apb0_pio", "apb0_ir0", "apb0_ir1", | |
| 178 | "apb0_iis2", "apb0_keypad"; | |
| 179 | }; | |
| 180 | ||
| 181 | apb1_mux: apb1_mux@01c20058 { | |
| 182 | #clock-cells = <0>; | |
| bf6534a1 | 183 | compatible = "allwinner,sun4i-a10-apb1-mux-clk"; |
| de7dc935 | 184 | reg = <0x01c20058 0x4>; |
| c3e5e66b | 185 | clocks = <&osc24M>, <&pll6 1>, <&osc32k>; |
| 06067a2f | 186 | clock-output-names = "apb1_mux"; |
| de7dc935 MR |
187 | }; |
| 188 | ||
| 189 | apb1: apb1@01c20058 { | |
| 190 | #clock-cells = <0>; | |
| bf6534a1 | 191 | compatible = "allwinner,sun4i-a10-apb1-clk"; |
| de7dc935 MR |
192 | reg = <0x01c20058 0x4>; |
| 193 | clocks = <&apb1_mux>; | |
| 06067a2f | 194 | clock-output-names = "apb1"; |
| de7dc935 MR |
195 | }; |
| 196 | ||
| 06067a2f | 197 | apb1_gates: clk@01c2006c { |
| de7dc935 MR |
198 | #clock-cells = <1>; |
| 199 | compatible = "allwinner,sun7i-a20-apb1-gates-clk"; | |
| 200 | reg = <0x01c2006c 0x4>; | |
| 201 | clocks = <&apb1>; | |
| 202 | clock-output-names = "apb1_i2c0", "apb1_i2c1", | |
| 203 | "apb1_i2c2", "apb1_i2c3", "apb1_can", | |
| 204 | "apb1_scr", "apb1_ps20", "apb1_ps21", | |
| 205 | "apb1_i2c4", "apb1_uart0", "apb1_uart1", | |
| 206 | "apb1_uart2", "apb1_uart3", "apb1_uart4", | |
| 207 | "apb1_uart5", "apb1_uart6", "apb1_uart7"; | |
| 208 | }; | |
| 1c92b95b EL |
209 | |
| 210 | nand_clk: clk@01c20080 { | |
| 211 | #clock-cells = <0>; | |
| bf6534a1 | 212 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
213 | reg = <0x01c20080 0x4>; |
| 214 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 215 | clock-output-names = "nand"; | |
| 216 | }; | |
| 217 | ||
| 218 | ms_clk: clk@01c20084 { | |
| 219 | #clock-cells = <0>; | |
| bf6534a1 | 220 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
221 | reg = <0x01c20084 0x4>; |
| 222 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 223 | clock-output-names = "ms"; | |
| 224 | }; | |
| 225 | ||
| 226 | mmc0_clk: clk@01c20088 { | |
| 227 | #clock-cells = <0>; | |
| bf6534a1 | 228 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
229 | reg = <0x01c20088 0x4>; |
| 230 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 231 | clock-output-names = "mmc0"; | |
| 232 | }; | |
| 233 | ||
| 234 | mmc1_clk: clk@01c2008c { | |
| 235 | #clock-cells = <0>; | |
| bf6534a1 | 236 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
237 | reg = <0x01c2008c 0x4>; |
| 238 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 239 | clock-output-names = "mmc1"; | |
| 240 | }; | |
| 241 | ||
| 242 | mmc2_clk: clk@01c20090 { | |
| 243 | #clock-cells = <0>; | |
| bf6534a1 | 244 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
245 | reg = <0x01c20090 0x4>; |
| 246 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 247 | clock-output-names = "mmc2"; | |
| 248 | }; | |
| 249 | ||
| 250 | mmc3_clk: clk@01c20094 { | |
| 251 | #clock-cells = <0>; | |
| bf6534a1 | 252 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
253 | reg = <0x01c20094 0x4>; |
| 254 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 255 | clock-output-names = "mmc3"; | |
| 256 | }; | |
| 257 | ||
| 258 | ts_clk: clk@01c20098 { | |
| 259 | #clock-cells = <0>; | |
| bf6534a1 | 260 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
261 | reg = <0x01c20098 0x4>; |
| 262 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 263 | clock-output-names = "ts"; | |
| 264 | }; | |
| 265 | ||
| 266 | ss_clk: clk@01c2009c { | |
| 267 | #clock-cells = <0>; | |
| bf6534a1 | 268 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
269 | reg = <0x01c2009c 0x4>; |
| 270 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 271 | clock-output-names = "ss"; | |
| 272 | }; | |
| 273 | ||
| 274 | spi0_clk: clk@01c200a0 { | |
| 275 | #clock-cells = <0>; | |
| bf6534a1 | 276 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
277 | reg = <0x01c200a0 0x4>; |
| 278 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 279 | clock-output-names = "spi0"; | |
| 280 | }; | |
| 281 | ||
| 282 | spi1_clk: clk@01c200a4 { | |
| 283 | #clock-cells = <0>; | |
| bf6534a1 | 284 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
285 | reg = <0x01c200a4 0x4>; |
| 286 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 287 | clock-output-names = "spi1"; | |
| 288 | }; | |
| 289 | ||
| 290 | spi2_clk: clk@01c200a8 { | |
| 291 | #clock-cells = <0>; | |
| bf6534a1 | 292 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
293 | reg = <0x01c200a8 0x4>; |
| 294 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 295 | clock-output-names = "spi2"; | |
| 296 | }; | |
| 297 | ||
| 298 | pata_clk: clk@01c200ac { | |
| 299 | #clock-cells = <0>; | |
| bf6534a1 | 300 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
301 | reg = <0x01c200ac 0x4>; |
| 302 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 303 | clock-output-names = "pata"; | |
| 304 | }; | |
| 305 | ||
| 306 | ir0_clk: clk@01c200b0 { | |
| 307 | #clock-cells = <0>; | |
| bf6534a1 | 308 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
309 | reg = <0x01c200b0 0x4>; |
| 310 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 311 | clock-output-names = "ir0"; | |
| 312 | }; | |
| 313 | ||
| 314 | ir1_clk: clk@01c200b4 { | |
| 315 | #clock-cells = <0>; | |
| bf6534a1 | 316 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
317 | reg = <0x01c200b4 0x4>; |
| 318 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 319 | clock-output-names = "ir1"; | |
| 320 | }; | |
| 321 | ||
| 434e41b3 RB |
322 | usb_clk: clk@01c200cc { |
| 323 | #clock-cells = <1>; | |
| 324 | #reset-cells = <1>; | |
| 325 | compatible = "allwinner,sun4i-a10-usb-clk"; | |
| 326 | reg = <0x01c200cc 0x4>; | |
| 327 | clocks = <&pll6 1>; | |
| 328 | clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy"; | |
| 329 | }; | |
| 330 | ||
| 1c92b95b EL |
331 | spi3_clk: clk@01c200d4 { |
| 332 | #clock-cells = <0>; | |
| bf6534a1 | 333 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
334 | reg = <0x01c200d4 0x4>; |
| 335 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 336 | clock-output-names = "spi3"; | |
| 337 | }; | |
| 118c07ae EL |
338 | |
| 339 | mbus_clk: clk@01c2015c { | |
| 340 | #clock-cells = <0>; | |
| bf6534a1 | 341 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 118c07ae EL |
342 | reg = <0x01c2015c 0x4>; |
| 343 | clocks = <&osc24M>, <&pll6 2>, <&pll5 1>; | |
| 344 | clock-output-names = "mbus"; | |
| 345 | }; | |
| 0aff0370 | 346 | |
| daed5a81 CYT |
347 | /* |
| 348 | * The following two are dummy clocks, placeholders used in the gmac_tx | |
| 349 | * clock. The gmac driver will choose one parent depending on the PHY | |
| 350 | * interface mode, using clk_set_rate auto-reparenting. | |
| 351 | * The actual TX clock rate is not controlled by the gmac_tx clock. | |
| 352 | */ | |
| 353 | mii_phy_tx_clk: clk@2 { | |
| 354 | #clock-cells = <0>; | |
| 355 | compatible = "fixed-clock"; | |
| 356 | clock-frequency = <25000000>; | |
| 357 | clock-output-names = "mii_phy_tx"; | |
| 358 | }; | |
| 359 | ||
| 360 | gmac_int_tx_clk: clk@3 { | |
| 361 | #clock-cells = <0>; | |
| 362 | compatible = "fixed-clock"; | |
| 363 | clock-frequency = <125000000>; | |
| 364 | clock-output-names = "gmac_int_tx"; | |
| 365 | }; | |
| 366 | ||
| 367 | gmac_tx_clk: clk@01c20164 { | |
| 368 | #clock-cells = <0>; | |
| 369 | compatible = "allwinner,sun7i-a20-gmac-clk"; | |
| 370 | reg = <0x01c20164 0x4>; | |
| 371 | clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; | |
| 372 | clock-output-names = "gmac_tx"; | |
| 373 | }; | |
| 374 | ||
| 0aff0370 CYT |
375 | /* |
| 376 | * Dummy clock used by output clocks | |
| 377 | */ | |
| 378 | osc24M_32k: clk@1 { | |
| 379 | #clock-cells = <0>; | |
| 380 | compatible = "fixed-factor-clock"; | |
| 381 | clock-div = <750>; | |
| 382 | clock-mult = <1>; | |
| 383 | clocks = <&osc24M>; | |
| 384 | clock-output-names = "osc24M_32k"; | |
| 385 | }; | |
| 386 | ||
| 387 | clk_out_a: clk@01c201f0 { | |
| 388 | #clock-cells = <0>; | |
| 389 | compatible = "allwinner,sun7i-a20-out-clk"; | |
| 390 | reg = <0x01c201f0 0x4>; | |
| 391 | clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; | |
| 392 | clock-output-names = "clk_out_a"; | |
| 393 | }; | |
| 394 | ||
| 395 | clk_out_b: clk@01c201f4 { | |
| 396 | #clock-cells = <0>; | |
| 397 | compatible = "allwinner,sun7i-a20-out-clk"; | |
| 398 | reg = <0x01c201f4 0x4>; | |
| 399 | clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; | |
| 400 | clock-output-names = "clk_out_b"; | |
| 401 | }; | |
| 4790ecfa MR |
402 | }; |
| 403 | ||
| 404 | soc@01c00000 { | |
| 405 | compatible = "simple-bus"; | |
| 406 | #address-cells = <1>; | |
| 407 | #size-cells = <1>; | |
| 408 | ranges; | |
| 409 | ||
| 8ff973a2 CC |
410 | nmi_intc: interrupt-controller@01c00030 { |
| 411 | compatible = "allwinner,sun7i-a20-sc-nmi"; | |
| 412 | interrupt-controller; | |
| 413 | #interrupt-cells = <2>; | |
| 414 | reg = <0x01c00030 0x0c>; | |
| 415 | interrupts = <0 0 4>; | |
| 416 | }; | |
| 417 | ||
| 36ab3e73 MR |
418 | spi0: spi@01c05000 { |
| 419 | compatible = "allwinner,sun4i-a10-spi"; | |
| 420 | reg = <0x01c05000 0x1000>; | |
| 421 | interrupts = <0 10 4>; | |
| 422 | clocks = <&ahb_gates 20>, <&spi0_clk>; | |
| 423 | clock-names = "ahb", "mod"; | |
| 424 | status = "disabled"; | |
| 425 | #address-cells = <1>; | |
| 426 | #size-cells = <0>; | |
| 427 | }; | |
| 428 | ||
| 429 | spi1: spi@01c06000 { | |
| 430 | compatible = "allwinner,sun4i-a10-spi"; | |
| 431 | reg = <0x01c06000 0x1000>; | |
| 432 | interrupts = <0 11 4>; | |
| 433 | clocks = <&ahb_gates 21>, <&spi1_clk>; | |
| 434 | clock-names = "ahb", "mod"; | |
| 435 | status = "disabled"; | |
| 436 | #address-cells = <1>; | |
| 437 | #size-cells = <0>; | |
| 438 | }; | |
| 439 | ||
| 2e804d03 | 440 | emac: ethernet@01c0b000 { |
| 1c70e099 | 441 | compatible = "allwinner,sun4i-a10-emac"; |
| 2e804d03 | 442 | reg = <0x01c0b000 0x1000>; |
| 378d0aee | 443 | interrupts = <0 55 4>; |
| 2e804d03 MR |
444 | clocks = <&ahb_gates 17>; |
| 445 | status = "disabled"; | |
| 446 | }; | |
| 447 | ||
| 448 | mdio@01c0b080 { | |
| 1c70e099 | 449 | compatible = "allwinner,sun4i-a10-mdio"; |
| 2e804d03 MR |
450 | reg = <0x01c0b080 0x14>; |
| 451 | status = "disabled"; | |
| 452 | #address-cells = <1>; | |
| 453 | #size-cells = <0>; | |
| 454 | }; | |
| 455 | ||
| 9debd0a2 RB |
456 | usbphy: phy@01c13400 { |
| 457 | #phy-cells = <1>; | |
| 458 | compatible = "allwinner,sun7i-a20-usb-phy"; | |
| 459 | reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; | |
| 460 | reg-names = "phy_ctrl", "pmu1", "pmu2"; | |
| 461 | clocks = <&usb_clk 8>; | |
| 462 | clock-names = "usb_phy"; | |
| 463 | resets = <&usb_clk 1>, <&usb_clk 2>; | |
| 464 | reset-names = "usb1_reset", "usb2_reset"; | |
| 465 | status = "disabled"; | |
| 466 | }; | |
| 467 | ||
| 468 | ehci0: usb@01c14000 { | |
| 469 | compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; | |
| 470 | reg = <0x01c14000 0x100>; | |
| 471 | interrupts = <0 39 4>; | |
| 472 | clocks = <&ahb_gates 1>; | |
| 473 | phys = <&usbphy 1>; | |
| 474 | phy-names = "usb"; | |
| 475 | status = "disabled"; | |
| 476 | }; | |
| 477 | ||
| 478 | ohci0: usb@01c14400 { | |
| 479 | compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; | |
| 480 | reg = <0x01c14400 0x100>; | |
| 481 | interrupts = <0 64 4>; | |
| 482 | clocks = <&usb_clk 6>, <&ahb_gates 2>; | |
| 483 | phys = <&usbphy 1>; | |
| 484 | phy-names = "usb"; | |
| 485 | status = "disabled"; | |
| 486 | }; | |
| 487 | ||
| 36ab3e73 MR |
488 | spi2: spi@01c17000 { |
| 489 | compatible = "allwinner,sun4i-a10-spi"; | |
| 490 | reg = <0x01c17000 0x1000>; | |
| 491 | interrupts = <0 12 4>; | |
| 492 | clocks = <&ahb_gates 22>, <&spi2_clk>; | |
| 493 | clock-names = "ahb", "mod"; | |
| 494 | status = "disabled"; | |
| 495 | #address-cells = <1>; | |
| 496 | #size-cells = <0>; | |
| 497 | }; | |
| 498 | ||
| 902febf9 HG |
499 | ahci: sata@01c18000 { |
| 500 | compatible = "allwinner,sun4i-a10-ahci"; | |
| 501 | reg = <0x01c18000 0x1000>; | |
| 502 | interrupts = <0 56 4>; | |
| 503 | clocks = <&pll6 0>, <&ahb_gates 25>; | |
| 504 | status = "disabled"; | |
| 505 | }; | |
| 506 | ||
| 9debd0a2 RB |
507 | ehci1: usb@01c1c000 { |
| 508 | compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; | |
| 509 | reg = <0x01c1c000 0x100>; | |
| 510 | interrupts = <0 40 4>; | |
| 511 | clocks = <&ahb_gates 3>; | |
| 512 | phys = <&usbphy 2>; | |
| 513 | phy-names = "usb"; | |
| 514 | status = "disabled"; | |
| 515 | }; | |
| 516 | ||
| 517 | ohci1: usb@01c1c400 { | |
| 518 | compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; | |
| 519 | reg = <0x01c1c400 0x100>; | |
| 520 | interrupts = <0 65 4>; | |
| 521 | clocks = <&usb_clk 7>, <&ahb_gates 4>; | |
| 522 | phys = <&usbphy 2>; | |
| 523 | phy-names = "usb"; | |
| 524 | status = "disabled"; | |
| 525 | }; | |
| 526 | ||
| 36ab3e73 MR |
527 | spi3: spi@01c1f000 { |
| 528 | compatible = "allwinner,sun4i-a10-spi"; | |
| 529 | reg = <0x01c1f000 0x1000>; | |
| 530 | interrupts = <0 50 4>; | |
| 531 | clocks = <&ahb_gates 23>, <&spi3_clk>; | |
| 532 | clock-names = "ahb", "mod"; | |
| 533 | status = "disabled"; | |
| 2e804d03 MR |
534 | #address-cells = <1>; |
| 535 | #size-cells = <0>; | |
| 536 | }; | |
| 537 | ||
| 17eac031 MR |
538 | pio: pinctrl@01c20800 { |
| 539 | compatible = "allwinner,sun7i-a20-pinctrl"; | |
| 540 | reg = <0x01c20800 0x400>; | |
| 378d0aee | 541 | interrupts = <0 28 4>; |
| de7dc935 | 542 | clocks = <&apb0_gates 5>; |
| 17eac031 MR |
543 | gpio-controller; |
| 544 | interrupt-controller; | |
| 545 | #address-cells = <1>; | |
| 546 | #size-cells = <0>; | |
| 547 | #gpio-cells = <3>; | |
| 9f229ba9 MR |
548 | |
| 549 | uart0_pins_a: uart0@0 { | |
| 550 | allwinner,pins = "PB22", "PB23"; | |
| 551 | allwinner,function = "uart0"; | |
| 552 | allwinner,drive = <0>; | |
| 553 | allwinner,pull = <0>; | |
| 554 | }; | |
| 555 | ||
| 4261ec43 CYT |
556 | uart2_pins_a: uart2@0 { |
| 557 | allwinner,pins = "PI16", "PI17", "PI18", "PI19"; | |
| 558 | allwinner,function = "uart2"; | |
| 559 | allwinner,drive = <0>; | |
| 560 | allwinner,pull = <0>; | |
| 561 | }; | |
| 562 | ||
| 9f229ba9 MR |
563 | uart6_pins_a: uart6@0 { |
| 564 | allwinner,pins = "PI12", "PI13"; | |
| 565 | allwinner,function = "uart6"; | |
| 566 | allwinner,drive = <0>; | |
| 567 | allwinner,pull = <0>; | |
| 568 | }; | |
| 569 | ||
| 570 | uart7_pins_a: uart7@0 { | |
| 571 | allwinner,pins = "PI20", "PI21"; | |
| 572 | allwinner,function = "uart7"; | |
| 573 | allwinner,drive = <0>; | |
| 574 | allwinner,pull = <0>; | |
| 575 | }; | |
| 756084c5 | 576 | |
| e5496a31 MR |
577 | i2c0_pins_a: i2c0@0 { |
| 578 | allwinner,pins = "PB0", "PB1"; | |
| 579 | allwinner,function = "i2c0"; | |
| 580 | allwinner,drive = <0>; | |
| 581 | allwinner,pull = <0>; | |
| 582 | }; | |
| 583 | ||
| 584 | i2c1_pins_a: i2c1@0 { | |
| 585 | allwinner,pins = "PB18", "PB19"; | |
| 586 | allwinner,function = "i2c1"; | |
| 587 | allwinner,drive = <0>; | |
| 588 | allwinner,pull = <0>; | |
| 589 | }; | |
| 590 | ||
| 591 | i2c2_pins_a: i2c2@0 { | |
| 592 | allwinner,pins = "PB20", "PB21"; | |
| 593 | allwinner,function = "i2c2"; | |
| 594 | allwinner,drive = <0>; | |
| 595 | allwinner,pull = <0>; | |
| 596 | }; | |
| 597 | ||
| 756084c5 MR |
598 | emac_pins_a: emac0@0 { |
| 599 | allwinner,pins = "PA0", "PA1", "PA2", | |
| 600 | "PA3", "PA4", "PA5", "PA6", | |
| 601 | "PA7", "PA8", "PA9", "PA10", | |
| 602 | "PA11", "PA12", "PA13", "PA14", | |
| 603 | "PA15", "PA16"; | |
| 604 | allwinner,function = "emac"; | |
| 605 | allwinner,drive = <0>; | |
| 606 | allwinner,pull = <0>; | |
| 607 | }; | |
| f2e0759e CYT |
608 | |
| 609 | clk_out_a_pins_a: clk_out_a@0 { | |
| 610 | allwinner,pins = "PI12"; | |
| 611 | allwinner,function = "clk_out_a"; | |
| 612 | allwinner,drive = <0>; | |
| 613 | allwinner,pull = <0>; | |
| 614 | }; | |
| 615 | ||
| 616 | clk_out_b_pins_a: clk_out_b@0 { | |
| 617 | allwinner,pins = "PI13"; | |
| 618 | allwinner,function = "clk_out_b"; | |
| 619 | allwinner,drive = <0>; | |
| 620 | allwinner,pull = <0>; | |
| 621 | }; | |
| 129ccbcd CYT |
622 | |
| 623 | gmac_pins_mii_a: gmac_mii@0 { | |
| 624 | allwinner,pins = "PA0", "PA1", "PA2", | |
| 625 | "PA3", "PA4", "PA5", "PA6", | |
| 626 | "PA7", "PA8", "PA9", "PA10", | |
| 627 | "PA11", "PA12", "PA13", "PA14", | |
| 628 | "PA15", "PA16"; | |
| 629 | allwinner,function = "gmac"; | |
| 630 | allwinner,drive = <0>; | |
| 631 | allwinner,pull = <0>; | |
| 632 | }; | |
| 633 | ||
| 634 | gmac_pins_rgmii_a: gmac_rgmii@0 { | |
| 635 | allwinner,pins = "PA0", "PA1", "PA2", | |
| 636 | "PA3", "PA4", "PA5", "PA6", | |
| 637 | "PA7", "PA8", "PA10", | |
| 638 | "PA11", "PA12", "PA13", | |
| 639 | "PA15", "PA16"; | |
| 640 | allwinner,function = "gmac"; | |
| 641 | /* | |
| 642 | * data lines in RGMII mode use DDR mode | |
| 643 | * and need a higher signal drive strength | |
| 644 | */ | |
| 645 | allwinner,drive = <3>; | |
| 646 | allwinner,pull = <0>; | |
| 647 | }; | |
| 412f2c6f MR |
648 | |
| 649 | spi1_pins_a: spi1@0 { | |
| 650 | allwinner,pins = "PI16", "PI17", "PI18", "PI19"; | |
| 651 | allwinner,function = "spi1"; | |
| 652 | allwinner,drive = <0>; | |
| 653 | allwinner,pull = <0>; | |
| 654 | }; | |
| 655 | ||
| 656 | spi2_pins_a: spi2@0 { | |
| 657 | allwinner,pins = "PC19", "PC20", "PC21", "PC22"; | |
| 658 | allwinner,function = "spi2"; | |
| 659 | allwinner,drive = <0>; | |
| 660 | allwinner,pull = <0>; | |
| 661 | }; | |
| 17eac031 MR |
662 | }; |
| 663 | ||
| 4790ecfa | 664 | timer@01c20c00 { |
| b4f26440 | 665 | compatible = "allwinner,sun4i-a10-timer"; |
| 4790ecfa | 666 | reg = <0x01c20c00 0x90>; |
| 378d0aee MR |
667 | interrupts = <0 22 4>, |
| 668 | <0 23 4>, | |
| 669 | <0 24 4>, | |
| 670 | <0 25 4>, | |
| 671 | <0 67 4>, | |
| 672 | <0 68 4>; | |
| 4790ecfa MR |
673 | clocks = <&osc24M>; |
| 674 | }; | |
| 675 | ||
| 676 | wdt: watchdog@01c20c90 { | |
| ca5d04d9 | 677 | compatible = "allwinner,sun4i-a10-wdt"; |
| 4790ecfa MR |
678 | reg = <0x01c20c90 0x10>; |
| 679 | }; | |
| 680 | ||
| b5d905c7 CC |
681 | rtc: rtc@01c20d00 { |
| 682 | compatible = "allwinner,sun7i-a20-rtc"; | |
| 683 | reg = <0x01c20d00 0x20>; | |
| 2f418987 | 684 | interrupts = <0 24 4>; |
| b5d905c7 CC |
685 | }; |
| 686 | ||
| 2bad969f OS |
687 | sid: eeprom@01c23800 { |
| 688 | compatible = "allwinner,sun7i-a20-sid"; | |
| 689 | reg = <0x01c23800 0x200>; | |
| 690 | }; | |
| 691 | ||
| 00f7ed8d | 692 | rtp: rtp@01c25000 { |
| 40dd8f3b | 693 | compatible = "allwinner,sun4i-a10-ts"; |
| 00f7ed8d HG |
694 | reg = <0x01c25000 0x100>; |
| 695 | interrupts = <0 29 4>; | |
| 696 | }; | |
| 697 | ||
| 4790ecfa MR |
698 | uart0: serial@01c28000 { |
| 699 | compatible = "snps,dw-apb-uart"; | |
| 700 | reg = <0x01c28000 0x400>; | |
| 378d0aee | 701 | interrupts = <0 1 4>; |
| 4790ecfa MR |
702 | reg-shift = <2>; |
| 703 | reg-io-width = <4>; | |
| de7dc935 | 704 | clocks = <&apb1_gates 16>; |
| 4790ecfa MR |
705 | status = "disabled"; |
| 706 | }; | |
| 707 | ||
| 708 | uart1: serial@01c28400 { | |
| 709 | compatible = "snps,dw-apb-uart"; | |
| 710 | reg = <0x01c28400 0x400>; | |
| 378d0aee | 711 | interrupts = <0 2 4>; |
| 4790ecfa MR |
712 | reg-shift = <2>; |
| 713 | reg-io-width = <4>; | |
| de7dc935 | 714 | clocks = <&apb1_gates 17>; |
| 4790ecfa MR |
715 | status = "disabled"; |
| 716 | }; | |
| 717 | ||
| 718 | uart2: serial@01c28800 { | |
| 719 | compatible = "snps,dw-apb-uart"; | |
| 720 | reg = <0x01c28800 0x400>; | |
| 378d0aee | 721 | interrupts = <0 3 4>; |
| 4790ecfa MR |
722 | reg-shift = <2>; |
| 723 | reg-io-width = <4>; | |
| de7dc935 | 724 | clocks = <&apb1_gates 18>; |
| 4790ecfa MR |
725 | status = "disabled"; |
| 726 | }; | |
| 727 | ||
| 728 | uart3: serial@01c28c00 { | |
| 729 | compatible = "snps,dw-apb-uart"; | |
| 730 | reg = <0x01c28c00 0x400>; | |
| 378d0aee | 731 | interrupts = <0 4 4>; |
| 4790ecfa MR |
732 | reg-shift = <2>; |
| 733 | reg-io-width = <4>; | |
| de7dc935 | 734 | clocks = <&apb1_gates 19>; |
| 4790ecfa MR |
735 | status = "disabled"; |
| 736 | }; | |
| 737 | ||
| 738 | uart4: serial@01c29000 { | |
| 739 | compatible = "snps,dw-apb-uart"; | |
| 740 | reg = <0x01c29000 0x400>; | |
| 378d0aee | 741 | interrupts = <0 17 4>; |
| 4790ecfa MR |
742 | reg-shift = <2>; |
| 743 | reg-io-width = <4>; | |
| de7dc935 | 744 | clocks = <&apb1_gates 20>; |
| 4790ecfa MR |
745 | status = "disabled"; |
| 746 | }; | |
| 747 | ||
| 748 | uart5: serial@01c29400 { | |
| 749 | compatible = "snps,dw-apb-uart"; | |
| 750 | reg = <0x01c29400 0x400>; | |
| 378d0aee | 751 | interrupts = <0 18 4>; |
| 4790ecfa MR |
752 | reg-shift = <2>; |
| 753 | reg-io-width = <4>; | |
| de7dc935 | 754 | clocks = <&apb1_gates 21>; |
| 4790ecfa MR |
755 | status = "disabled"; |
| 756 | }; | |
| 757 | ||
| 758 | uart6: serial@01c29800 { | |
| 759 | compatible = "snps,dw-apb-uart"; | |
| 760 | reg = <0x01c29800 0x400>; | |
| 378d0aee | 761 | interrupts = <0 19 4>; |
| 4790ecfa MR |
762 | reg-shift = <2>; |
| 763 | reg-io-width = <4>; | |
| de7dc935 | 764 | clocks = <&apb1_gates 22>; |
| 4790ecfa MR |
765 | status = "disabled"; |
| 766 | }; | |
| 767 | ||
| 768 | uart7: serial@01c29c00 { | |
| 769 | compatible = "snps,dw-apb-uart"; | |
| 770 | reg = <0x01c29c00 0x400>; | |
| 378d0aee | 771 | interrupts = <0 20 4>; |
| 4790ecfa MR |
772 | reg-shift = <2>; |
| 773 | reg-io-width = <4>; | |
| de7dc935 | 774 | clocks = <&apb1_gates 23>; |
| 4790ecfa MR |
775 | status = "disabled"; |
| 776 | }; | |
| 777 | ||
| 428abbb8 MR |
778 | i2c0: i2c@01c2ac00 { |
| 779 | compatible = "allwinner,sun4i-i2c"; | |
| 780 | reg = <0x01c2ac00 0x400>; | |
| 378d0aee | 781 | interrupts = <0 7 4>; |
| 428abbb8 MR |
782 | clocks = <&apb1_gates 0>; |
| 783 | clock-frequency = <100000>; | |
| 784 | status = "disabled"; | |
| d1412aed HG |
785 | #address-cells = <1>; |
| 786 | #size-cells = <0>; | |
| 428abbb8 MR |
787 | }; |
| 788 | ||
| 789 | i2c1: i2c@01c2b000 { | |
| 790 | compatible = "allwinner,sun4i-i2c"; | |
| 791 | reg = <0x01c2b000 0x400>; | |
| 378d0aee | 792 | interrupts = <0 8 4>; |
| 428abbb8 MR |
793 | clocks = <&apb1_gates 1>; |
| 794 | clock-frequency = <100000>; | |
| 795 | status = "disabled"; | |
| d1412aed HG |
796 | #address-cells = <1>; |
| 797 | #size-cells = <0>; | |
| 428abbb8 MR |
798 | }; |
| 799 | ||
| 800 | i2c2: i2c@01c2b400 { | |
| 801 | compatible = "allwinner,sun4i-i2c"; | |
| 802 | reg = <0x01c2b400 0x400>; | |
| 378d0aee | 803 | interrupts = <0 9 4>; |
| 428abbb8 MR |
804 | clocks = <&apb1_gates 2>; |
| 805 | clock-frequency = <100000>; | |
| 806 | status = "disabled"; | |
| d1412aed HG |
807 | #address-cells = <1>; |
| 808 | #size-cells = <0>; | |
| 428abbb8 MR |
809 | }; |
| 810 | ||
| 811 | i2c3: i2c@01c2b800 { | |
| 812 | compatible = "allwinner,sun4i-i2c"; | |
| 813 | reg = <0x01c2b800 0x400>; | |
| 378d0aee | 814 | interrupts = <0 88 4>; |
| 428abbb8 MR |
815 | clocks = <&apb1_gates 3>; |
| 816 | clock-frequency = <100000>; | |
| 817 | status = "disabled"; | |
| d1412aed HG |
818 | #address-cells = <1>; |
| 819 | #size-cells = <0>; | |
| 428abbb8 MR |
820 | }; |
| 821 | ||
| 822 | i2c4: i2c@01c2bc00 { | |
| 823 | compatible = "allwinner,sun4i-i2c"; | |
| 824 | reg = <0x01c2bc00 0x400>; | |
| 378d0aee | 825 | interrupts = <0 89 4>; |
| 428abbb8 MR |
826 | clocks = <&apb1_gates 15>; |
| 827 | clock-frequency = <100000>; | |
| 828 | status = "disabled"; | |
| d1412aed HG |
829 | #address-cells = <1>; |
| 830 | #size-cells = <0>; | |
| 428abbb8 MR |
831 | }; |
| 832 | ||
| c40b8d58 CYT |
833 | gmac: ethernet@01c50000 { |
| 834 | compatible = "allwinner,sun7i-a20-gmac"; | |
| 835 | reg = <0x01c50000 0x10000>; | |
| 836 | interrupts = <0 85 4>; | |
| 837 | interrupt-names = "macirq"; | |
| 838 | clocks = <&ahb_gates 49>, <&gmac_tx_clk>; | |
| 839 | clock-names = "stmmaceth", "allwinner_gmac_tx"; | |
| 840 | snps,pbl = <2>; | |
| 841 | snps,fixed-burst; | |
| 842 | snps,force_sf_dma_mode; | |
| 843 | status = "disabled"; | |
| 844 | #address-cells = <1>; | |
| 845 | #size-cells = <0>; | |
| 846 | }; | |
| 847 | ||
| 31f8ad38 MR |
848 | hstimer@01c60000 { |
| 849 | compatible = "allwinner,sun7i-a20-hstimer"; | |
| 850 | reg = <0x01c60000 0x1000>; | |
| 2f418987 MR |
851 | interrupts = <0 81 4>, |
| 852 | <0 82 4>, | |
| 853 | <0 83 4>, | |
| 854 | <0 84 4>; | |
| 31f8ad38 MR |
855 | clocks = <&ahb_gates 28>; |
| 856 | }; | |
| 857 | ||
| 4790ecfa MR |
858 | gic: interrupt-controller@01c81000 { |
| 859 | compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; | |
| 860 | reg = <0x01c81000 0x1000>, | |
| 861 | <0x01c82000 0x1000>, | |
| 862 | <0x01c84000 0x2000>, | |
| 863 | <0x01c86000 0x2000>; | |
| 864 | interrupt-controller; | |
| 865 | #interrupt-cells = <3>; | |
| 866 | interrupts = <1 9 0xf04>; | |
| 867 | }; | |
| 868 | }; | |
| 869 | }; |