projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 4790ecfa MR |
1 | /* |
| 2 | * Copyright 2013 Maxime Ripard | |
| 3 | * | |
| 4 | * Maxime Ripard <maxime.ripard@free-electrons.com> | |
| 5 | * | |
| 6 | * The code contained herein is licensed under the GNU General Public | |
| 7 | * License. You may obtain a copy of the GNU General Public License | |
| 8 | * Version 2 or later at the following locations: | |
| 9 | * | |
| 10 | * http://www.opensource.org/licenses/gpl-license.html | |
| 11 | * http://www.gnu.org/copyleft/gpl.html | |
| 12 | */ | |
| 13 | ||
| 14 | /include/ "skeleton.dtsi" | |
| 15 | ||
| 16 | / { | |
| 17 | interrupt-parent = <&gic>; | |
| 18 | ||
| 19 | cpus { | |
| 20 | #address-cells = <1>; | |
| 21 | #size-cells = <0>; | |
| 22 | ||
| 23 | cpu@0 { | |
| 24 | compatible = "arm,cortex-a7"; | |
| 25 | device_type = "cpu"; | |
| 26 | reg = <0>; | |
| 27 | }; | |
| 28 | ||
| 29 | cpu@1 { | |
| 30 | compatible = "arm,cortex-a7"; | |
| 31 | device_type = "cpu"; | |
| 32 | reg = <1>; | |
| 33 | }; | |
| 34 | }; | |
| 35 | ||
| 36 | memory { | |
| 37 | reg = <0x40000000 0x80000000>; | |
| 38 | }; | |
| 39 | ||
| 40 | clocks { | |
| 41 | #address-cells = <1>; | |
| 42 | #size-cells = <1>; | |
| 43 | ranges; | |
| 44 | ||
| 45 | osc24M: osc24M@01c20050 { | |
| 46 | #clock-cells = <0>; | |
| 47 | compatible = "fixed-clock"; | |
| 48 | clock-frequency = <24000000>; | |
| 49 | }; | |
| 50 | ||
| 51 | osc32k: osc32k { | |
| 52 | #clock-cells = <0>; | |
| 53 | compatible = "fixed-clock"; | |
| 54 | clock-frequency = <32768>; | |
| 55 | }; | |
| 56 | }; | |
| 57 | ||
| 58 | soc@01c00000 { | |
| 59 | compatible = "simple-bus"; | |
| 60 | #address-cells = <1>; | |
| 61 | #size-cells = <1>; | |
| 62 | ranges; | |
| 63 | ||
| 64 | timer@01c20c00 { | |
| 65 | compatible = "allwinner,sun4i-timer"; | |
| 66 | reg = <0x01c20c00 0x90>; | |
| 67 | interrupts = <0 22 1>, | |
| 68 | <0 23 1>, | |
| 69 | <0 24 1>, | |
| 70 | <0 25 1>, | |
| 71 | <0 67 1>, | |
| 72 | <0 68 1>; | |
| 73 | clocks = <&osc24M>; | |
| 74 | }; | |
| 75 | ||
| 76 | wdt: watchdog@01c20c90 { | |
| 77 | compatible = "allwinner,sun4i-wdt"; | |
| 78 | reg = <0x01c20c90 0x10>; | |
| 79 | }; | |
| 80 | ||
| 81 | uart0: serial@01c28000 { | |
| 82 | compatible = "snps,dw-apb-uart"; | |
| 83 | reg = <0x01c28000 0x400>; | |
| 84 | interrupts = <0 1 1>; | |
| 85 | reg-shift = <2>; | |
| 86 | reg-io-width = <4>; | |
| 87 | clocks = <&osc24M>; | |
| 88 | status = "disabled"; | |
| 89 | }; | |
| 90 | ||
| 91 | uart1: serial@01c28400 { | |
| 92 | compatible = "snps,dw-apb-uart"; | |
| 93 | reg = <0x01c28400 0x400>; | |
| 94 | interrupts = <0 2 1>; | |
| 95 | reg-shift = <2>; | |
| 96 | reg-io-width = <4>; | |
| 97 | clocks = <&osc24M>; | |
| 98 | status = "disabled"; | |
| 99 | }; | |
| 100 | ||
| 101 | uart2: serial@01c28800 { | |
| 102 | compatible = "snps,dw-apb-uart"; | |
| 103 | reg = <0x01c28800 0x400>; | |
| 104 | interrupts = <0 3 1>; | |
| 105 | reg-shift = <2>; | |
| 106 | reg-io-width = <4>; | |
| 107 | clocks = <&osc24M>; | |
| 108 | status = "disabled"; | |
| 109 | }; | |
| 110 | ||
| 111 | uart3: serial@01c28c00 { | |
| 112 | compatible = "snps,dw-apb-uart"; | |
| 113 | reg = <0x01c28c00 0x400>; | |
| 114 | interrupts = <0 4 1>; | |
| 115 | reg-shift = <2>; | |
| 116 | reg-io-width = <4>; | |
| 117 | clocks = <&osc24M>; | |
| 118 | status = "disabled"; | |
| 119 | }; | |
| 120 | ||
| 121 | uart4: serial@01c29000 { | |
| 122 | compatible = "snps,dw-apb-uart"; | |
| 123 | reg = <0x01c29000 0x400>; | |
| 124 | interrupts = <0 17 1>; | |
| 125 | reg-shift = <2>; | |
| 126 | reg-io-width = <4>; | |
| 127 | clocks = <&osc24M>; | |
| 128 | status = "disabled"; | |
| 129 | }; | |
| 130 | ||
| 131 | uart5: serial@01c29400 { | |
| 132 | compatible = "snps,dw-apb-uart"; | |
| 133 | reg = <0x01c29400 0x400>; | |
| 134 | interrupts = <0 18 1>; | |
| 135 | reg-shift = <2>; | |
| 136 | reg-io-width = <4>; | |
| 137 | clocks = <&osc24M>; | |
| 138 | status = "disabled"; | |
| 139 | }; | |
| 140 | ||
| 141 | uart6: serial@01c29800 { | |
| 142 | compatible = "snps,dw-apb-uart"; | |
| 143 | reg = <0x01c29800 0x400>; | |
| 144 | interrupts = <0 19 1>; | |
| 145 | reg-shift = <2>; | |
| 146 | reg-io-width = <4>; | |
| 147 | clocks = <&osc24M>; | |
| 148 | status = "disabled"; | |
| 149 | }; | |
| 150 | ||
| 151 | uart7: serial@01c29c00 { | |
| 152 | compatible = "snps,dw-apb-uart"; | |
| 153 | reg = <0x01c29c00 0x400>; | |
| 154 | interrupts = <0 20 1>; | |
| 155 | reg-shift = <2>; | |
| 156 | reg-io-width = <4>; | |
| 157 | clocks = <&osc24M>; | |
| 158 | status = "disabled"; | |
| 159 | }; | |
| 160 | ||
| 161 | gic: interrupt-controller@01c81000 { | |
| 162 | compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; | |
| 163 | reg = <0x01c81000 0x1000>, | |
| 164 | <0x01c82000 0x1000>, | |
| 165 | <0x01c84000 0x2000>, | |
| 166 | <0x01c86000 0x2000>; | |
| 167 | interrupt-controller; | |
| 168 | #interrupt-cells = <3>; | |
| 169 | interrupts = <1 9 0xf04>; | |
| 170 | }; | |
| 171 | }; | |
| 172 | }; |