[deliverable/linux.git] / arch / arm / boot / dts / sun7i-a20.dtsi

/*
 * Copyright 2013 Maxime Ripard
 *
 * Maxime Ripard <maxime.ripard@free-electrons.com>
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

/include/ "skeleton.dtsi"

/ {
	interrupt-parent = <&gic>;

	aliases {
		ethernet0 = &gmac;
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
		serial4 = &uart4;
		serial5 = &uart5;
		serial6 = &uart6;
		serial7 = &uart7;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0>;
		};

		cpu@1 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <1>;
		};
	};

	memory {
		reg = <0x40000000 0x80000000>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <1 13 0xf08>,
			     <1 14 0xf08>,
			     <1 11 0xf08>,
			     <1 10 0xf08>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		osc24M: clk@01c20050 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-osc-clk";
			reg = <0x01c20050 0x4>;
			clock-frequency = <24000000>;
			clock-output-names = "osc24M";
		};

		osc32k: clk@0 {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32768>;
			clock-output-names = "osc32k";
		};

		pll1: clk@01c20000 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-pll1-clk";
			reg = <0x01c20000 0x4>;
			clocks = <&osc24M>;
			clock-output-names = "pll1";
		};

		pll4: clk@01c20018 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-pll1-clk";
			reg = <0x01c20018 0x4>;
			clocks = <&osc24M>;
			clock-output-names = "pll4";
		};

		pll5: clk@01c20020 {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-pll5-clk";
			reg = <0x01c20020 0x4>;
			clocks = <&osc24M>;
			clock-output-names = "pll5_ddr", "pll5_other";
		};

		pll6: clk@01c20028 {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-pll6-clk";
			reg = <0x01c20028 0x4>;
			clocks = <&osc24M>;
			clock-output-names = "pll6_sata", "pll6_other", "pll6";
		};

		cpu: cpu@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-cpu-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
			clock-output-names = "cpu";
		};

		axi: axi@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-axi-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&cpu>;
			clock-output-names = "axi";
		};

		ahb: ahb@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-ahb-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&axi>;
			clock-output-names = "ahb";
		};

		ahb_gates: clk@01c20060 {
			#clock-cells = <1>;
			compatible = "allwinner,sun7i-a20-ahb-gates-clk";
			reg = <0x01c20060 0x8>;
			clocks = <&ahb>;
			clock-output-names = "ahb_usb0", "ahb_ehci0",
				"ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
				"ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
				"ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
				"ahb_nand", "ahb_sdram", "ahb_ace",
				"ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
				"ahb_spi2", "ahb_spi3", "ahb_sata",
				"ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
				"ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
				"ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
				"ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
				"ahb_de_fe1", "ahb_gmac", "ahb_mp",
				"ahb_mali";
		};

		apb0: apb0@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-apb0-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&ahb>;
			clock-output-names = "apb0";
		};

		apb0_gates: clk@01c20068 {
			#clock-cells = <1>;
			compatible = "allwinner,sun7i-a20-apb0-gates-clk";
			reg = <0x01c20068 0x4>;
			clocks = <&apb0>;
			clock-output-names = "apb0_codec", "apb0_spdif",
				"apb0_ac97", "apb0_iis0", "apb0_iis1",
				"apb0_pio", "apb0_ir0", "apb0_ir1",
				"apb0_iis2", "apb0_keypad";
		};

		apb1_mux: apb1_mux@01c20058 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-apb1-mux-clk";
			reg = <0x01c20058 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
			clock-output-names = "apb1_mux";
		};

		apb1: apb1@01c20058 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-apb1-clk";
			reg = <0x01c20058 0x4>;
			clocks = <&apb1_mux>;
			clock-output-names = "apb1";
		};

		apb1_gates: clk@01c2006c {
			#clock-cells = <1>;
			compatible = "allwinner,sun7i-a20-apb1-gates-clk";
			reg = <0x01c2006c 0x4>;
			clocks = <&apb1>;
			clock-output-names = "apb1_i2c0", "apb1_i2c1",
				"apb1_i2c2", "apb1_i2c3", "apb1_can",
				"apb1_scr", "apb1_ps20", "apb1_ps21",
				"apb1_i2c4", "apb1_uart0", "apb1_uart1",
				"apb1_uart2", "apb1_uart3", "apb1_uart4",
				"apb1_uart5", "apb1_uart6", "apb1_uart7";
		};

		nand_clk: clk@01c20080 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c20080 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "nand";
		};

		ms_clk: clk@01c20084 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c20084 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "ms";
		};

		mmc0_clk: clk@01c20088 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c20088 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "mmc0";
		};

		mmc1_clk: clk@01c2008c {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c2008c 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "mmc1";
		};

		mmc2_clk: clk@01c20090 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c20090 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "mmc2";
		};

		mmc3_clk: clk@01c20094 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c20094 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "mmc3";
		};

		ts_clk: clk@01c20098 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c20098 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "ts";
		};

		ss_clk: clk@01c2009c {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c2009c 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "ss";
		};

		spi0_clk: clk@01c200a0 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c200a0 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "spi0";
		};

		spi1_clk: clk@01c200a4 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c200a4 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "spi1";
		};

		spi2_clk: clk@01c200a8 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c200a8 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "spi2";
		};

		pata_clk: clk@01c200ac {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c200ac 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "pata";
		};

		ir0_clk: clk@01c200b0 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c200b0 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "ir0";
		};

		ir1_clk: clk@01c200b4 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c200b4 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "ir1";
		};

		usb_clk: clk@01c200cc {
			#clock-cells = <1>;
		        #reset-cells = <1>;
			compatible = "allwinner,sun4i-a10-usb-clk";
			reg = <0x01c200cc 0x4>;
			clocks = <&pll6 1>;
			clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
		};

		spi3_clk: clk@01c200d4 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c200d4 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "spi3";
		};

		mbus_clk: clk@01c2015c {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c2015c 0x4>;
			clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
			clock-output-names = "mbus";
		};

		/*
		 * The following two are dummy clocks, placeholders used in the gmac_tx
		 * clock. The gmac driver will choose one parent depending on the PHY
		 * interface mode, using clk_set_rate auto-reparenting.
		 * The actual TX clock rate is not controlled by the gmac_tx clock.
		 */
		mii_phy_tx_clk: clk@2 {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <25000000>;
			clock-output-names = "mii_phy_tx";
		};

		gmac_int_tx_clk: clk@3 {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <125000000>;
			clock-output-names = "gmac_int_tx";
		};

		gmac_tx_clk: clk@01c20164 {
			#clock-cells = <0>;
			compatible = "allwinner,sun7i-a20-gmac-clk";
			reg = <0x01c20164 0x4>;
			clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
			clock-output-names = "gmac_tx";
		};

		/*
		 * Dummy clock used by output clocks
		 */
		osc24M_32k: clk@1 {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clock-div = <750>;
			clock-mult = <1>;
			clocks = <&osc24M>;
			clock-output-names = "osc24M_32k";
		};

		clk_out_a: clk@01c201f0 {
			#clock-cells = <0>;
			compatible = "allwinner,sun7i-a20-out-clk";
			reg = <0x01c201f0 0x4>;
			clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
			clock-output-names = "clk_out_a";
		};

		clk_out_b: clk@01c201f4 {
			#clock-cells = <0>;
			compatible = "allwinner,sun7i-a20-out-clk";
			reg = <0x01c201f4 0x4>;
			clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
			clock-output-names = "clk_out_b";
		};
	};

	soc@01c00000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		emac: ethernet@01c0b000 {
			compatible = "allwinner,sun4i-emac";
			reg = <0x01c0b000 0x1000>;
			interrupts = <0 55 4>;
			clocks = <&ahb_gates 17>;
			status = "disabled";
		};

		mdio@01c0b080 {
			compatible = "allwinner,sun4i-mdio";
			reg = <0x01c0b080 0x14>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		pio: pinctrl@01c20800 {
			compatible = "allwinner,sun7i-a20-pinctrl";
			reg = <0x01c20800 0x400>;
			interrupts = <0 28 4>;
			clocks = <&apb0_gates 5>;
			gpio-controller;
			interrupt-controller;
			#address-cells = <1>;
			#size-cells = <0>;
			#gpio-cells = <3>;

			uart0_pins_a: uart0@0 {
				allwinner,pins = "PB22", "PB23";
				allwinner,function = "uart0";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			uart2_pins_a: uart2@0 {
				allwinner,pins = "PI16", "PI17", "PI18", "PI19";
				allwinner,function = "uart2";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			uart6_pins_a: uart6@0 {
				allwinner,pins = "PI12", "PI13";
				allwinner,function = "uart6";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			uart7_pins_a: uart7@0 {
				allwinner,pins = "PI20", "PI21";
				allwinner,function = "uart7";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			i2c0_pins_a: i2c0@0 {
				allwinner,pins = "PB0", "PB1";
				allwinner,function = "i2c0";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			i2c1_pins_a: i2c1@0 {
				allwinner,pins = "PB18", "PB19";
				allwinner,function = "i2c1";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			i2c2_pins_a: i2c2@0 {
				allwinner,pins = "PB20", "PB21";
				allwinner,function = "i2c2";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			emac_pins_a: emac0@0 {
				allwinner,pins = "PA0", "PA1", "PA2",
						"PA3", "PA4", "PA5", "PA6",
						"PA7", "PA8", "PA9", "PA10",
						"PA11", "PA12", "PA13", "PA14",
						"PA15", "PA16";
				allwinner,function = "emac";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			clk_out_a_pins_a: clk_out_a@0 {
				allwinner,pins = "PI12";
				allwinner,function = "clk_out_a";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			clk_out_b_pins_a: clk_out_b@0 {
				allwinner,pins = "PI13";
				allwinner,function = "clk_out_b";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			gmac_pins_mii_a: gmac_mii@0 {
				allwinner,pins = "PA0", "PA1", "PA2",
						"PA3", "PA4", "PA5", "PA6",
						"PA7", "PA8", "PA9", "PA10",
						"PA11", "PA12", "PA13", "PA14",
						"PA15", "PA16";
				allwinner,function = "gmac";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			gmac_pins_rgmii_a: gmac_rgmii@0 {
				allwinner,pins = "PA0", "PA1", "PA2",
						"PA3", "PA4", "PA5", "PA6",
						"PA7", "PA8", "PA10",
						"PA11", "PA12", "PA13",
						"PA15", "PA16";
				allwinner,function = "gmac";
				/*
				 * data lines in RGMII mode use DDR mode
				 * and need a higher signal drive strength
				 */
				allwinner,drive = <3>;
				allwinner,pull = <0>;
			};
		};

		timer@01c20c00 {
			compatible = "allwinner,sun4i-timer";
			reg = <0x01c20c00 0x90>;
			interrupts = <0 22 4>,
				     <0 23 4>,
				     <0 24 4>,
				     <0 25 4>,
				     <0 67 4>,
				     <0 68 4>;
			clocks = <&osc24M>;
		};

		wdt: watchdog@01c20c90 {
			compatible = "allwinner,sun4i-wdt";
			reg = <0x01c20c90 0x10>;
		};

		rtc: rtc@01c20d00 {
			compatible = "allwinner,sun7i-a20-rtc";
			reg = <0x01c20d00 0x20>;
			interrupts = <0 24 1>;
		};

		sid: eeprom@01c23800 {
			compatible = "allwinner,sun7i-a20-sid";
			reg = <0x01c23800 0x200>;
		};

		rtp: rtp@01c25000 {
			compatible = "allwinner,sun4i-ts";
			reg = <0x01c25000 0x100>;
			interrupts = <0 29 4>;
		};

		uart0: serial@01c28000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28000 0x400>;
			interrupts = <0 1 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 16>;
			status = "disabled";
		};

		uart1: serial@01c28400 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28400 0x400>;
			interrupts = <0 2 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 17>;
			status = "disabled";
		};

		uart2: serial@01c28800 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28800 0x400>;
			interrupts = <0 3 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 18>;
			status = "disabled";
		};

		uart3: serial@01c28c00 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28c00 0x400>;
			interrupts = <0 4 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 19>;
			status = "disabled";
		};

		uart4: serial@01c29000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29000 0x400>;
			interrupts = <0 17 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 20>;
			status = "disabled";
		};

		uart5: serial@01c29400 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29400 0x400>;
			interrupts = <0 18 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 21>;
			status = "disabled";
		};

		uart6: serial@01c29800 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29800 0x400>;
			interrupts = <0 19 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 22>;
			status = "disabled";
		};

		uart7: serial@01c29c00 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29c00 0x400>;
			interrupts = <0 20 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 23>;
			status = "disabled";
		};

		i2c0: i2c@01c2ac00 {
			compatible = "allwinner,sun4i-i2c";
			reg = <0x01c2ac00 0x400>;
			interrupts = <0 7 4>;
			clocks = <&apb1_gates 0>;
			clock-frequency = <100000>;
			status = "disabled";
		};

		i2c1: i2c@01c2b000 {
			compatible = "allwinner,sun4i-i2c";
			reg = <0x01c2b000 0x400>;
			interrupts = <0 8 4>;
			clocks = <&apb1_gates 1>;
			clock-frequency = <100000>;
			status = "disabled";
		};

		i2c2: i2c@01c2b400 {
			compatible = "allwinner,sun4i-i2c";
			reg = <0x01c2b400 0x400>;
			interrupts = <0 9 4>;
			clocks = <&apb1_gates 2>;
			clock-frequency = <100000>;
			status = "disabled";
		};

		i2c3: i2c@01c2b800 {
			compatible = "allwinner,sun4i-i2c";
			reg = <0x01c2b800 0x400>;
			interrupts = <0 88 4>;
			clocks = <&apb1_gates 3>;
			clock-frequency = <100000>;
			status = "disabled";
		};

		i2c4: i2c@01c2bc00 {
			compatible = "allwinner,sun4i-i2c";
			reg = <0x01c2bc00 0x400>;
			interrupts = <0 89 4>;
			clocks = <&apb1_gates 15>;
			clock-frequency = <100000>;
			status = "disabled";
		};

		gmac: ethernet@01c50000 {
			compatible = "allwinner,sun7i-a20-gmac";
			reg = <0x01c50000 0x10000>;
			interrupts = <0 85 4>;
			interrupt-names = "macirq";
			clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
			clock-names = "stmmaceth", "allwinner_gmac_tx";
			snps,pbl = <2>;
			snps,fixed-burst;
			snps,force_sf_dma_mode;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		hstimer@01c60000 {
			compatible = "allwinner,sun7i-a20-hstimer";
			reg = <0x01c60000 0x1000>;
			interrupts = <0 81 1>,
				     <0 82 1>,
				     <0 83 1>,
				     <0 84 1>;
			clocks = <&ahb_gates 28>;
		};

		gic: interrupt-controller@01c81000 {
			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
			reg = <0x01c81000 0x1000>,
			      <0x01c82000 0x1000>,
			      <0x01c84000 0x2000>,
			      <0x01c86000 0x2000>;
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <1 9 0xf04>;
		};
	};
};
Commit	Line	Data
4790ecfa MR	1	/*
	2	* Copyright 2013 Maxime Ripard
	3	*
	4	* Maxime Ripard <maxime.ripard@free-electrons.com>
	5	*
	6	* The code contained herein is licensed under the GNU General Public
	7	* License. You may obtain a copy of the GNU General Public License
	8	* Version 2 or later at the following locations:
	9	*
	10	* http://www.opensource.org/licenses/gpl-license.html
	11	* http://www.gnu.org/copyleft/gpl.html
	12	*/
	13
	14	/include/ "skeleton.dtsi"
	15
	16	/ {
	17	interrupt-parent = <&gic>;
	18
e751cce9	19	aliases {
18428f77	20	ethernet0 = &gmac;
4566b4be MR	21	serial0 = &uart0;
	22	serial1 = &uart1;
	23	serial2 = &uart2;
	24	serial3 = &uart3;
	25	serial4 = &uart4;
	26	serial5 = &uart5;
	27	serial6 = &uart6;
	28	serial7 = &uart7;
e751cce9 EL	29	};
e751cce9 EL	30
4790ecfa MR	31	cpus {
	32	#address-cells = <1>;
	33	#size-cells = <0>;
	34
	35	cpu@0 {
	36	compatible = "arm,cortex-a7";
	37	device_type = "cpu";
	38	reg = <0>;
	39	};
	40
	41	cpu@1 {
	42	compatible = "arm,cortex-a7";
	43	device_type = "cpu";
	44	reg = <1>;
	45	};
	46	};
	47
	48	memory {
	49	reg = <0x40000000 0x80000000>;
	50	};
	51
7902763e MZ	52	timer {
	53	compatible = "arm,armv7-timer";
	54	interrupts = <1 13 0xf08>,
	55	<1 14 0xf08>,
	56	<1 11 0xf08>,
	57	<1 10 0xf08>;
	58	};
	59
4790ecfa MR	60	clocks {
	61	#address-cells = <1>;
	62	#size-cells = <1>;
	63	ranges;
	64
06067a2f	65	osc24M: clk@01c20050 {
4790ecfa	66	#clock-cells = <0>;
de7dc935 MR	67	compatible = "allwinner,sun4i-osc-clk";
de7dc935 MR	68	reg = <0x01c20050 0x4>;
4790ecfa	69	clock-frequency = <24000000>;
06067a2f	70	clock-output-names = "osc24M";
4790ecfa MR	71	};
4790ecfa MR	72
673fac74	73	osc32k: clk@0 {
4790ecfa MR	74	#clock-cells = <0>;
	75	compatible = "fixed-clock";
	76	clock-frequency = <32768>;
673fac74	77	clock-output-names = "osc32k";
4790ecfa	78	};
de7dc935	79
06067a2f	80	pll1: clk@01c20000 {
de7dc935 MR	81	#clock-cells = <0>;
	82	compatible = "allwinner,sun4i-pll1-clk";
	83	reg = <0x01c20000 0x4>;
	84	clocks = <&osc24M>;
06067a2f	85	clock-output-names = "pll1";
de7dc935 MR	86	};
de7dc935 MR	87
06067a2f	88	pll4: clk@01c20018 {
de7dc935	89	#clock-cells = <0>;
ec5589f7 EL	90	compatible = "allwinner,sun4i-pll1-clk";
	91	reg = <0x01c20018 0x4>;
	92	clocks = <&osc24M>;
06067a2f	93	clock-output-names = "pll4";
ec5589f7 EL	94	};
ec5589f7 EL	95
06067a2f	96	pll5: clk@01c20020 {
c3e5e66b EL	97	#clock-cells = <1>;
	98	compatible = "allwinner,sun4i-pll5-clk";
	99	reg = <0x01c20020 0x4>;
	100	clocks = <&osc24M>;
	101	clock-output-names = "pll5_ddr", "pll5_other";
	102	};
	103
06067a2f	104	pll6: clk@01c20028 {
c3e5e66b EL	105	#clock-cells = <1>;
	106	compatible = "allwinner,sun4i-pll6-clk";
	107	reg = <0x01c20028 0x4>;
	108	clocks = <&osc24M>;
	109	clock-output-names = "pll6_sata", "pll6_other", "pll6";
de7dc935 MR	110	};
	111
	112	cpu: cpu@01c20054 {
	113	#clock-cells = <0>;
	114	compatible = "allwinner,sun4i-cpu-clk";
	115	reg = <0x01c20054 0x4>;
c3e5e66b	116	clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
06067a2f	117	clock-output-names = "cpu";
de7dc935 MR	118	};
	119
	120	axi: axi@01c20054 {
	121	#clock-cells = <0>;
	122	compatible = "allwinner,sun4i-axi-clk";
	123	reg = <0x01c20054 0x4>;
	124	clocks = <&cpu>;
06067a2f	125	clock-output-names = "axi";
de7dc935 MR	126	};
	127
	128	ahb: ahb@01c20054 {
	129	#clock-cells = <0>;
	130	compatible = "allwinner,sun4i-ahb-clk";
	131	reg = <0x01c20054 0x4>;
	132	clocks = <&axi>;
06067a2f	133	clock-output-names = "ahb";
de7dc935 MR	134	};
de7dc935 MR	135
06067a2f	136	ahb_gates: clk@01c20060 {
de7dc935 MR	137	#clock-cells = <1>;
	138	compatible = "allwinner,sun7i-a20-ahb-gates-clk";
	139	reg = <0x01c20060 0x8>;
	140	clocks = <&ahb>;
	141	clock-output-names = "ahb_usb0", "ahb_ehci0",
	142	"ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
	143	"ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
	144	"ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
	145	"ahb_nand", "ahb_sdram", "ahb_ace",
	146	"ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
	147	"ahb_spi2", "ahb_spi3", "ahb_sata",
	148	"ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
	149	"ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
	150	"ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
	151	"ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
	152	"ahb_de_fe1", "ahb_gmac", "ahb_mp",
	153	"ahb_mali";
	154	};
	155
	156	apb0: apb0@01c20054 {
	157	#clock-cells = <0>;
	158	compatible = "allwinner,sun4i-apb0-clk";
	159	reg = <0x01c20054 0x4>;
	160	clocks = <&ahb>;
06067a2f	161	clock-output-names = "apb0";
de7dc935 MR	162	};
de7dc935 MR	163
06067a2f	164	apb0_gates: clk@01c20068 {
de7dc935 MR	165	#clock-cells = <1>;
	166	compatible = "allwinner,sun7i-a20-apb0-gates-clk";
	167	reg = <0x01c20068 0x4>;
	168	clocks = <&apb0>;
	169	clock-output-names = "apb0_codec", "apb0_spdif",
	170	"apb0_ac97", "apb0_iis0", "apb0_iis1",
	171	"apb0_pio", "apb0_ir0", "apb0_ir1",
	172	"apb0_iis2", "apb0_keypad";
	173	};
	174
	175	apb1_mux: apb1_mux@01c20058 {
	176	#clock-cells = <0>;
	177	compatible = "allwinner,sun4i-apb1-mux-clk";
	178	reg = <0x01c20058 0x4>;
c3e5e66b	179	clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
06067a2f	180	clock-output-names = "apb1_mux";
de7dc935 MR	181	};
	182
	183	apb1: apb1@01c20058 {
	184	#clock-cells = <0>;
	185	compatible = "allwinner,sun4i-apb1-clk";
	186	reg = <0x01c20058 0x4>;
	187	clocks = <&apb1_mux>;
06067a2f	188	clock-output-names = "apb1";
de7dc935 MR	189	};
de7dc935 MR	190
06067a2f	191	apb1_gates: clk@01c2006c {
de7dc935 MR	192	#clock-cells = <1>;
	193	compatible = "allwinner,sun7i-a20-apb1-gates-clk";
	194	reg = <0x01c2006c 0x4>;
	195	clocks = <&apb1>;
	196	clock-output-names = "apb1_i2c0", "apb1_i2c1",
	197	"apb1_i2c2", "apb1_i2c3", "apb1_can",
	198	"apb1_scr", "apb1_ps20", "apb1_ps21",
	199	"apb1_i2c4", "apb1_uart0", "apb1_uart1",
	200	"apb1_uart2", "apb1_uart3", "apb1_uart4",
	201	"apb1_uart5", "apb1_uart6", "apb1_uart7";
	202	};
1c92b95b EL	203
	204	nand_clk: clk@01c20080 {
	205	#clock-cells = <0>;
	206	compatible = "allwinner,sun4i-mod0-clk";
	207	reg = <0x01c20080 0x4>;
	208	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
	209	clock-output-names = "nand";
	210	};
	211
	212	ms_clk: clk@01c20084 {
	213	#clock-cells = <0>;
	214	compatible = "allwinner,sun4i-mod0-clk";
	215	reg = <0x01c20084 0x4>;
	216	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
	217	clock-output-names = "ms";
	218	};
	219
	220	mmc0_clk: clk@01c20088 {
	221	#clock-cells = <0>;
	222	compatible = "allwinner,sun4i-mod0-clk";
	223	reg = <0x01c20088 0x4>;
	224	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
	225	clock-output-names = "mmc0";
	226	};
	227
	228	mmc1_clk: clk@01c2008c {
	229	#clock-cells = <0>;
	230	compatible = "allwinner,sun4i-mod0-clk";
	231	reg = <0x01c2008c 0x4>;
	232	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
	233	clock-output-names = "mmc1";
	234	};
	235
	236	mmc2_clk: clk@01c20090 {
	237	#clock-cells = <0>;
	238	compatible = "allwinner,sun4i-mod0-clk";
	239	reg = <0x01c20090 0x4>;
	240	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
	241	clock-output-names = "mmc2";
	242	};
	243
	244	mmc3_clk: clk@01c20094 {
	245	#clock-cells = <0>;
	246	compatible = "allwinner,sun4i-mod0-clk";
	247	reg = <0x01c20094 0x4>;
	248	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
	249	clock-output-names = "mmc3";
	250	};
	251
	252	ts_clk: clk@01c20098 {
	253	#clock-cells = <0>;
	254	compatible = "allwinner,sun4i-mod0-clk";
	255	reg = <0x01c20098 0x4>;
	256	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
	257	clock-output-names = "ts";
	258	};
	259
	260	ss_clk: clk@01c2009c {
	261	#clock-cells = <0>;
	262	compatible = "allwinner,sun4i-mod0-clk";
	263	reg = <0x01c2009c 0x4>;
	264	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
	265	clock-output-names = "ss";
	266	};
267
268	spi0_clk: clk@01c200a0 {
269	#clock-cells = <0>;
270	compatible = "allwinner,sun4i-mod0-clk";
271	reg = <0x01c200a0 0x4>;
272	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
273	clock-output-names = "spi0";
274	};
275
276	spi1_clk: clk@01c200a4 {
277	#clock-cells = <0>;
278	compatible = "allwinner,sun4i-mod0-clk";
279	reg = <0x01c200a4 0x4>;
280	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
281	clock-output-names = "spi1";
282	};
283
284	spi2_clk: clk@01c200a8 {
285	#clock-cells = <0>;
286	compatible = "allwinner,sun4i-mod0-clk";
287	reg = <0x01c200a8 0x4>;
288	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
289	clock-output-names = "spi2";
290	};
291
292	pata_clk: clk@01c200ac {
293	#clock-cells = <0>;
294	compatible = "allwinner,sun4i-mod0-clk";
295	reg = <0x01c200ac 0x4>;
296	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
297	clock-output-names = "pata";
298	};
299
300	ir0_clk: clk@01c200b0 {
301	#clock-cells = <0>;
302	compatible = "allwinner,sun4i-mod0-clk";
303	reg = <0x01c200b0 0x4>;
304	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
305	clock-output-names = "ir0";
306	};
307
308	ir1_clk: clk@01c200b4 {
309	#clock-cells = <0>;
310	compatible = "allwinner,sun4i-mod0-clk";
311	reg = <0x01c200b4 0x4>;
312	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
313	clock-output-names = "ir1";
314	};
315
434e41b3 RB	316	usb_clk: clk@01c200cc {
	317	#clock-cells = <1>;
	318	#reset-cells = <1>;
	319	compatible = "allwinner,sun4i-a10-usb-clk";
	320	reg = <0x01c200cc 0x4>;
	321	clocks = <&pll6 1>;
	322	clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
	323	};
	324
1c92b95b EL	325	spi3_clk: clk@01c200d4 {
	326	#clock-cells = <0>;
	327	compatible = "allwinner,sun4i-mod0-clk";
	328	reg = <0x01c200d4 0x4>;
	329	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
	330	clock-output-names = "spi3";
	331	};
118c07ae EL	332
	333	mbus_clk: clk@01c2015c {
	334	#clock-cells = <0>;
	335	compatible = "allwinner,sun4i-mod0-clk";
	336	reg = <0x01c2015c 0x4>;
	337	clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
	338	clock-output-names = "mbus";
	339	};
0aff0370	340
daed5a81 CYT	341	/*
	342	* The following two are dummy clocks, placeholders used in the gmac_tx
	343	* clock. The gmac driver will choose one parent depending on the PHY
	344	* interface mode, using clk_set_rate auto-reparenting.
	345	* The actual TX clock rate is not controlled by the gmac_tx clock.
	346	*/
	347	mii_phy_tx_clk: clk@2 {
	348	#clock-cells = <0>;
	349	compatible = "fixed-clock";
	350	clock-frequency = <25000000>;
	351	clock-output-names = "mii_phy_tx";
	352	};
	353
	354	gmac_int_tx_clk: clk@3 {
	355	#clock-cells = <0>;
	356	compatible = "fixed-clock";
	357	clock-frequency = <125000000>;
	358	clock-output-names = "gmac_int_tx";
	359	};
	360
	361	gmac_tx_clk: clk@01c20164 {
	362	#clock-cells = <0>;
	363	compatible = "allwinner,sun7i-a20-gmac-clk";
	364	reg = <0x01c20164 0x4>;
	365	clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
	366	clock-output-names = "gmac_tx";
	367	};
	368
0aff0370 CYT	369	/*
	370	* Dummy clock used by output clocks
	371	*/
	372	osc24M_32k: clk@1 {
	373	#clock-cells = <0>;
	374	compatible = "fixed-factor-clock";
	375	clock-div = <750>;
	376	clock-mult = <1>;
	377	clocks = <&osc24M>;
	378	clock-output-names = "osc24M_32k";
	379	};
	380
	381	clk_out_a: clk@01c201f0 {
	382	#clock-cells = <0>;
	383	compatible = "allwinner,sun7i-a20-out-clk";
	384	reg = <0x01c201f0 0x4>;
	385	clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
	386	clock-output-names = "clk_out_a";
	387	};
	388
	389	clk_out_b: clk@01c201f4 {
	390	#clock-cells = <0>;
	391	compatible = "allwinner,sun7i-a20-out-clk";
	392	reg = <0x01c201f4 0x4>;
	393	clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
	394	clock-output-names = "clk_out_b";
	395	};
4790ecfa MR	396	};
	397
	398	soc@01c00000 {
	399	compatible = "simple-bus";
	400	#address-cells = <1>;
	401	#size-cells = <1>;
	402	ranges;
	403
2e804d03 MR	404	emac: ethernet@01c0b000 {
	405	compatible = "allwinner,sun4i-emac";
	406	reg = <0x01c0b000 0x1000>;
378d0aee	407	interrupts = <0 55 4>;
2e804d03 MR	408	clocks = <&ahb_gates 17>;
	409	status = "disabled";
	410	};
	411
	412	mdio@01c0b080 {
	413	compatible = "allwinner,sun4i-mdio";
	414	reg = <0x01c0b080 0x14>;
	415	status = "disabled";
	416	#address-cells = <1>;
	417	#size-cells = <0>;
	418	};
	419
17eac031 MR	420	pio: pinctrl@01c20800 {
	421	compatible = "allwinner,sun7i-a20-pinctrl";
	422	reg = <0x01c20800 0x400>;
378d0aee	423	interrupts = <0 28 4>;
de7dc935	424	clocks = <&apb0_gates 5>;
17eac031 MR	425	gpio-controller;
	426	interrupt-controller;
	427	#address-cells = <1>;
	428	#size-cells = <0>;
	429	#gpio-cells = <3>;
9f229ba9 MR	430
	431	uart0_pins_a: uart0@0 {
	432	allwinner,pins = "PB22", "PB23";
	433	allwinner,function = "uart0";
	434	allwinner,drive = <0>;
	435	allwinner,pull = <0>;
	436	};
	437
4261ec43 CYT	438	uart2_pins_a: uart2@0 {
	439	allwinner,pins = "PI16", "PI17", "PI18", "PI19";
	440	allwinner,function = "uart2";
	441	allwinner,drive = <0>;
	442	allwinner,pull = <0>;
	443	};
	444
9f229ba9 MR	445	uart6_pins_a: uart6@0 {
	446	allwinner,pins = "PI12", "PI13";
	447	allwinner,function = "uart6";
	448	allwinner,drive = <0>;
	449	allwinner,pull = <0>;
	450	};
	451
	452	uart7_pins_a: uart7@0 {
	453	allwinner,pins = "PI20", "PI21";
	454	allwinner,function = "uart7";
	455	allwinner,drive = <0>;
	456	allwinner,pull = <0>;
	457	};
756084c5	458
e5496a31 MR	459	i2c0_pins_a: i2c0@0 {
	460	allwinner,pins = "PB0", "PB1";
	461	allwinner,function = "i2c0";
	462	allwinner,drive = <0>;
	463	allwinner,pull = <0>;
	464	};
	465
	466	i2c1_pins_a: i2c1@0 {
	467	allwinner,pins = "PB18", "PB19";
	468	allwinner,function = "i2c1";
	469	allwinner,drive = <0>;
	470	allwinner,pull = <0>;
	471	};
	472
	473	i2c2_pins_a: i2c2@0 {
	474	allwinner,pins = "PB20", "PB21";
	475	allwinner,function = "i2c2";
	476	allwinner,drive = <0>;
	477	allwinner,pull = <0>;
	478	};
	479
756084c5 MR	480	emac_pins_a: emac0@0 {
	481	allwinner,pins = "PA0", "PA1", "PA2",
	482	"PA3", "PA4", "PA5", "PA6",
	483	"PA7", "PA8", "PA9", "PA10",
	484	"PA11", "PA12", "PA13", "PA14",
	485	"PA15", "PA16";
	486	allwinner,function = "emac";
	487	allwinner,drive = <0>;
	488	allwinner,pull = <0>;
	489	};
f2e0759e CYT	490
	491	clk_out_a_pins_a: clk_out_a@0 {
	492	allwinner,pins = "PI12";
	493	allwinner,function = "clk_out_a";
	494	allwinner,drive = <0>;
	495	allwinner,pull = <0>;
	496	};
	497
	498	clk_out_b_pins_a: clk_out_b@0 {
	499	allwinner,pins = "PI13";
	500	allwinner,function = "clk_out_b";
	501	allwinner,drive = <0>;
	502	allwinner,pull = <0>;
	503	};
129ccbcd CYT	504
	505	gmac_pins_mii_a: gmac_mii@0 {
	506	allwinner,pins = "PA0", "PA1", "PA2",
	507	"PA3", "PA4", "PA5", "PA6",
	508	"PA7", "PA8", "PA9", "PA10",
	509	"PA11", "PA12", "PA13", "PA14",
	510	"PA15", "PA16";
	511	allwinner,function = "gmac";
	512	allwinner,drive = <0>;
	513	allwinner,pull = <0>;
	514	};
	515
	516	gmac_pins_rgmii_a: gmac_rgmii@0 {
	517	allwinner,pins = "PA0", "PA1", "PA2",
	518	"PA3", "PA4", "PA5", "PA6",
	519	"PA7", "PA8", "PA10",
	520	"PA11", "PA12", "PA13",
	521	"PA15", "PA16";
	522	allwinner,function = "gmac";
	523	/*
	524	* data lines in RGMII mode use DDR mode
	525	* and need a higher signal drive strength
	526	*/
	527	allwinner,drive = <3>;
	528	allwinner,pull = <0>;
	529	};
17eac031 MR	530	};
17eac031 MR	531
4790ecfa MR	532	timer@01c20c00 {
	533	compatible = "allwinner,sun4i-timer";
	534	reg = <0x01c20c00 0x90>;
378d0aee MR	535	interrupts = <0 22 4>,
	536	<0 23 4>,
	537	<0 24 4>,
	538	<0 25 4>,
	539	<0 67 4>,
	540	<0 68 4>;
4790ecfa MR	541	clocks = <&osc24M>;
	542	};
	543
	544	wdt: watchdog@01c20c90 {
	545	compatible = "allwinner,sun4i-wdt";
	546	reg = <0x01c20c90 0x10>;
	547	};
	548
b5d905c7 CC	549	rtc: rtc@01c20d00 {
	550	compatible = "allwinner,sun7i-a20-rtc";
	551	reg = <0x01c20d00 0x20>;
	552	interrupts = <0 24 1>;
	553	};
	554
2bad969f OS	555	sid: eeprom@01c23800 {
	556	compatible = "allwinner,sun7i-a20-sid";
	557	reg = <0x01c23800 0x200>;
	558	};
	559
00f7ed8d HG	560	rtp: rtp@01c25000 {
	561	compatible = "allwinner,sun4i-ts";
	562	reg = <0x01c25000 0x100>;
	563	interrupts = <0 29 4>;
	564	};
	565
4790ecfa MR	566	uart0: serial@01c28000 {
	567	compatible = "snps,dw-apb-uart";
	568	reg = <0x01c28000 0x400>;
378d0aee	569	interrupts = <0 1 4>;
4790ecfa MR	570	reg-shift = <2>;
4790ecfa MR	571	reg-io-width = <4>;
de7dc935	572	clocks = <&apb1_gates 16>;
4790ecfa MR	573	status = "disabled";
	574	};
	575
	576	uart1: serial@01c28400 {
	577	compatible = "snps,dw-apb-uart";
	578	reg = <0x01c28400 0x400>;
378d0aee	579	interrupts = <0 2 4>;
4790ecfa MR	580	reg-shift = <2>;
4790ecfa MR	581	reg-io-width = <4>;
de7dc935	582	clocks = <&apb1_gates 17>;
4790ecfa MR	583	status = "disabled";
	584	};
	585
	586	uart2: serial@01c28800 {
	587	compatible = "snps,dw-apb-uart";
	588	reg = <0x01c28800 0x400>;
378d0aee	589	interrupts = <0 3 4>;
4790ecfa MR	590	reg-shift = <2>;
4790ecfa MR	591	reg-io-width = <4>;
de7dc935	592	clocks = <&apb1_gates 18>;
4790ecfa MR	593	status = "disabled";
	594	};
	595
	596	uart3: serial@01c28c00 {
	597	compatible = "snps,dw-apb-uart";
	598	reg = <0x01c28c00 0x400>;
378d0aee	599	interrupts = <0 4 4>;
4790ecfa MR	600	reg-shift = <2>;
4790ecfa MR	601	reg-io-width = <4>;
de7dc935	602	clocks = <&apb1_gates 19>;
4790ecfa MR	603	status = "disabled";
	604	};
	605
	606	uart4: serial@01c29000 {
	607	compatible = "snps,dw-apb-uart";
	608	reg = <0x01c29000 0x400>;
378d0aee	609	interrupts = <0 17 4>;
4790ecfa MR	610	reg-shift = <2>;
4790ecfa MR	611	reg-io-width = <4>;
de7dc935	612	clocks = <&apb1_gates 20>;
4790ecfa MR	613	status = "disabled";
	614	};
	615
	616	uart5: serial@01c29400 {
	617	compatible = "snps,dw-apb-uart";
	618	reg = <0x01c29400 0x400>;
378d0aee	619	interrupts = <0 18 4>;
4790ecfa MR	620	reg-shift = <2>;
4790ecfa MR	621	reg-io-width = <4>;
de7dc935	622	clocks = <&apb1_gates 21>;
4790ecfa MR	623	status = "disabled";
	624	};
	625
	626	uart6: serial@01c29800 {
	627	compatible = "snps,dw-apb-uart";
	628	reg = <0x01c29800 0x400>;
378d0aee	629	interrupts = <0 19 4>;
4790ecfa MR	630	reg-shift = <2>;
4790ecfa MR	631	reg-io-width = <4>;
de7dc935	632	clocks = <&apb1_gates 22>;
4790ecfa MR	633	status = "disabled";
	634	};
	635
	636	uart7: serial@01c29c00 {
	637	compatible = "snps,dw-apb-uart";
	638	reg = <0x01c29c00 0x400>;
378d0aee	639	interrupts = <0 20 4>;
4790ecfa MR	640	reg-shift = <2>;
4790ecfa MR	641	reg-io-width = <4>;
de7dc935	642	clocks = <&apb1_gates 23>;
4790ecfa MR	643	status = "disabled";
	644	};
	645
428abbb8 MR	646	i2c0: i2c@01c2ac00 {
	647	compatible = "allwinner,sun4i-i2c";
	648	reg = <0x01c2ac00 0x400>;
378d0aee	649	interrupts = <0 7 4>;
428abbb8 MR	650	clocks = <&apb1_gates 0>;
	651	clock-frequency = <100000>;
	652	status = "disabled";
	653	};
	654
	655	i2c1: i2c@01c2b000 {
	656	compatible = "allwinner,sun4i-i2c";
	657	reg = <0x01c2b000 0x400>;
378d0aee	658	interrupts = <0 8 4>;
428abbb8 MR	659	clocks = <&apb1_gates 1>;
	660	clock-frequency = <100000>;
	661	status = "disabled";
	662	};
	663
	664	i2c2: i2c@01c2b400 {
	665	compatible = "allwinner,sun4i-i2c";
	666	reg = <0x01c2b400 0x400>;
378d0aee	667	interrupts = <0 9 4>;
428abbb8 MR	668	clocks = <&apb1_gates 2>;
	669	clock-frequency = <100000>;
	670	status = "disabled";
	671	};
	672
	673	i2c3: i2c@01c2b800 {
	674	compatible = "allwinner,sun4i-i2c";
	675	reg = <0x01c2b800 0x400>;
378d0aee	676	interrupts = <0 88 4>;
428abbb8 MR	677	clocks = <&apb1_gates 3>;
	678	clock-frequency = <100000>;
	679	status = "disabled";
	680	};
	681
	682	i2c4: i2c@01c2bc00 {
	683	compatible = "allwinner,sun4i-i2c";
	684	reg = <0x01c2bc00 0x400>;
378d0aee	685	interrupts = <0 89 4>;
428abbb8 MR	686	clocks = <&apb1_gates 15>;
	687	clock-frequency = <100000>;
	688	status = "disabled";
	689	};
	690
c40b8d58 CYT	691	gmac: ethernet@01c50000 {
	692	compatible = "allwinner,sun7i-a20-gmac";
	693	reg = <0x01c50000 0x10000>;
	694	interrupts = <0 85 4>;
	695	interrupt-names = "macirq";
	696	clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
	697	clock-names = "stmmaceth", "allwinner_gmac_tx";
	698	snps,pbl = <2>;
	699	snps,fixed-burst;
	700	snps,force_sf_dma_mode;
	701	status = "disabled";
	702	#address-cells = <1>;
	703	#size-cells = <0>;
	704	};
	705
31f8ad38 MR	706	hstimer@01c60000 {
	707	compatible = "allwinner,sun7i-a20-hstimer";
	708	reg = <0x01c60000 0x1000>;
	709	interrupts = <0 81 1>,
	710	<0 82 1>,
	711	<0 83 1>,
	712	<0 84 1>;
	713	clocks = <&ahb_gates 28>;
	714	};
	715
4790ecfa MR	716	gic: interrupt-controller@01c81000 {
	717	compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
	718	reg = <0x01c81000 0x1000>,
	719	<0x01c82000 0x1000>,
	720	<0x01c84000 0x2000>,
	721	<0x01c86000 0x2000>;
	722	interrupt-controller;
	723	#interrupt-cells = <3>;
	724	interrupts = <1 9 0xf04>;
	725	};
	726	};
	727	};