projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 4790ecfa MR |
1 | /* |
| 2 | * Copyright 2013 Maxime Ripard | |
| 3 | * | |
| 4 | * Maxime Ripard <maxime.ripard@free-electrons.com> | |
| 5 | * | |
| 6 | * The code contained herein is licensed under the GNU General Public | |
| 7 | * License. You may obtain a copy of the GNU General Public License | |
| 8 | * Version 2 or later at the following locations: | |
| 9 | * | |
| 10 | * http://www.opensource.org/licenses/gpl-license.html | |
| 11 | * http://www.gnu.org/copyleft/gpl.html | |
| 12 | */ | |
| 13 | ||
| 14 | /include/ "skeleton.dtsi" | |
| 15 | ||
| 16 | / { | |
| 17 | interrupt-parent = <&gic>; | |
| 18 | ||
| e751cce9 | 19 | aliases { |
| 18428f77 | 20 | ethernet0 = &gmac; |
| 4566b4be MR |
21 | serial0 = &uart0; |
| 22 | serial1 = &uart1; | |
| 23 | serial2 = &uart2; | |
| 24 | serial3 = &uart3; | |
| 25 | serial4 = &uart4; | |
| 26 | serial5 = &uart5; | |
| 27 | serial6 = &uart6; | |
| 28 | serial7 = &uart7; | |
| e751cce9 EL |
29 | }; |
| 30 | ||
| 4790ecfa MR |
31 | cpus { |
| 32 | #address-cells = <1>; | |
| 33 | #size-cells = <0>; | |
| 34 | ||
| 35 | cpu@0 { | |
| 36 | compatible = "arm,cortex-a7"; | |
| 37 | device_type = "cpu"; | |
| 38 | reg = <0>; | |
| 39 | }; | |
| 40 | ||
| 41 | cpu@1 { | |
| 42 | compatible = "arm,cortex-a7"; | |
| 43 | device_type = "cpu"; | |
| 44 | reg = <1>; | |
| 45 | }; | |
| 46 | }; | |
| 47 | ||
| 48 | memory { | |
| 49 | reg = <0x40000000 0x80000000>; | |
| 50 | }; | |
| 51 | ||
| 7902763e MZ |
52 | timer { |
| 53 | compatible = "arm,armv7-timer"; | |
| 54 | interrupts = <1 13 0xf08>, | |
| 55 | <1 14 0xf08>, | |
| 56 | <1 11 0xf08>, | |
| 57 | <1 10 0xf08>; | |
| 58 | }; | |
| 59 | ||
| e29ea4d3 MR |
60 | pmu { |
| 61 | compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu"; | |
| 62 | interrupts = <0 120 4>, | |
| 63 | <0 121 4>; | |
| 64 | }; | |
| 65 | ||
| 4790ecfa MR |
66 | clocks { |
| 67 | #address-cells = <1>; | |
| 68 | #size-cells = <1>; | |
| 69 | ranges; | |
| 70 | ||
| 06067a2f | 71 | osc24M: clk@01c20050 { |
| 4790ecfa | 72 | #clock-cells = <0>; |
| bf6534a1 | 73 | compatible = "allwinner,sun4i-a10-osc-clk"; |
| de7dc935 | 74 | reg = <0x01c20050 0x4>; |
| 4790ecfa | 75 | clock-frequency = <24000000>; |
| 06067a2f | 76 | clock-output-names = "osc24M"; |
| 4790ecfa MR |
77 | }; |
| 78 | ||
| 673fac74 | 79 | osc32k: clk@0 { |
| 4790ecfa MR |
80 | #clock-cells = <0>; |
| 81 | compatible = "fixed-clock"; | |
| 82 | clock-frequency = <32768>; | |
| 673fac74 | 83 | clock-output-names = "osc32k"; |
| 4790ecfa | 84 | }; |
| de7dc935 | 85 | |
| 06067a2f | 86 | pll1: clk@01c20000 { |
| de7dc935 | 87 | #clock-cells = <0>; |
| bf6534a1 | 88 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
| de7dc935 MR |
89 | reg = <0x01c20000 0x4>; |
| 90 | clocks = <&osc24M>; | |
| 06067a2f | 91 | clock-output-names = "pll1"; |
| de7dc935 MR |
92 | }; |
| 93 | ||
| 06067a2f | 94 | pll4: clk@01c20018 { |
| de7dc935 | 95 | #clock-cells = <0>; |
| 04ebcb54 | 96 | compatible = "allwinner,sun7i-a20-pll4-clk"; |
| ec5589f7 EL |
97 | reg = <0x01c20018 0x4>; |
| 98 | clocks = <&osc24M>; | |
| 06067a2f | 99 | clock-output-names = "pll4"; |
| ec5589f7 EL |
100 | }; |
| 101 | ||
| 06067a2f | 102 | pll5: clk@01c20020 { |
| c3e5e66b | 103 | #clock-cells = <1>; |
| bf6534a1 | 104 | compatible = "allwinner,sun4i-a10-pll5-clk"; |
| c3e5e66b EL |
105 | reg = <0x01c20020 0x4>; |
| 106 | clocks = <&osc24M>; | |
| 107 | clock-output-names = "pll5_ddr", "pll5_other"; | |
| 108 | }; | |
| 109 | ||
| 06067a2f | 110 | pll6: clk@01c20028 { |
| c3e5e66b | 111 | #clock-cells = <1>; |
| bf6534a1 | 112 | compatible = "allwinner,sun4i-a10-pll6-clk"; |
| c3e5e66b EL |
113 | reg = <0x01c20028 0x4>; |
| 114 | clocks = <&osc24M>; | |
| 115 | clock-output-names = "pll6_sata", "pll6_other", "pll6"; | |
| de7dc935 MR |
116 | }; |
| 117 | ||
| 04ebcb54 EL |
118 | pll8: clk@01c20040 { |
| 119 | #clock-cells = <0>; | |
| 120 | compatible = "allwinner,sun7i-a20-pll4-clk"; | |
| 121 | reg = <0x01c20040 0x4>; | |
| 122 | clocks = <&osc24M>; | |
| 123 | clock-output-names = "pll8"; | |
| 124 | }; | |
| 125 | ||
| de7dc935 MR |
126 | cpu: cpu@01c20054 { |
| 127 | #clock-cells = <0>; | |
| bf6534a1 | 128 | compatible = "allwinner,sun4i-a10-cpu-clk"; |
| de7dc935 | 129 | reg = <0x01c20054 0x4>; |
| c3e5e66b | 130 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>; |
| 06067a2f | 131 | clock-output-names = "cpu"; |
| de7dc935 MR |
132 | }; |
| 133 | ||
| 134 | axi: axi@01c20054 { | |
| 135 | #clock-cells = <0>; | |
| bf6534a1 | 136 | compatible = "allwinner,sun4i-a10-axi-clk"; |
| de7dc935 MR |
137 | reg = <0x01c20054 0x4>; |
| 138 | clocks = <&cpu>; | |
| 06067a2f | 139 | clock-output-names = "axi"; |
| de7dc935 MR |
140 | }; |
| 141 | ||
| 142 | ahb: ahb@01c20054 { | |
| 143 | #clock-cells = <0>; | |
| bf6534a1 | 144 | compatible = "allwinner,sun4i-a10-ahb-clk"; |
| de7dc935 MR |
145 | reg = <0x01c20054 0x4>; |
| 146 | clocks = <&axi>; | |
| 06067a2f | 147 | clock-output-names = "ahb"; |
| de7dc935 MR |
148 | }; |
| 149 | ||
| 06067a2f | 150 | ahb_gates: clk@01c20060 { |
| de7dc935 MR |
151 | #clock-cells = <1>; |
| 152 | compatible = "allwinner,sun7i-a20-ahb-gates-clk"; | |
| 153 | reg = <0x01c20060 0x8>; | |
| 154 | clocks = <&ahb>; | |
| 155 | clock-output-names = "ahb_usb0", "ahb_ehci0", | |
| 156 | "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", | |
| 157 | "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0", | |
| 158 | "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms", | |
| 159 | "ahb_nand", "ahb_sdram", "ahb_ace", | |
| 160 | "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1", | |
| 161 | "ahb_spi2", "ahb_spi3", "ahb_sata", | |
| 162 | "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0", | |
| 163 | "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0", | |
| 164 | "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0", | |
| 165 | "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0", | |
| 166 | "ahb_de_fe1", "ahb_gmac", "ahb_mp", | |
| 167 | "ahb_mali"; | |
| 168 | }; | |
| 169 | ||
| 170 | apb0: apb0@01c20054 { | |
| 171 | #clock-cells = <0>; | |
| bf6534a1 | 172 | compatible = "allwinner,sun4i-a10-apb0-clk"; |
| de7dc935 MR |
173 | reg = <0x01c20054 0x4>; |
| 174 | clocks = <&ahb>; | |
| 06067a2f | 175 | clock-output-names = "apb0"; |
| de7dc935 MR |
176 | }; |
| 177 | ||
| 06067a2f | 178 | apb0_gates: clk@01c20068 { |
| de7dc935 MR |
179 | #clock-cells = <1>; |
| 180 | compatible = "allwinner,sun7i-a20-apb0-gates-clk"; | |
| 181 | reg = <0x01c20068 0x4>; | |
| 182 | clocks = <&apb0>; | |
| 183 | clock-output-names = "apb0_codec", "apb0_spdif", | |
| 184 | "apb0_ac97", "apb0_iis0", "apb0_iis1", | |
| 185 | "apb0_pio", "apb0_ir0", "apb0_ir1", | |
| 186 | "apb0_iis2", "apb0_keypad"; | |
| 187 | }; | |
| 188 | ||
| 189 | apb1_mux: apb1_mux@01c20058 { | |
| 190 | #clock-cells = <0>; | |
| bf6534a1 | 191 | compatible = "allwinner,sun4i-a10-apb1-mux-clk"; |
| de7dc935 | 192 | reg = <0x01c20058 0x4>; |
| c3e5e66b | 193 | clocks = <&osc24M>, <&pll6 1>, <&osc32k>; |
| 06067a2f | 194 | clock-output-names = "apb1_mux"; |
| de7dc935 MR |
195 | }; |
| 196 | ||
| 197 | apb1: apb1@01c20058 { | |
| 198 | #clock-cells = <0>; | |
| bf6534a1 | 199 | compatible = "allwinner,sun4i-a10-apb1-clk"; |
| de7dc935 MR |
200 | reg = <0x01c20058 0x4>; |
| 201 | clocks = <&apb1_mux>; | |
| 06067a2f | 202 | clock-output-names = "apb1"; |
| de7dc935 MR |
203 | }; |
| 204 | ||
| 06067a2f | 205 | apb1_gates: clk@01c2006c { |
| de7dc935 MR |
206 | #clock-cells = <1>; |
| 207 | compatible = "allwinner,sun7i-a20-apb1-gates-clk"; | |
| 208 | reg = <0x01c2006c 0x4>; | |
| 209 | clocks = <&apb1>; | |
| 210 | clock-output-names = "apb1_i2c0", "apb1_i2c1", | |
| 211 | "apb1_i2c2", "apb1_i2c3", "apb1_can", | |
| 212 | "apb1_scr", "apb1_ps20", "apb1_ps21", | |
| 213 | "apb1_i2c4", "apb1_uart0", "apb1_uart1", | |
| 214 | "apb1_uart2", "apb1_uart3", "apb1_uart4", | |
| 215 | "apb1_uart5", "apb1_uart6", "apb1_uart7"; | |
| 216 | }; | |
| 1c92b95b EL |
217 | |
| 218 | nand_clk: clk@01c20080 { | |
| 219 | #clock-cells = <0>; | |
| bf6534a1 | 220 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
221 | reg = <0x01c20080 0x4>; |
| 222 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 223 | clock-output-names = "nand"; | |
| 224 | }; | |
| 225 | ||
| 226 | ms_clk: clk@01c20084 { | |
| 227 | #clock-cells = <0>; | |
| bf6534a1 | 228 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
229 | reg = <0x01c20084 0x4>; |
| 230 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 231 | clock-output-names = "ms"; | |
| 232 | }; | |
| 233 | ||
| 234 | mmc0_clk: clk@01c20088 { | |
| 235 | #clock-cells = <0>; | |
| bf6534a1 | 236 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
237 | reg = <0x01c20088 0x4>; |
| 238 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 239 | clock-output-names = "mmc0"; | |
| 240 | }; | |
| 241 | ||
| 242 | mmc1_clk: clk@01c2008c { | |
| 243 | #clock-cells = <0>; | |
| bf6534a1 | 244 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
245 | reg = <0x01c2008c 0x4>; |
| 246 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 247 | clock-output-names = "mmc1"; | |
| 248 | }; | |
| 249 | ||
| 250 | mmc2_clk: clk@01c20090 { | |
| 251 | #clock-cells = <0>; | |
| bf6534a1 | 252 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
253 | reg = <0x01c20090 0x4>; |
| 254 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 255 | clock-output-names = "mmc2"; | |
| 256 | }; | |
| 257 | ||
| 258 | mmc3_clk: clk@01c20094 { | |
| 259 | #clock-cells = <0>; | |
| bf6534a1 | 260 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
261 | reg = <0x01c20094 0x4>; |
| 262 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 263 | clock-output-names = "mmc3"; | |
| 264 | }; | |
| 265 | ||
| 266 | ts_clk: clk@01c20098 { | |
| 267 | #clock-cells = <0>; | |
| bf6534a1 | 268 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
269 | reg = <0x01c20098 0x4>; |
| 270 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 271 | clock-output-names = "ts"; | |
| 272 | }; | |
| 273 | ||
| 274 | ss_clk: clk@01c2009c { | |
| 275 | #clock-cells = <0>; | |
| bf6534a1 | 276 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
277 | reg = <0x01c2009c 0x4>; |
| 278 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 279 | clock-output-names = "ss"; | |
| 280 | }; | |
| 281 | ||
| 282 | spi0_clk: clk@01c200a0 { | |
| 283 | #clock-cells = <0>; | |
| bf6534a1 | 284 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
285 | reg = <0x01c200a0 0x4>; |
| 286 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 287 | clock-output-names = "spi0"; | |
| 288 | }; | |
| 289 | ||
| 290 | spi1_clk: clk@01c200a4 { | |
| 291 | #clock-cells = <0>; | |
| bf6534a1 | 292 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
293 | reg = <0x01c200a4 0x4>; |
| 294 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 295 | clock-output-names = "spi1"; | |
| 296 | }; | |
| 297 | ||
| 298 | spi2_clk: clk@01c200a8 { | |
| 299 | #clock-cells = <0>; | |
| bf6534a1 | 300 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
301 | reg = <0x01c200a8 0x4>; |
| 302 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 303 | clock-output-names = "spi2"; | |
| 304 | }; | |
| 305 | ||
| 306 | pata_clk: clk@01c200ac { | |
| 307 | #clock-cells = <0>; | |
| bf6534a1 | 308 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
309 | reg = <0x01c200ac 0x4>; |
| 310 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 311 | clock-output-names = "pata"; | |
| 312 | }; | |
| 313 | ||
| 314 | ir0_clk: clk@01c200b0 { | |
| 315 | #clock-cells = <0>; | |
| bf6534a1 | 316 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
317 | reg = <0x01c200b0 0x4>; |
| 318 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 319 | clock-output-names = "ir0"; | |
| 320 | }; | |
| 321 | ||
| 322 | ir1_clk: clk@01c200b4 { | |
| 323 | #clock-cells = <0>; | |
| bf6534a1 | 324 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
325 | reg = <0x01c200b4 0x4>; |
| 326 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 327 | clock-output-names = "ir1"; | |
| 328 | }; | |
| 329 | ||
| 434e41b3 RB |
330 | usb_clk: clk@01c200cc { |
| 331 | #clock-cells = <1>; | |
| 332 | #reset-cells = <1>; | |
| 333 | compatible = "allwinner,sun4i-a10-usb-clk"; | |
| 334 | reg = <0x01c200cc 0x4>; | |
| 335 | clocks = <&pll6 1>; | |
| 336 | clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy"; | |
| 337 | }; | |
| 338 | ||
| 1c92b95b EL |
339 | spi3_clk: clk@01c200d4 { |
| 340 | #clock-cells = <0>; | |
| bf6534a1 | 341 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
342 | reg = <0x01c200d4 0x4>; |
| 343 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 344 | clock-output-names = "spi3"; | |
| 345 | }; | |
| 118c07ae EL |
346 | |
| 347 | mbus_clk: clk@01c2015c { | |
| 348 | #clock-cells = <0>; | |
| bf6534a1 | 349 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 118c07ae EL |
350 | reg = <0x01c2015c 0x4>; |
| 351 | clocks = <&osc24M>, <&pll6 2>, <&pll5 1>; | |
| 352 | clock-output-names = "mbus"; | |
| 353 | }; | |
| 0aff0370 | 354 | |
| daed5a81 CYT |
355 | /* |
| 356 | * The following two are dummy clocks, placeholders used in the gmac_tx | |
| 357 | * clock. The gmac driver will choose one parent depending on the PHY | |
| 358 | * interface mode, using clk_set_rate auto-reparenting. | |
| 359 | * The actual TX clock rate is not controlled by the gmac_tx clock. | |
| 360 | */ | |
| 361 | mii_phy_tx_clk: clk@2 { | |
| 362 | #clock-cells = <0>; | |
| 363 | compatible = "fixed-clock"; | |
| 364 | clock-frequency = <25000000>; | |
| 365 | clock-output-names = "mii_phy_tx"; | |
| 366 | }; | |
| 367 | ||
| 368 | gmac_int_tx_clk: clk@3 { | |
| 369 | #clock-cells = <0>; | |
| 370 | compatible = "fixed-clock"; | |
| 371 | clock-frequency = <125000000>; | |
| 372 | clock-output-names = "gmac_int_tx"; | |
| 373 | }; | |
| 374 | ||
| 375 | gmac_tx_clk: clk@01c20164 { | |
| 376 | #clock-cells = <0>; | |
| 377 | compatible = "allwinner,sun7i-a20-gmac-clk"; | |
| 378 | reg = <0x01c20164 0x4>; | |
| 379 | clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; | |
| 380 | clock-output-names = "gmac_tx"; | |
| 381 | }; | |
| 382 | ||
| 0aff0370 CYT |
383 | /* |
| 384 | * Dummy clock used by output clocks | |
| 385 | */ | |
| 386 | osc24M_32k: clk@1 { | |
| 387 | #clock-cells = <0>; | |
| 388 | compatible = "fixed-factor-clock"; | |
| 389 | clock-div = <750>; | |
| 390 | clock-mult = <1>; | |
| 391 | clocks = <&osc24M>; | |
| 392 | clock-output-names = "osc24M_32k"; | |
| 393 | }; | |
| 394 | ||
| 395 | clk_out_a: clk@01c201f0 { | |
| 396 | #clock-cells = <0>; | |
| 397 | compatible = "allwinner,sun7i-a20-out-clk"; | |
| 398 | reg = <0x01c201f0 0x4>; | |
| 399 | clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; | |
| 400 | clock-output-names = "clk_out_a"; | |
| 401 | }; | |
| 402 | ||
| 403 | clk_out_b: clk@01c201f4 { | |
| 404 | #clock-cells = <0>; | |
| 405 | compatible = "allwinner,sun7i-a20-out-clk"; | |
| 406 | reg = <0x01c201f4 0x4>; | |
| 407 | clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; | |
| 408 | clock-output-names = "clk_out_b"; | |
| 409 | }; | |
| 4790ecfa MR |
410 | }; |
| 411 | ||
| 412 | soc@01c00000 { | |
| 413 | compatible = "simple-bus"; | |
| 414 | #address-cells = <1>; | |
| 415 | #size-cells = <1>; | |
| 416 | ranges; | |
| 417 | ||
| 8ff973a2 CC |
418 | nmi_intc: interrupt-controller@01c00030 { |
| 419 | compatible = "allwinner,sun7i-a20-sc-nmi"; | |
| 420 | interrupt-controller; | |
| 421 | #interrupt-cells = <2>; | |
| 422 | reg = <0x01c00030 0x0c>; | |
| 423 | interrupts = <0 0 4>; | |
| 424 | }; | |
| 425 | ||
| 36ab3e73 MR |
426 | spi0: spi@01c05000 { |
| 427 | compatible = "allwinner,sun4i-a10-spi"; | |
| 428 | reg = <0x01c05000 0x1000>; | |
| 429 | interrupts = <0 10 4>; | |
| 430 | clocks = <&ahb_gates 20>, <&spi0_clk>; | |
| 431 | clock-names = "ahb", "mod"; | |
| 432 | status = "disabled"; | |
| 433 | #address-cells = <1>; | |
| 434 | #size-cells = <0>; | |
| 435 | }; | |
| 436 | ||
| 437 | spi1: spi@01c06000 { | |
| 438 | compatible = "allwinner,sun4i-a10-spi"; | |
| 439 | reg = <0x01c06000 0x1000>; | |
| 440 | interrupts = <0 11 4>; | |
| 441 | clocks = <&ahb_gates 21>, <&spi1_clk>; | |
| 442 | clock-names = "ahb", "mod"; | |
| 443 | status = "disabled"; | |
| 444 | #address-cells = <1>; | |
| 445 | #size-cells = <0>; | |
| 446 | }; | |
| 447 | ||
| 2e804d03 | 448 | emac: ethernet@01c0b000 { |
| 1c70e099 | 449 | compatible = "allwinner,sun4i-a10-emac"; |
| 2e804d03 | 450 | reg = <0x01c0b000 0x1000>; |
| 378d0aee | 451 | interrupts = <0 55 4>; |
| 2e804d03 MR |
452 | clocks = <&ahb_gates 17>; |
| 453 | status = "disabled"; | |
| 454 | }; | |
| 455 | ||
| 456 | mdio@01c0b080 { | |
| 1c70e099 | 457 | compatible = "allwinner,sun4i-a10-mdio"; |
| 2e804d03 MR |
458 | reg = <0x01c0b080 0x14>; |
| 459 | status = "disabled"; | |
| 460 | #address-cells = <1>; | |
| 461 | #size-cells = <0>; | |
| 462 | }; | |
| 463 | ||
| dd29ce53 HG |
464 | mmc0: mmc@01c0f000 { |
| 465 | compatible = "allwinner,sun5i-a13-mmc"; | |
| 466 | reg = <0x01c0f000 0x1000>; | |
| 467 | clocks = <&ahb_gates 8>, <&mmc0_clk>; | |
| 468 | clock-names = "ahb", "mmc"; | |
| 469 | interrupts = <0 32 4>; | |
| 470 | status = "disabled"; | |
| 471 | }; | |
| 472 | ||
| 473 | mmc1: mmc@01c10000 { | |
| 474 | compatible = "allwinner,sun5i-a13-mmc"; | |
| 475 | reg = <0x01c10000 0x1000>; | |
| 476 | clocks = <&ahb_gates 9>, <&mmc1_clk>; | |
| 477 | clock-names = "ahb", "mmc"; | |
| 478 | interrupts = <0 33 4>; | |
| 479 | status = "disabled"; | |
| 480 | }; | |
| 481 | ||
| 482 | mmc2: mmc@01c11000 { | |
| 483 | compatible = "allwinner,sun5i-a13-mmc"; | |
| 484 | reg = <0x01c11000 0x1000>; | |
| 485 | clocks = <&ahb_gates 10>, <&mmc2_clk>; | |
| 486 | clock-names = "ahb", "mmc"; | |
| 487 | interrupts = <0 34 4>; | |
| 488 | status = "disabled"; | |
| 489 | }; | |
| 490 | ||
| 491 | mmc3: mmc@01c12000 { | |
| 492 | compatible = "allwinner,sun5i-a13-mmc"; | |
| 493 | reg = <0x01c12000 0x1000>; | |
| 494 | clocks = <&ahb_gates 11>, <&mmc3_clk>; | |
| 495 | clock-names = "ahb", "mmc"; | |
| 496 | interrupts = <0 35 4>; | |
| 497 | status = "disabled"; | |
| 498 | }; | |
| 499 | ||
| 9debd0a2 RB |
500 | usbphy: phy@01c13400 { |
| 501 | #phy-cells = <1>; | |
| 502 | compatible = "allwinner,sun7i-a20-usb-phy"; | |
| 503 | reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; | |
| 504 | reg-names = "phy_ctrl", "pmu1", "pmu2"; | |
| 505 | clocks = <&usb_clk 8>; | |
| 506 | clock-names = "usb_phy"; | |
| 507 | resets = <&usb_clk 1>, <&usb_clk 2>; | |
| 508 | reset-names = "usb1_reset", "usb2_reset"; | |
| 509 | status = "disabled"; | |
| 510 | }; | |
| 511 | ||
| 512 | ehci0: usb@01c14000 { | |
| 513 | compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; | |
| 514 | reg = <0x01c14000 0x100>; | |
| 515 | interrupts = <0 39 4>; | |
| 516 | clocks = <&ahb_gates 1>; | |
| 517 | phys = <&usbphy 1>; | |
| 518 | phy-names = "usb"; | |
| 519 | status = "disabled"; | |
| 520 | }; | |
| 521 | ||
| 522 | ohci0: usb@01c14400 { | |
| 523 | compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; | |
| 524 | reg = <0x01c14400 0x100>; | |
| 525 | interrupts = <0 64 4>; | |
| 526 | clocks = <&usb_clk 6>, <&ahb_gates 2>; | |
| 527 | phys = <&usbphy 1>; | |
| 528 | phy-names = "usb"; | |
| 529 | status = "disabled"; | |
| 530 | }; | |
| 531 | ||
| 36ab3e73 MR |
532 | spi2: spi@01c17000 { |
| 533 | compatible = "allwinner,sun4i-a10-spi"; | |
| 534 | reg = <0x01c17000 0x1000>; | |
| 535 | interrupts = <0 12 4>; | |
| 536 | clocks = <&ahb_gates 22>, <&spi2_clk>; | |
| 537 | clock-names = "ahb", "mod"; | |
| 538 | status = "disabled"; | |
| 539 | #address-cells = <1>; | |
| 540 | #size-cells = <0>; | |
| 541 | }; | |
| 542 | ||
| 902febf9 HG |
543 | ahci: sata@01c18000 { |
| 544 | compatible = "allwinner,sun4i-a10-ahci"; | |
| 545 | reg = <0x01c18000 0x1000>; | |
| 546 | interrupts = <0 56 4>; | |
| 547 | clocks = <&pll6 0>, <&ahb_gates 25>; | |
| 548 | status = "disabled"; | |
| 549 | }; | |
| 550 | ||
| 9debd0a2 RB |
551 | ehci1: usb@01c1c000 { |
| 552 | compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; | |
| 553 | reg = <0x01c1c000 0x100>; | |
| 554 | interrupts = <0 40 4>; | |
| 555 | clocks = <&ahb_gates 3>; | |
| 556 | phys = <&usbphy 2>; | |
| 557 | phy-names = "usb"; | |
| 558 | status = "disabled"; | |
| 559 | }; | |
| 560 | ||
| 561 | ohci1: usb@01c1c400 { | |
| 562 | compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; | |
| 563 | reg = <0x01c1c400 0x100>; | |
| 564 | interrupts = <0 65 4>; | |
| 565 | clocks = <&usb_clk 7>, <&ahb_gates 4>; | |
| 566 | phys = <&usbphy 2>; | |
| 567 | phy-names = "usb"; | |
| 568 | status = "disabled"; | |
| 569 | }; | |
| 570 | ||
| 36ab3e73 MR |
571 | spi3: spi@01c1f000 { |
| 572 | compatible = "allwinner,sun4i-a10-spi"; | |
| 573 | reg = <0x01c1f000 0x1000>; | |
| 574 | interrupts = <0 50 4>; | |
| 575 | clocks = <&ahb_gates 23>, <&spi3_clk>; | |
| 576 | clock-names = "ahb", "mod"; | |
| 577 | status = "disabled"; | |
| 2e804d03 MR |
578 | #address-cells = <1>; |
| 579 | #size-cells = <0>; | |
| 580 | }; | |
| 581 | ||
| 17eac031 MR |
582 | pio: pinctrl@01c20800 { |
| 583 | compatible = "allwinner,sun7i-a20-pinctrl"; | |
| 584 | reg = <0x01c20800 0x400>; | |
| 378d0aee | 585 | interrupts = <0 28 4>; |
| de7dc935 | 586 | clocks = <&apb0_gates 5>; |
| 17eac031 MR |
587 | gpio-controller; |
| 588 | interrupt-controller; | |
| 589 | #address-cells = <1>; | |
| 590 | #size-cells = <0>; | |
| 591 | #gpio-cells = <3>; | |
| 9f229ba9 | 592 | |
| fd7898a2 AB |
593 | pwm0_pins_a: pwm0@0 { |
| 594 | allwinner,pins = "PB2"; | |
| 595 | allwinner,function = "pwm"; | |
| 596 | allwinner,drive = <0>; | |
| 597 | allwinner,pull = <0>; | |
| 598 | }; | |
| 599 | ||
| 600 | pwm1_pins_a: pwm1@0 { | |
| 601 | allwinner,pins = "PI3"; | |
| 602 | allwinner,function = "pwm"; | |
| 603 | allwinner,drive = <0>; | |
| 604 | allwinner,pull = <0>; | |
| 605 | }; | |
| 606 | ||
| 9f229ba9 MR |
607 | uart0_pins_a: uart0@0 { |
| 608 | allwinner,pins = "PB22", "PB23"; | |
| 609 | allwinner,function = "uart0"; | |
| 610 | allwinner,drive = <0>; | |
| 611 | allwinner,pull = <0>; | |
| 612 | }; | |
| 613 | ||
| 4261ec43 CYT |
614 | uart2_pins_a: uart2@0 { |
| 615 | allwinner,pins = "PI16", "PI17", "PI18", "PI19"; | |
| 616 | allwinner,function = "uart2"; | |
| 617 | allwinner,drive = <0>; | |
| 618 | allwinner,pull = <0>; | |
| 619 | }; | |
| 620 | ||
| 9f229ba9 MR |
621 | uart6_pins_a: uart6@0 { |
| 622 | allwinner,pins = "PI12", "PI13"; | |
| 623 | allwinner,function = "uart6"; | |
| 624 | allwinner,drive = <0>; | |
| 625 | allwinner,pull = <0>; | |
| 626 | }; | |
| 627 | ||
| 628 | uart7_pins_a: uart7@0 { | |
| 629 | allwinner,pins = "PI20", "PI21"; | |
| 630 | allwinner,function = "uart7"; | |
| 631 | allwinner,drive = <0>; | |
| 632 | allwinner,pull = <0>; | |
| 633 | }; | |
| 756084c5 | 634 | |
| e5496a31 MR |
635 | i2c0_pins_a: i2c0@0 { |
| 636 | allwinner,pins = "PB0", "PB1"; | |
| 637 | allwinner,function = "i2c0"; | |
| 638 | allwinner,drive = <0>; | |
| 639 | allwinner,pull = <0>; | |
| 640 | }; | |
| 641 | ||
| 642 | i2c1_pins_a: i2c1@0 { | |
| 643 | allwinner,pins = "PB18", "PB19"; | |
| 644 | allwinner,function = "i2c1"; | |
| 645 | allwinner,drive = <0>; | |
| 646 | allwinner,pull = <0>; | |
| 647 | }; | |
| 648 | ||
| 649 | i2c2_pins_a: i2c2@0 { | |
| 650 | allwinner,pins = "PB20", "PB21"; | |
| 651 | allwinner,function = "i2c2"; | |
| 652 | allwinner,drive = <0>; | |
| 653 | allwinner,pull = <0>; | |
| 654 | }; | |
| 655 | ||
| 756084c5 MR |
656 | emac_pins_a: emac0@0 { |
| 657 | allwinner,pins = "PA0", "PA1", "PA2", | |
| 658 | "PA3", "PA4", "PA5", "PA6", | |
| 659 | "PA7", "PA8", "PA9", "PA10", | |
| 660 | "PA11", "PA12", "PA13", "PA14", | |
| 661 | "PA15", "PA16"; | |
| 662 | allwinner,function = "emac"; | |
| 663 | allwinner,drive = <0>; | |
| 664 | allwinner,pull = <0>; | |
| 665 | }; | |
| f2e0759e CYT |
666 | |
| 667 | clk_out_a_pins_a: clk_out_a@0 { | |
| 668 | allwinner,pins = "PI12"; | |
| 669 | allwinner,function = "clk_out_a"; | |
| 670 | allwinner,drive = <0>; | |
| 671 | allwinner,pull = <0>; | |
| 672 | }; | |
| 673 | ||
| 674 | clk_out_b_pins_a: clk_out_b@0 { | |
| 675 | allwinner,pins = "PI13"; | |
| 676 | allwinner,function = "clk_out_b"; | |
| 677 | allwinner,drive = <0>; | |
| 678 | allwinner,pull = <0>; | |
| 679 | }; | |
| 129ccbcd CYT |
680 | |
| 681 | gmac_pins_mii_a: gmac_mii@0 { | |
| 682 | allwinner,pins = "PA0", "PA1", "PA2", | |
| 683 | "PA3", "PA4", "PA5", "PA6", | |
| 684 | "PA7", "PA8", "PA9", "PA10", | |
| 685 | "PA11", "PA12", "PA13", "PA14", | |
| 686 | "PA15", "PA16"; | |
| 687 | allwinner,function = "gmac"; | |
| 688 | allwinner,drive = <0>; | |
| 689 | allwinner,pull = <0>; | |
| 690 | }; | |
| 691 | ||
| 692 | gmac_pins_rgmii_a: gmac_rgmii@0 { | |
| 693 | allwinner,pins = "PA0", "PA1", "PA2", | |
| 694 | "PA3", "PA4", "PA5", "PA6", | |
| 695 | "PA7", "PA8", "PA10", | |
| 696 | "PA11", "PA12", "PA13", | |
| 697 | "PA15", "PA16"; | |
| 698 | allwinner,function = "gmac"; | |
| 699 | /* | |
| 700 | * data lines in RGMII mode use DDR mode | |
| 701 | * and need a higher signal drive strength | |
| 702 | */ | |
| 703 | allwinner,drive = <3>; | |
| 704 | allwinner,pull = <0>; | |
| 705 | }; | |
| 412f2c6f MR |
706 | |
| 707 | spi1_pins_a: spi1@0 { | |
| 708 | allwinner,pins = "PI16", "PI17", "PI18", "PI19"; | |
| 709 | allwinner,function = "spi1"; | |
| 710 | allwinner,drive = <0>; | |
| 711 | allwinner,pull = <0>; | |
| 712 | }; | |
| 713 | ||
| 714 | spi2_pins_a: spi2@0 { | |
| 715 | allwinner,pins = "PC19", "PC20", "PC21", "PC22"; | |
| 716 | allwinner,function = "spi2"; | |
| 717 | allwinner,drive = <0>; | |
| 718 | allwinner,pull = <0>; | |
| 719 | }; | |
| 11fbedf4 HG |
720 | |
| 721 | mmc0_pins_a: mmc0@0 { | |
| 722 | allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; | |
| 723 | allwinner,function = "mmc0"; | |
| 724 | allwinner,drive = <2>; | |
| 725 | allwinner,pull = <0>; | |
| 726 | }; | |
| 727 | ||
| 728 | mmc0_cd_pin_reference_design: mmc0_cd_pin@0 { | |
| 729 | allwinner,pins = "PH1"; | |
| 730 | allwinner,function = "gpio_in"; | |
| 731 | allwinner,drive = <0>; | |
| 732 | allwinner,pull = <1>; | |
| 733 | }; | |
| 734 | ||
| 735 | mmc3_pins_a: mmc3@0 { | |
| 736 | allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9"; | |
| 737 | allwinner,function = "mmc3"; | |
| 738 | allwinner,drive = <2>; | |
| 739 | allwinner,pull = <0>; | |
| 740 | }; | |
| 17eac031 MR |
741 | }; |
| 742 | ||
| 4790ecfa | 743 | timer@01c20c00 { |
| b4f26440 | 744 | compatible = "allwinner,sun4i-a10-timer"; |
| 4790ecfa | 745 | reg = <0x01c20c00 0x90>; |
| 378d0aee MR |
746 | interrupts = <0 22 4>, |
| 747 | <0 23 4>, | |
| 748 | <0 24 4>, | |
| 749 | <0 25 4>, | |
| 750 | <0 67 4>, | |
| 751 | <0 68 4>; | |
| 4790ecfa MR |
752 | clocks = <&osc24M>; |
| 753 | }; | |
| 754 | ||
| 755 | wdt: watchdog@01c20c90 { | |
| ca5d04d9 | 756 | compatible = "allwinner,sun4i-a10-wdt"; |
| 4790ecfa MR |
757 | reg = <0x01c20c90 0x10>; |
| 758 | }; | |
| 759 | ||
| b5d905c7 CC |
760 | rtc: rtc@01c20d00 { |
| 761 | compatible = "allwinner,sun7i-a20-rtc"; | |
| 762 | reg = <0x01c20d00 0x20>; | |
| 2f418987 | 763 | interrupts = <0 24 4>; |
| b5d905c7 CC |
764 | }; |
| 765 | ||
| 8ec40c25 AB |
766 | pwm: pwm@01c20e00 { |
| 767 | compatible = "allwinner,sun7i-a20-pwm"; | |
| 768 | reg = <0x01c20e00 0xc>; | |
| 769 | clocks = <&osc24M>; | |
| 770 | #pwm-cells = <3>; | |
| 771 | status = "disabled"; | |
| 772 | }; | |
| 773 | ||
| 2bad969f OS |
774 | sid: eeprom@01c23800 { |
| 775 | compatible = "allwinner,sun7i-a20-sid"; | |
| 776 | reg = <0x01c23800 0x200>; | |
| 777 | }; | |
| 778 | ||
| 00f7ed8d | 779 | rtp: rtp@01c25000 { |
| 40dd8f3b | 780 | compatible = "allwinner,sun4i-a10-ts"; |
| 00f7ed8d HG |
781 | reg = <0x01c25000 0x100>; |
| 782 | interrupts = <0 29 4>; | |
| 783 | }; | |
| 784 | ||
| 4790ecfa MR |
785 | uart0: serial@01c28000 { |
| 786 | compatible = "snps,dw-apb-uart"; | |
| 787 | reg = <0x01c28000 0x400>; | |
| 378d0aee | 788 | interrupts = <0 1 4>; |
| 4790ecfa MR |
789 | reg-shift = <2>; |
| 790 | reg-io-width = <4>; | |
| de7dc935 | 791 | clocks = <&apb1_gates 16>; |
| 4790ecfa MR |
792 | status = "disabled"; |
| 793 | }; | |
| 794 | ||
| 795 | uart1: serial@01c28400 { | |
| 796 | compatible = "snps,dw-apb-uart"; | |
| 797 | reg = <0x01c28400 0x400>; | |
| 378d0aee | 798 | interrupts = <0 2 4>; |
| 4790ecfa MR |
799 | reg-shift = <2>; |
| 800 | reg-io-width = <4>; | |
| de7dc935 | 801 | clocks = <&apb1_gates 17>; |
| 4790ecfa MR |
802 | status = "disabled"; |
| 803 | }; | |
| 804 | ||
| 805 | uart2: serial@01c28800 { | |
| 806 | compatible = "snps,dw-apb-uart"; | |
| 807 | reg = <0x01c28800 0x400>; | |
| 378d0aee | 808 | interrupts = <0 3 4>; |
| 4790ecfa MR |
809 | reg-shift = <2>; |
| 810 | reg-io-width = <4>; | |
| de7dc935 | 811 | clocks = <&apb1_gates 18>; |
| 4790ecfa MR |
812 | status = "disabled"; |
| 813 | }; | |
| 814 | ||
| 815 | uart3: serial@01c28c00 { | |
| 816 | compatible = "snps,dw-apb-uart"; | |
| 817 | reg = <0x01c28c00 0x400>; | |
| 378d0aee | 818 | interrupts = <0 4 4>; |
| 4790ecfa MR |
819 | reg-shift = <2>; |
| 820 | reg-io-width = <4>; | |
| de7dc935 | 821 | clocks = <&apb1_gates 19>; |
| 4790ecfa MR |
822 | status = "disabled"; |
| 823 | }; | |
| 824 | ||
| 825 | uart4: serial@01c29000 { | |
| 826 | compatible = "snps,dw-apb-uart"; | |
| 827 | reg = <0x01c29000 0x400>; | |
| 378d0aee | 828 | interrupts = <0 17 4>; |
| 4790ecfa MR |
829 | reg-shift = <2>; |
| 830 | reg-io-width = <4>; | |
| de7dc935 | 831 | clocks = <&apb1_gates 20>; |
| 4790ecfa MR |
832 | status = "disabled"; |
| 833 | }; | |
| 834 | ||
| 835 | uart5: serial@01c29400 { | |
| 836 | compatible = "snps,dw-apb-uart"; | |
| 837 | reg = <0x01c29400 0x400>; | |
| 378d0aee | 838 | interrupts = <0 18 4>; |
| 4790ecfa MR |
839 | reg-shift = <2>; |
| 840 | reg-io-width = <4>; | |
| de7dc935 | 841 | clocks = <&apb1_gates 21>; |
| 4790ecfa MR |
842 | status = "disabled"; |
| 843 | }; | |
| 844 | ||
| 845 | uart6: serial@01c29800 { | |
| 846 | compatible = "snps,dw-apb-uart"; | |
| 847 | reg = <0x01c29800 0x400>; | |
| 378d0aee | 848 | interrupts = <0 19 4>; |
| 4790ecfa MR |
849 | reg-shift = <2>; |
| 850 | reg-io-width = <4>; | |
| de7dc935 | 851 | clocks = <&apb1_gates 22>; |
| 4790ecfa MR |
852 | status = "disabled"; |
| 853 | }; | |
| 854 | ||
| 855 | uart7: serial@01c29c00 { | |
| 856 | compatible = "snps,dw-apb-uart"; | |
| 857 | reg = <0x01c29c00 0x400>; | |
| 378d0aee | 858 | interrupts = <0 20 4>; |
| 4790ecfa MR |
859 | reg-shift = <2>; |
| 860 | reg-io-width = <4>; | |
| de7dc935 | 861 | clocks = <&apb1_gates 23>; |
| 4790ecfa MR |
862 | status = "disabled"; |
| 863 | }; | |
| 864 | ||
| 428abbb8 | 865 | i2c0: i2c@01c2ac00 { |
| d275545e | 866 | compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; |
| 428abbb8 | 867 | reg = <0x01c2ac00 0x400>; |
| 378d0aee | 868 | interrupts = <0 7 4>; |
| 428abbb8 MR |
869 | clocks = <&apb1_gates 0>; |
| 870 | clock-frequency = <100000>; | |
| 871 | status = "disabled"; | |
| d1412aed HG |
872 | #address-cells = <1>; |
| 873 | #size-cells = <0>; | |
| 428abbb8 MR |
874 | }; |
| 875 | ||
| 876 | i2c1: i2c@01c2b000 { | |
| d275545e | 877 | compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; |
| 428abbb8 | 878 | reg = <0x01c2b000 0x400>; |
| 378d0aee | 879 | interrupts = <0 8 4>; |
| 428abbb8 MR |
880 | clocks = <&apb1_gates 1>; |
| 881 | clock-frequency = <100000>; | |
| 882 | status = "disabled"; | |
| d1412aed HG |
883 | #address-cells = <1>; |
| 884 | #size-cells = <0>; | |
| 428abbb8 MR |
885 | }; |
| 886 | ||
| 887 | i2c2: i2c@01c2b400 { | |
| d275545e | 888 | compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; |
| 428abbb8 | 889 | reg = <0x01c2b400 0x400>; |
| 378d0aee | 890 | interrupts = <0 9 4>; |
| 428abbb8 MR |
891 | clocks = <&apb1_gates 2>; |
| 892 | clock-frequency = <100000>; | |
| 893 | status = "disabled"; | |
| d1412aed HG |
894 | #address-cells = <1>; |
| 895 | #size-cells = <0>; | |
| 428abbb8 MR |
896 | }; |
| 897 | ||
| 898 | i2c3: i2c@01c2b800 { | |
| d275545e | 899 | compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; |
| 428abbb8 | 900 | reg = <0x01c2b800 0x400>; |
| 378d0aee | 901 | interrupts = <0 88 4>; |
| 428abbb8 MR |
902 | clocks = <&apb1_gates 3>; |
| 903 | clock-frequency = <100000>; | |
| 904 | status = "disabled"; | |
| d1412aed HG |
905 | #address-cells = <1>; |
| 906 | #size-cells = <0>; | |
| 428abbb8 MR |
907 | }; |
| 908 | ||
| a3867045 | 909 | i2c4: i2c@01c2c000 { |
| d275545e | 910 | compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; |
| a3867045 | 911 | reg = <0x01c2c000 0x400>; |
| 378d0aee | 912 | interrupts = <0 89 4>; |
| 428abbb8 MR |
913 | clocks = <&apb1_gates 15>; |
| 914 | clock-frequency = <100000>; | |
| 915 | status = "disabled"; | |
| d1412aed HG |
916 | #address-cells = <1>; |
| 917 | #size-cells = <0>; | |
| 428abbb8 MR |
918 | }; |
| 919 | ||
| c40b8d58 CYT |
920 | gmac: ethernet@01c50000 { |
| 921 | compatible = "allwinner,sun7i-a20-gmac"; | |
| 922 | reg = <0x01c50000 0x10000>; | |
| 923 | interrupts = <0 85 4>; | |
| 924 | interrupt-names = "macirq"; | |
| 925 | clocks = <&ahb_gates 49>, <&gmac_tx_clk>; | |
| 926 | clock-names = "stmmaceth", "allwinner_gmac_tx"; | |
| 927 | snps,pbl = <2>; | |
| 928 | snps,fixed-burst; | |
| 929 | snps,force_sf_dma_mode; | |
| 930 | status = "disabled"; | |
| 931 | #address-cells = <1>; | |
| 932 | #size-cells = <0>; | |
| 933 | }; | |
| 934 | ||
| 31f8ad38 MR |
935 | hstimer@01c60000 { |
| 936 | compatible = "allwinner,sun7i-a20-hstimer"; | |
| 937 | reg = <0x01c60000 0x1000>; | |
| 2f418987 MR |
938 | interrupts = <0 81 4>, |
| 939 | <0 82 4>, | |
| 940 | <0 83 4>, | |
| 941 | <0 84 4>; | |
| 31f8ad38 MR |
942 | clocks = <&ahb_gates 28>; |
| 943 | }; | |
| 944 | ||
| 4790ecfa MR |
945 | gic: interrupt-controller@01c81000 { |
| 946 | compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; | |
| 947 | reg = <0x01c81000 0x1000>, | |
| 948 | <0x01c82000 0x1000>, | |
| 949 | <0x01c84000 0x2000>, | |
| 950 | <0x01c86000 0x2000>; | |
| 951 | interrupt-controller; | |
| 952 | #interrupt-cells = <3>; | |
| 953 | interrupts = <1 9 0xf04>; | |
| 954 | }; | |
| 955 | }; | |
| 956 | }; |