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ARM: dts: sun5i: Add rtp controller node
[deliverable/linux.git] / arch / arm / boot / dts / sun7i-a20.dtsi
CommitLineData
4790ecfa
MR		 1/*
2 * Copyright 2013 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "skeleton.dtsi"
15
16/ {
17 interrupt-parent = <&gic>;
18
e751cce9
EL		 19 aliases {
20 ethernet0 = &emac;
21 };
22
4790ecfa
MR		 23 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 cpu@0 {
28 compatible = "arm,cortex-a7";
29 device_type = "cpu";
30 reg = <0>;
31 };
32
33 cpu@1 {
34 compatible = "arm,cortex-a7";
35 device_type = "cpu";
36 reg = <1>;
37 };
38 };
39
40 memory {
41 reg = <0x40000000 0x80000000>;
42 };
43
44 clocks {
45 #address-cells = <1>;
46 #size-cells = <1>;
47 ranges;
48
49 osc24M: osc24M@01c20050 {
50 #clock-cells = <0>;
de7dc935
MR		 51 compatible = "allwinner,sun4i-osc-clk";
52 reg = <0x01c20050 0x4>;
4790ecfa
MR		 53 clock-frequency = <24000000>;
54 };
55
56 osc32k: osc32k {
57 #clock-cells = <0>;
58 compatible = "fixed-clock";
59 clock-frequency = <32768>;
60 };
de7dc935
MR		 61
62 pll1: pll1@01c20000 {
63 #clock-cells = <0>;
64 compatible = "allwinner,sun4i-pll1-clk";
65 reg = <0x01c20000 0x4>;
66 clocks = <&osc24M>;
67 };
68
ec5589f7 69 pll4: pll4@01c20018 {
de7dc935 70 #clock-cells = <0>;
ec5589f7
EL		 71 compatible = "allwinner,sun4i-pll1-clk";
72 reg = <0x01c20018 0x4>;
73 clocks = <&osc24M>;
74 };
75
c3e5e66b
EL		 76 pll5: pll5@01c20020 {
77 #clock-cells = <1>;
78 compatible = "allwinner,sun4i-pll5-clk";
79 reg = <0x01c20020 0x4>;
80 clocks = <&osc24M>;
81 clock-output-names = "pll5_ddr", "pll5_other";
82 };
83
84 pll6: pll6@01c20028 {
85 #clock-cells = <1>;
86 compatible = "allwinner,sun4i-pll6-clk";
87 reg = <0x01c20028 0x4>;
88 clocks = <&osc24M>;
89 clock-output-names = "pll6_sata", "pll6_other", "pll6";
de7dc935
MR		 90 };
91
92 cpu: cpu@01c20054 {
93 #clock-cells = <0>;
94 compatible = "allwinner,sun4i-cpu-clk";
95 reg = <0x01c20054 0x4>;
c3e5e66b 96 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
de7dc935
MR		 97 };
98
99 axi: axi@01c20054 {
100 #clock-cells = <0>;
101 compatible = "allwinner,sun4i-axi-clk";
102 reg = <0x01c20054 0x4>;
103 clocks = <&cpu>;
104 };
105
106 ahb: ahb@01c20054 {
107 #clock-cells = <0>;
108 compatible = "allwinner,sun4i-ahb-clk";
109 reg = <0x01c20054 0x4>;
110 clocks = <&axi>;
111 };
112
113 ahb_gates: ahb_gates@01c20060 {
114 #clock-cells = <1>;
115 compatible = "allwinner,sun7i-a20-ahb-gates-clk";
116 reg = <0x01c20060 0x8>;
117 clocks = <&ahb>;
118 clock-output-names = "ahb_usb0", "ahb_ehci0",
119 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
120 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
121 "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
122 "ahb_nand", "ahb_sdram", "ahb_ace",
123 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
124 "ahb_spi2", "ahb_spi3", "ahb_sata",
125 "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
126 "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
127 "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
128 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
129 "ahb_de_fe1", "ahb_gmac", "ahb_mp",
130 "ahb_mali";
131 };
132
133 apb0: apb0@01c20054 {
134 #clock-cells = <0>;
135 compatible = "allwinner,sun4i-apb0-clk";
136 reg = <0x01c20054 0x4>;
137 clocks = <&ahb>;
138 };
139
140 apb0_gates: apb0_gates@01c20068 {
141 #clock-cells = <1>;
142 compatible = "allwinner,sun7i-a20-apb0-gates-clk";
143 reg = <0x01c20068 0x4>;
144 clocks = <&apb0>;
145 clock-output-names = "apb0_codec", "apb0_spdif",
146 "apb0_ac97", "apb0_iis0", "apb0_iis1",
147 "apb0_pio", "apb0_ir0", "apb0_ir1",
148 "apb0_iis2", "apb0_keypad";
149 };
150
151 apb1_mux: apb1_mux@01c20058 {
152 #clock-cells = <0>;
153 compatible = "allwinner,sun4i-apb1-mux-clk";
154 reg = <0x01c20058 0x4>;
c3e5e66b 155 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
de7dc935
MR		 156 };
157
158 apb1: apb1@01c20058 {
159 #clock-cells = <0>;
160 compatible = "allwinner,sun4i-apb1-clk";
161 reg = <0x01c20058 0x4>;
162 clocks = <&apb1_mux>;
163 };
164
165 apb1_gates: apb1_gates@01c2006c {
166 #clock-cells = <1>;
167 compatible = "allwinner,sun7i-a20-apb1-gates-clk";
168 reg = <0x01c2006c 0x4>;
169 clocks = <&apb1>;
170 clock-output-names = "apb1_i2c0", "apb1_i2c1",
171 "apb1_i2c2", "apb1_i2c3", "apb1_can",
172 "apb1_scr", "apb1_ps20", "apb1_ps21",
173 "apb1_i2c4", "apb1_uart0", "apb1_uart1",
174 "apb1_uart2", "apb1_uart3", "apb1_uart4",
175 "apb1_uart5", "apb1_uart6", "apb1_uart7";
176 };
1c92b95b
EL		 177
178 nand_clk: clk@01c20080 {
179 #clock-cells = <0>;
180 compatible = "allwinner,sun4i-mod0-clk";
181 reg = <0x01c20080 0x4>;
182 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
183 clock-output-names = "nand";
184 };
185
186 ms_clk: clk@01c20084 {
187 #clock-cells = <0>;
188 compatible = "allwinner,sun4i-mod0-clk";
189 reg = <0x01c20084 0x4>;
190 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
191 clock-output-names = "ms";
192 };
193
194 mmc0_clk: clk@01c20088 {
195 #clock-cells = <0>;
196 compatible = "allwinner,sun4i-mod0-clk";
197 reg = <0x01c20088 0x4>;
198 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
199 clock-output-names = "mmc0";
200 };
201
202 mmc1_clk: clk@01c2008c {
203 #clock-cells = <0>;
204 compatible = "allwinner,sun4i-mod0-clk";
205 reg = <0x01c2008c 0x4>;
206 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
207 clock-output-names = "mmc1";
208 };
209
210 mmc2_clk: clk@01c20090 {
211 #clock-cells = <0>;
212 compatible = "allwinner,sun4i-mod0-clk";
213 reg = <0x01c20090 0x4>;
214 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
215 clock-output-names = "mmc2";
216 };
217
218 mmc3_clk: clk@01c20094 {
219 #clock-cells = <0>;
220 compatible = "allwinner,sun4i-mod0-clk";
221 reg = <0x01c20094 0x4>;
222 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
223 clock-output-names = "mmc3";
224 };
225
226 ts_clk: clk@01c20098 {
227 #clock-cells = <0>;
228 compatible = "allwinner,sun4i-mod0-clk";
229 reg = <0x01c20098 0x4>;
230 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
231 clock-output-names = "ts";
232 };
233
234 ss_clk: clk@01c2009c {
235 #clock-cells = <0>;
236 compatible = "allwinner,sun4i-mod0-clk";
237 reg = <0x01c2009c 0x4>;
238 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
239 clock-output-names = "ss";
240 };
241
242 spi0_clk: clk@01c200a0 {
243 #clock-cells = <0>;
244 compatible = "allwinner,sun4i-mod0-clk";
245 reg = <0x01c200a0 0x4>;
246 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
247 clock-output-names = "spi0";
248 };
249
250 spi1_clk: clk@01c200a4 {
251 #clock-cells = <0>;
252 compatible = "allwinner,sun4i-mod0-clk";
253 reg = <0x01c200a4 0x4>;
254 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
255 clock-output-names = "spi1";
256 };
257
258 spi2_clk: clk@01c200a8 {
259 #clock-cells = <0>;
260 compatible = "allwinner,sun4i-mod0-clk";
261 reg = <0x01c200a8 0x4>;
262 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
263 clock-output-names = "spi2";
264 };
265
266 pata_clk: clk@01c200ac {
267 #clock-cells = <0>;
268 compatible = "allwinner,sun4i-mod0-clk";
269 reg = <0x01c200ac 0x4>;
270 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
271 clock-output-names = "pata";
272 };
273
274 ir0_clk: clk@01c200b0 {
275 #clock-cells = <0>;
276 compatible = "allwinner,sun4i-mod0-clk";
277 reg = <0x01c200b0 0x4>;
278 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
279 clock-output-names = "ir0";
280 };
281
282 ir1_clk: clk@01c200b4 {
283 #clock-cells = <0>;
284 compatible = "allwinner,sun4i-mod0-clk";
285 reg = <0x01c200b4 0x4>;
286 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
287 clock-output-names = "ir1";
288 };
289
290 spi3_clk: clk@01c200d4 {
291 #clock-cells = <0>;
292 compatible = "allwinner,sun4i-mod0-clk";
293 reg = <0x01c200d4 0x4>;
294 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
295 clock-output-names = "spi3";
296 };
118c07ae
EL		 297
298 mbus_clk: clk@01c2015c {
299 #clock-cells = <0>;
300 compatible = "allwinner,sun4i-mod0-clk";
301 reg = <0x01c2015c 0x4>;
302 clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
303 clock-output-names = "mbus";
304 };
4790ecfa
MR		 305 };
306
307 soc@01c00000 {
308 compatible = "simple-bus";
309 #address-cells = <1>;
310 #size-cells = <1>;
311 ranges;
312
2e804d03
MR		 313 emac: ethernet@01c0b000 {
314 compatible = "allwinner,sun4i-emac";
315 reg = <0x01c0b000 0x1000>;
316 interrupts = <0 55 1>;
317 clocks = <&ahb_gates 17>;
318 status = "disabled";
319 };
320
321 mdio@01c0b080 {
322 compatible = "allwinner,sun4i-mdio";
323 reg = <0x01c0b080 0x14>;
324 status = "disabled";
325 #address-cells = <1>;
326 #size-cells = <0>;
327 };
328
17eac031
MR		 329 pio: pinctrl@01c20800 {
330 compatible = "allwinner,sun7i-a20-pinctrl";
331 reg = <0x01c20800 0x400>;
332 interrupts = <0 28 1>;
de7dc935 333 clocks = <&apb0_gates 5>;
17eac031
MR		 334 gpio-controller;
335 interrupt-controller;
336 #address-cells = <1>;
337 #size-cells = <0>;
338 #gpio-cells = <3>;
9f229ba9
MR		 339
340 uart0_pins_a: uart0@0 {
341 allwinner,pins = "PB22", "PB23";
342 allwinner,function = "uart0";
343 allwinner,drive = <0>;
344 allwinner,pull = <0>;
345 };
346
347 uart6_pins_a: uart6@0 {
348 allwinner,pins = "PI12", "PI13";
349 allwinner,function = "uart6";
350 allwinner,drive = <0>;
351 allwinner,pull = <0>;
352 };
353
354 uart7_pins_a: uart7@0 {
355 allwinner,pins = "PI20", "PI21";
356 allwinner,function = "uart7";
357 allwinner,drive = <0>;
358 allwinner,pull = <0>;
359 };
756084c5 360
e5496a31
MR		 361 i2c0_pins_a: i2c0@0 {
362 allwinner,pins = "PB0", "PB1";
363 allwinner,function = "i2c0";
364 allwinner,drive = <0>;
365 allwinner,pull = <0>;
366 };
367
368 i2c1_pins_a: i2c1@0 {
369 allwinner,pins = "PB18", "PB19";
370 allwinner,function = "i2c1";
371 allwinner,drive = <0>;
372 allwinner,pull = <0>;
373 };
374
375 i2c2_pins_a: i2c2@0 {
376 allwinner,pins = "PB20", "PB21";
377 allwinner,function = "i2c2";
378 allwinner,drive = <0>;
379 allwinner,pull = <0>;
380 };
381
756084c5
MR		 382 emac_pins_a: emac0@0 {
383 allwinner,pins = "PA0", "PA1", "PA2",
384 "PA3", "PA4", "PA5", "PA6",
385 "PA7", "PA8", "PA9", "PA10",
386 "PA11", "PA12", "PA13", "PA14",
387 "PA15", "PA16";
388 allwinner,function = "emac";
389 allwinner,drive = <0>;
390 allwinner,pull = <0>;
391 };
17eac031
MR		 392 };
393
4790ecfa
MR		 394 timer@01c20c00 {
395 compatible = "allwinner,sun4i-timer";
396 reg = <0x01c20c00 0x90>;
397 interrupts = <0 22 1>,
398 <0 23 1>,
399 <0 24 1>,
400 <0 25 1>,
401 <0 67 1>,
402 <0 68 1>;
403 clocks = <&osc24M>;
404 };
405
406 wdt: watchdog@01c20c90 {
407 compatible = "allwinner,sun4i-wdt";
408 reg = <0x01c20c90 0x10>;
409 };
410
b5d905c7
CC		 411 rtc: rtc@01c20d00 {
412 compatible = "allwinner,sun7i-a20-rtc";
413 reg = <0x01c20d00 0x20>;
414 interrupts = <0 24 1>;
415 };
416
2bad969f
OS		 417 sid: eeprom@01c23800 {
418 compatible = "allwinner,sun7i-a20-sid";
419 reg = <0x01c23800 0x200>;
420 };
421
4790ecfa
MR		 422 uart0: serial@01c28000 {
423 compatible = "snps,dw-apb-uart";
424 reg = <0x01c28000 0x400>;
425 interrupts = <0 1 1>;
426 reg-shift = <2>;
427 reg-io-width = <4>;
de7dc935 428 clocks = <&apb1_gates 16>;
4790ecfa
MR		 429 status = "disabled";
430 };
431
432 uart1: serial@01c28400 {
433 compatible = "snps,dw-apb-uart";
434 reg = <0x01c28400 0x400>;
435 interrupts = <0 2 1>;
436 reg-shift = <2>;
437 reg-io-width = <4>;
de7dc935 438 clocks = <&apb1_gates 17>;
4790ecfa
MR		 439 status = "disabled";
440 };
441
442 uart2: serial@01c28800 {
443 compatible = "snps,dw-apb-uart";
444 reg = <0x01c28800 0x400>;
445 interrupts = <0 3 1>;
446 reg-shift = <2>;
447 reg-io-width = <4>;
de7dc935 448 clocks = <&apb1_gates 18>;
4790ecfa
MR		 449 status = "disabled";
450 };
451
452 uart3: serial@01c28c00 {
453 compatible = "snps,dw-apb-uart";
454 reg = <0x01c28c00 0x400>;
455 interrupts = <0 4 1>;
456 reg-shift = <2>;
457 reg-io-width = <4>;
de7dc935 458 clocks = <&apb1_gates 19>;
4790ecfa
MR		 459 status = "disabled";
460 };
461
462 uart4: serial@01c29000 {
463 compatible = "snps,dw-apb-uart";
464 reg = <0x01c29000 0x400>;
465 interrupts = <0 17 1>;
466 reg-shift = <2>;
467 reg-io-width = <4>;
de7dc935 468 clocks = <&apb1_gates 20>;
4790ecfa
MR		 469 status = "disabled";
470 };
471
472 uart5: serial@01c29400 {
473 compatible = "snps,dw-apb-uart";
474 reg = <0x01c29400 0x400>;
475 interrupts = <0 18 1>;
476 reg-shift = <2>;
477 reg-io-width = <4>;
de7dc935 478 clocks = <&apb1_gates 21>;
4790ecfa
MR		 479 status = "disabled";
480 };
481
482 uart6: serial@01c29800 {
483 compatible = "snps,dw-apb-uart";
484 reg = <0x01c29800 0x400>;
485 interrupts = <0 19 1>;
486 reg-shift = <2>;
487 reg-io-width = <4>;
de7dc935 488 clocks = <&apb1_gates 22>;
4790ecfa
MR		 489 status = "disabled";
490 };
491
492 uart7: serial@01c29c00 {
493 compatible = "snps,dw-apb-uart";
494 reg = <0x01c29c00 0x400>;
495 interrupts = <0 20 1>;
496 reg-shift = <2>;
497 reg-io-width = <4>;
de7dc935 498 clocks = <&apb1_gates 23>;
4790ecfa
MR		 499 status = "disabled";
500 };
501
428abbb8
MR		 502 i2c0: i2c@01c2ac00 {
503 compatible = "allwinner,sun4i-i2c";
504 reg = <0x01c2ac00 0x400>;
505 interrupts = <0 7 1>;
506 clocks = <&apb1_gates 0>;
507 clock-frequency = <100000>;
508 status = "disabled";
509 };
510
511 i2c1: i2c@01c2b000 {
512 compatible = "allwinner,sun4i-i2c";
513 reg = <0x01c2b000 0x400>;
514 interrupts = <0 8 1>;
515 clocks = <&apb1_gates 1>;
516 clock-frequency = <100000>;
517 status = "disabled";
518 };
519
520 i2c2: i2c@01c2b400 {
521 compatible = "allwinner,sun4i-i2c";
522 reg = <0x01c2b400 0x400>;
523 interrupts = <0 9 1>;
524 clocks = <&apb1_gates 2>;
525 clock-frequency = <100000>;
526 status = "disabled";
527 };
528
529 i2c3: i2c@01c2b800 {
530 compatible = "allwinner,sun4i-i2c";
531 reg = <0x01c2b800 0x400>;
532 interrupts = <0 88 1>;
533 clocks = <&apb1_gates 3>;
534 clock-frequency = <100000>;
535 status = "disabled";
536 };
537
538 i2c4: i2c@01c2bc00 {
539 compatible = "allwinner,sun4i-i2c";
540 reg = <0x01c2bc00 0x400>;
541 interrupts = <0 89 1>;
542 clocks = <&apb1_gates 15>;
543 clock-frequency = <100000>;
544 status = "disabled";
545 };
546
4790ecfa
MR		 547 gic: interrupt-controller@01c81000 {
548 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
549 reg = <0x01c81000 0x1000>,
550 <0x01c82000 0x1000>,
551 <0x01c84000 0x2000>,
552 <0x01c86000 0x2000>;
553 interrupt-controller;
554 #interrupt-cells = <3>;
555 interrupts = <1 9 0xf04>;
556 };
557 };
558};
Linux kernel - Deliverables
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