[deliverable/linux.git] / arch / arm / boot / dts / sun8i-a23-a33.dtsi

/*
 * Copyright 2014 Chen-Yu Tsai
 *
 * Chen-Yu Tsai <wens@csie.org>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include "skeleton.dtsi"

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/pinctrl/sun4i-a10.h>

/ {
	interrupt-parent = <&gic>;

	chosen {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		framebuffer@0 {
			compatible = "allwinner,simple-framebuffer",
				     "simple-framebuffer";
			allwinner,pipeline = "de_be0-lcd0";
			clocks = <&pll6 0>;
			status = "disabled";
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <24000000>;
		arm,cpu-registers-not-fw-configured;
	};

	cpus {
		enable-method = "allwinner,sun8i-a23";
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0>;
		};

		cpu@1 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <1>;
		};
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		osc24M: osc24M_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <24000000>;
			clock-output-names = "osc24M";
		};

		osc32k: osc32k_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32768>;
			clock-output-names = "osc32k";
		};

		pll1: clk@01c20000 {
			#clock-cells = <0>;
			compatible = "allwinner,sun8i-a23-pll1-clk";
			reg = <0x01c20000 0x4>;
			clocks = <&osc24M>;
			clock-output-names = "pll1";
		};

		/* dummy clock until actually implemented */
		pll5: pll5_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <0>;
			clock-output-names = "pll5";
		};

		pll6: clk@01c20028 {
			#clock-cells = <1>;
			compatible = "allwinner,sun6i-a31-pll6-clk";
			reg = <0x01c20028 0x4>;
			clocks = <&osc24M>;
			clock-output-names = "pll6", "pll6x2";
		};

		cpu: cpu_clk@01c20050 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-cpu-clk";
			reg = <0x01c20050 0x4>;

			/*
			 * PLL1 is listed twice here.
			 * While it looks suspicious, it's actually documented
			 * that way both in the datasheet and in the code from
			 * Allwinner.
			 */
			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
			clock-output-names = "cpu";
		};

		axi: axi_clk@01c20050 {
			#clock-cells = <0>;
			compatible = "allwinner,sun8i-a23-axi-clk";
			reg = <0x01c20050 0x4>;
			clocks = <&cpu>;
			clock-output-names = "axi";
		};

		ahb1: ahb1_clk@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun6i-a31-ahb1-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
			clock-output-names = "ahb1";
		};

		apb1: apb1_clk@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-apb0-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&ahb1>;
			clock-output-names = "apb1";
		};

		ahb1_gates: clk@01c20060 {
			#clock-cells = <1>;
			compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
			reg = <0x01c20060 0x8>;
			clocks = <&ahb1>;
			clock-indices = <1>, <6>,
					<8>, <9>, <10>,
					<13>, <14>,
					<19>, <20>,
					<21>, <24>, <26>,
					<29>, <32>, <36>,
					<40>, <44>, <46>,
					<52>, <54>,
					<57>;
			clock-output-names = "ahb1_mipidsi", "ahb1_dma",
					"ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
					"ahb1_nand", "ahb1_sdram",
					"ahb1_hstimer", "ahb1_spi0",
					"ahb1_spi1", "ahb1_otg", "ahb1_ehci",
					"ahb1_ohci", "ahb1_ve", "ahb1_lcd",
					"ahb1_csi", "ahb1_be",	"ahb1_fe",
					"ahb1_gpu", "ahb1_spinlock",
					"ahb1_drc";
		};

		apb1_gates: clk@01c20068 {
			#clock-cells = <1>;
			compatible = "allwinner,sun8i-a23-apb1-gates-clk";
			reg = <0x01c20068 0x4>;
			clocks = <&apb1>;
			clock-indices = <0>, <5>,
					<12>, <13>;
			clock-output-names = "apb1_codec", "apb1_pio",
					"apb1_daudio0",	"apb1_daudio1";
		};

		apb2: clk@01c20058 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-apb1-clk";
			reg = <0x01c20058 0x4>;
			clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
			clock-output-names = "apb2";
		};

		apb2_gates: clk@01c2006c {
			#clock-cells = <1>;
			compatible = "allwinner,sun8i-a23-apb2-gates-clk";
			reg = <0x01c2006c 0x4>;
			clocks = <&apb2>;
			clock-indices = <0>, <1>,
					<2>, <16>,
					<17>, <18>,
					<19>, <20>;
			clock-output-names = "apb2_i2c0", "apb2_i2c1",
					"apb2_i2c2", "apb2_uart0",
					"apb2_uart1", "apb2_uart2",
					"apb2_uart3", "apb2_uart4";
		};

		mmc0_clk: clk@01c20088 {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-mmc-clk";
			reg = <0x01c20088 0x4>;
			clocks = <&osc24M>, <&pll6 0>;
			clock-output-names = "mmc0",
					     "mmc0_output",
					     "mmc0_sample";
		};

		mmc1_clk: clk@01c2008c {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-mmc-clk";
			reg = <0x01c2008c 0x4>;
			clocks = <&osc24M>, <&pll6 0>;
			clock-output-names = "mmc1",
					     "mmc1_output",
					     "mmc1_sample";
		};

		mmc2_clk: clk@01c20090 {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-mmc-clk";
			reg = <0x01c20090 0x4>;
			clocks = <&osc24M>, <&pll6 0>;
			clock-output-names = "mmc2",
					     "mmc2_output",
					     "mmc2_sample";
		};

		usb_clk: clk@01c200cc {
			#clock-cells = <1>;
			#reset-cells = <1>;
			compatible = "allwinner,sun8i-a23-usb-clk";
			reg = <0x01c200cc 0x4>;
			clocks = <&osc24M>;
			clock-output-names = "usb_phy0", "usb_phy1", "usb_hsic",
					     "usb_hsic_12M", "usb_ohci0";
		};
	};

	soc@01c00000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		dma: dma-controller@01c02000 {
			compatible = "allwinner,sun8i-a23-dma";
			reg = <0x01c02000 0x1000>;
			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ahb1_gates 6>;
			resets = <&ahb1_rst 6>;
			#dma-cells = <1>;
		};

		mmc0: mmc@01c0f000 {
			compatible = "allwinner,sun5i-a13-mmc";
			reg = <0x01c0f000 0x1000>;
			clocks = <&ahb1_gates 8>,
				 <&mmc0_clk 0>,
				 <&mmc0_clk 1>,
				 <&mmc0_clk 2>;
			clock-names = "ahb",
				      "mmc",
				      "output",
				      "sample";
			resets = <&ahb1_rst 8>;
			reset-names = "ahb";
			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		mmc1: mmc@01c10000 {
			compatible = "allwinner,sun5i-a13-mmc";
			reg = <0x01c10000 0x1000>;
			clocks = <&ahb1_gates 9>,
				 <&mmc1_clk 0>,
				 <&mmc1_clk 1>,
				 <&mmc1_clk 2>;
			clock-names = "ahb",
				      "mmc",
				      "output",
				      "sample";
			resets = <&ahb1_rst 9>;
			reset-names = "ahb";
			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		mmc2: mmc@01c11000 {
			compatible = "allwinner,sun5i-a13-mmc";
			reg = <0x01c11000 0x1000>;
			clocks = <&ahb1_gates 10>,
				 <&mmc2_clk 0>,
				 <&mmc2_clk 1>,
				 <&mmc2_clk 2>;
			clock-names = "ahb",
				      "mmc",
				      "output",
				      "sample";
			resets = <&ahb1_rst 10>;
			reset-names = "ahb";
			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		pio: pinctrl@01c20800 {
			/* compatible gets set in SoC specific dtsi file */
			reg = <0x01c20800 0x400>;
			/* interrupts get set in SoC specific dtsi file */
			clocks = <&apb1_gates 5>;
			gpio-controller;
			interrupt-controller;
			#address-cells = <1>;
			#size-cells = <0>;
			#gpio-cells = <3>;

			uart0_pins_a: uart0@0 {
				allwinner,pins = "PF2", "PF4";
				allwinner,function = "uart0";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			mmc0_pins_a: mmc0@0 {
				allwinner,pins = "PF0", "PF1", "PF2",
						 "PF3", "PF4", "PF5";
				allwinner,function = "mmc0";
				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			mmc1_pins_a: mmc1@0 {
				allwinner,pins = "PG0", "PG1", "PG2",
						 "PG3", "PG4", "PG5";
				allwinner,function = "mmc1";
				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			mmc2_8bit_pins: mmc2_8bit {
				allwinner,pins = "PC5", "PC6", "PC8",
						 "PC9", "PC10", "PC11",
						 "PC12", "PC13", "PC14",
						 "PC15";
				allwinner,function = "mmc2";
				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			i2c0_pins_a: i2c0@0 {
				allwinner,pins = "PH2", "PH3";
				allwinner,function = "i2c0";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			i2c1_pins_a: i2c1@0 {
				allwinner,pins = "PH4", "PH5";
				allwinner,function = "i2c1";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			i2c2_pins_a: i2c2@0 {
				allwinner,pins = "PE12", "PE13";
				allwinner,function = "i2c2";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};
		};

		ahb1_rst: reset@01c202c0 {
			#reset-cells = <1>;
			compatible = "allwinner,sun6i-a31-clock-reset";
			reg = <0x01c202c0 0xc>;
		};

		apb1_rst: reset@01c202d0 {
			#reset-cells = <1>;
			compatible = "allwinner,sun6i-a31-clock-reset";
			reg = <0x01c202d0 0x4>;
		};

		apb2_rst: reset@01c202d8 {
			#reset-cells = <1>;
			compatible = "allwinner,sun6i-a31-clock-reset";
			reg = <0x01c202d8 0x4>;
		};

		timer@01c20c00 {
			compatible = "allwinner,sun4i-a10-timer";
			reg = <0x01c20c00 0xa0>;
			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&osc24M>;
		};

		wdt0: watchdog@01c20ca0 {
			compatible = "allwinner,sun6i-a31-wdt";
			reg = <0x01c20ca0 0x20>;
			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
		};

		lradc: lradc@01c22800 {
			compatible = "allwinner,sun4i-a10-lradc-keys";
			reg = <0x01c22800 0x100>;
			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		uart0: serial@01c28000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28000 0x400>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb2_gates 16>;
			resets = <&apb2_rst 16>;
			dmas = <&dma 6>, <&dma 6>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		uart1: serial@01c28400 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28400 0x400>;
			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb2_gates 17>;
			resets = <&apb2_rst 17>;
			dmas = <&dma 7>, <&dma 7>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		uart2: serial@01c28800 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28800 0x400>;
			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb2_gates 18>;
			resets = <&apb2_rst 18>;
			dmas = <&dma 8>, <&dma 8>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		uart3: serial@01c28c00 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28c00 0x400>;
			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb2_gates 19>;
			resets = <&apb2_rst 19>;
			dmas = <&dma 9>, <&dma 9>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		uart4: serial@01c29000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29000 0x400>;
			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb2_gates 20>;
			resets = <&apb2_rst 20>;
			dmas = <&dma 10>, <&dma 10>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		i2c0: i2c@01c2ac00 {
			compatible = "allwinner,sun6i-a31-i2c";
			reg = <0x01c2ac00 0x400>;
			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&apb2_gates 0>;
			resets = <&apb2_rst 0>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c1: i2c@01c2b000 {
			compatible = "allwinner,sun6i-a31-i2c";
			reg = <0x01c2b000 0x400>;
			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&apb2_gates 1>;
			resets = <&apb2_rst 1>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c2: i2c@01c2b400 {
			compatible = "allwinner,sun6i-a31-i2c";
			reg = <0x01c2b400 0x400>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&apb2_gates 2>;
			resets = <&apb2_rst 2>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		gic: interrupt-controller@01c81000 {
			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
			reg = <0x01c81000 0x1000>,
			      <0x01c82000 0x1000>,
			      <0x01c84000 0x2000>,
			      <0x01c86000 0x2000>;
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
		};

		rtc: rtc@01f00000 {
			compatible = "allwinner,sun6i-a31-rtc";
			reg = <0x01f00000 0x54>;
			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
		};

		prcm@01f01400 {
			compatible = "allwinner,sun8i-a23-prcm";
			reg = <0x01f01400 0x200>;

			ar100: ar100_clk {
				compatible = "fixed-factor-clock";
				#clock-cells = <0>;
				clock-div = <1>;
				clock-mult = <1>;
				clocks = <&osc24M>;
				clock-output-names = "ar100";
			};

			ahb0: ahb0_clk {
				compatible = "fixed-factor-clock";
				#clock-cells = <0>;
				clock-div = <1>;
				clock-mult = <1>;
				clocks = <&ar100>;
				clock-output-names = "ahb0";
			};

			apb0: apb0_clk {
				compatible = "allwinner,sun8i-a23-apb0-clk";
				#clock-cells = <0>;
				clocks = <&ahb0>;
				clock-output-names = "apb0";
			};

			apb0_gates: apb0_gates_clk {
				compatible = "allwinner,sun8i-a23-apb0-gates-clk";
				#clock-cells = <1>;
				clocks = <&apb0>;
				clock-output-names = "apb0_pio", "apb0_timer",
						"apb0_rsb", "apb0_uart",
						"apb0_i2c";
			};

			apb0_rst: apb0_rst {
				compatible = "allwinner,sun6i-a31-clock-reset";
				#reset-cells = <1>;
			};
		};

		cpucfg@01f01c00 {
			compatible = "allwinner,sun8i-a23-cpuconfig";
			reg = <0x01f01c00 0x300>;
		};

		r_uart: serial@01f02800 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01f02800 0x400>;
			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb0_gates 4>;
			resets = <&apb0_rst 4>;
			status = "disabled";
		};

		r_pio: pinctrl@01f02c00 {
			compatible = "allwinner,sun8i-a23-r-pinctrl";
			reg = <0x01f02c00 0x400>;
			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&apb0_gates 0>;
			resets = <&apb0_rst 0>;
			gpio-controller;
			interrupt-controller;
			#address-cells = <1>;
			#size-cells = <0>;
			#gpio-cells = <3>;

			r_uart_pins_a: r_uart@0 {
				allwinner,pins = "PL2", "PL3";
				allwinner,function = "s_uart";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};
		};
	};
};
Commit	Line	Data
a0e9e9be VP	1	/*
	2	* Copyright 2014 Chen-Yu Tsai
	3	*
	4	* Chen-Yu Tsai <wens@csie.org>
	5	*
	6	* This file is dual-licensed: you can use it either under the terms
	7	* of the GPL or the X11 license, at your option. Note that this dual
	8	* licensing only applies to this file, and not this project as a
	9	* whole.
	10	*
	11	* a) This file is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of the
	14	* License, or (at your option) any later version.
	15	*
	16	* This file is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* Or, alternatively,
	22	*
	23	* b) Permission is hereby granted, free of charge, to any person
	24	* obtaining a copy of this software and associated documentation
	25	* files (the "Software"), to deal in the Software without
	26	* restriction, including without limitation the rights to use,
	27	* copy, modify, merge, publish, distribute, sublicense, and/or
	28	* sell copies of the Software, and to permit persons to whom the
	29	* Software is furnished to do so, subject to the following
	30	* conditions:
	31	*
	32	* The above copyright notice and this permission notice shall be
	33	* included in all copies or substantial portions of the Software.
	34	*
	35	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	36	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	37	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	38	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	39	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	40	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	41	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	42	* OTHER DEALINGS IN THE SOFTWARE.
	43	*/
	44
	45	#include "skeleton.dtsi"
	46
	47	#include <dt-bindings/interrupt-controller/arm-gic.h>
	48
	49	#include <dt-bindings/pinctrl/sun4i-a10.h>
	50
	51	/ {
	52	interrupt-parent = <&gic>;
	53
	54	chosen {
	55	#address-cells = <1>;
	56	#size-cells = <1>;
	57	ranges;
	58
	59	framebuffer@0 {
	60	compatible = "allwinner,simple-framebuffer",
	61	"simple-framebuffer";
	62	allwinner,pipeline = "de_be0-lcd0";
	63	clocks = <&pll6 0>;
	64	status = "disabled";
65	};
66	};
67
68	timer {
69	compatible = "arm,armv7-timer";
70	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
71	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
72	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
73	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
74	clock-frequency = <24000000>;
75	arm,cpu-registers-not-fw-configured;
76	};
77
78	cpus {
79	enable-method = "allwinner,sun8i-a23";
80	#address-cells = <1>;
81	#size-cells = <0>;
82
83	cpu@0 {
84	compatible = "arm,cortex-a7";
85	device_type = "cpu";
86	reg = <0>;
87	};
88
89	cpu@1 {
90	compatible = "arm,cortex-a7";
91	device_type = "cpu";
92	reg = <1>;
93	};
94	};
95
96	clocks {
97	#address-cells = <1>;
98	#size-cells = <1>;
99	ranges;
100
101	osc24M: osc24M_clk {
102	#clock-cells = <0>;
103	compatible = "fixed-clock";
104	clock-frequency = <24000000>;
105	clock-output-names = "osc24M";
106	};
107
108	osc32k: osc32k_clk {
109	#clock-cells = <0>;
110	compatible = "fixed-clock";
111	clock-frequency = <32768>;
112	clock-output-names = "osc32k";
113	};
114
115	pll1: clk@01c20000 {
116	#clock-cells = <0>;
117	compatible = "allwinner,sun8i-a23-pll1-clk";
118	reg = <0x01c20000 0x4>;
119	clocks = <&osc24M>;
120	clock-output-names = "pll1";
121	};
122
123	/* dummy clock until actually implemented */
124	pll5: pll5_clk {
125	#clock-cells = <0>;
126	compatible = "fixed-clock";
127	clock-frequency = <0>;
128	clock-output-names = "pll5";
129	};
130
131	pll6: clk@01c20028 {
132	#clock-cells = <1>;
133	compatible = "allwinner,sun6i-a31-pll6-clk";
134	reg = <0x01c20028 0x4>;
135	clocks = <&osc24M>;
136	clock-output-names = "pll6", "pll6x2";
137	};
138
139	cpu: cpu_clk@01c20050 {
140	#clock-cells = <0>;
141	compatible = "allwinner,sun4i-a10-cpu-clk";
142	reg = <0x01c20050 0x4>;
143
144	/*
145	* PLL1 is listed twice here.
146	* While it looks suspicious, it's actually documented
147	* that way both in the datasheet and in the code from
148	* Allwinner.
149	*/
150	clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
151	clock-output-names = "cpu";
152	};
153
154	axi: axi_clk@01c20050 {
155	#clock-cells = <0>;
156	compatible = "allwinner,sun8i-a23-axi-clk";
157	reg = <0x01c20050 0x4>;
158	clocks = <&cpu>;
159	clock-output-names = "axi";
160	};
161
162	ahb1: ahb1_clk@01c20054 {
163	#clock-cells = <0>;
164	compatible = "allwinner,sun6i-a31-ahb1-clk";
165	reg = <0x01c20054 0x4>;
166	clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
167	clock-output-names = "ahb1";
168	};
169
170	apb1: apb1_clk@01c20054 {
171	#clock-cells = <0>;
172	compatible = "allwinner,sun4i-a10-apb0-clk";
173	reg = <0x01c20054 0x4>;
174	clocks = <&ahb1>;
175	clock-output-names = "apb1";
176	};
177
178	ahb1_gates: clk@01c20060 {
179	#clock-cells = <1>;
180	compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
181	reg = <0x01c20060 0x8>;
182	clocks = <&ahb1>;
c0a6e360 MR	183	clock-indices = <1>, <6>,
	184	<8>, <9>, <10>,
	185	<13>, <14>,
	186	<19>, <20>,
	187	<21>, <24>, <26>,
	188	<29>, <32>, <36>,
	189	<40>, <44>, <46>,
	190	<52>, <54>,
	191	<57>;
a0e9e9be VP	192	clock-output-names = "ahb1_mipidsi", "ahb1_dma",
	193	"ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
	194	"ahb1_nand", "ahb1_sdram",
	195	"ahb1_hstimer", "ahb1_spi0",
	196	"ahb1_spi1", "ahb1_otg", "ahb1_ehci",
	197	"ahb1_ohci", "ahb1_ve", "ahb1_lcd",
	198	"ahb1_csi", "ahb1_be", "ahb1_fe",
	199	"ahb1_gpu", "ahb1_spinlock",
	200	"ahb1_drc";
	201	};
	202
	203	apb1_gates: clk@01c20068 {
	204	#clock-cells = <1>;
	205	compatible = "allwinner,sun8i-a23-apb1-gates-clk";
	206	reg = <0x01c20068 0x4>;
	207	clocks = <&apb1>;
c0a6e360 MR	208	clock-indices = <0>, <5>,
c0a6e360 MR	209	<12>, <13>;
a0e9e9be VP	210	clock-output-names = "apb1_codec", "apb1_pio",
	211	"apb1_daudio0", "apb1_daudio1";
	212	};
	213
	214	apb2: clk@01c20058 {
	215	#clock-cells = <0>;
	216	compatible = "allwinner,sun4i-a10-apb1-clk";
	217	reg = <0x01c20058 0x4>;
	218	clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
	219	clock-output-names = "apb2";
	220	};
	221
	222	apb2_gates: clk@01c2006c {
	223	#clock-cells = <1>;
	224	compatible = "allwinner,sun8i-a23-apb2-gates-clk";
	225	reg = <0x01c2006c 0x4>;
	226	clocks = <&apb2>;
c0a6e360 MR	227	clock-indices = <0>, <1>,
	228	<2>, <16>,
	229	<17>, <18>,
	230	<19>, <20>;
a0e9e9be VP	231	clock-output-names = "apb2_i2c0", "apb2_i2c1",
	232	"apb2_i2c2", "apb2_uart0",
	233	"apb2_uart1", "apb2_uart2",
	234	"apb2_uart3", "apb2_uart4";
	235	};
	236
	237	mmc0_clk: clk@01c20088 {
	238	#clock-cells = <1>;
	239	compatible = "allwinner,sun4i-a10-mmc-clk";
	240	reg = <0x01c20088 0x4>;
	241	clocks = <&osc24M>, <&pll6 0>;
	242	clock-output-names = "mmc0",
	243	"mmc0_output",
	244	"mmc0_sample";
	245	};
	246
	247	mmc1_clk: clk@01c2008c {
	248	#clock-cells = <1>;
	249	compatible = "allwinner,sun4i-a10-mmc-clk";
	250	reg = <0x01c2008c 0x4>;
	251	clocks = <&osc24M>, <&pll6 0>;
	252	clock-output-names = "mmc1",
	253	"mmc1_output",
	254	"mmc1_sample";
	255	};
	256
	257	mmc2_clk: clk@01c20090 {
	258	#clock-cells = <1>;
	259	compatible = "allwinner,sun4i-a10-mmc-clk";
	260	reg = <0x01c20090 0x4>;
	261	clocks = <&osc24M>, <&pll6 0>;
	262	clock-output-names = "mmc2",
	263	"mmc2_output",
	264	"mmc2_sample";
	265	};
ef3476e2 HG	266
	267	usb_clk: clk@01c200cc {
	268	#clock-cells = <1>;
	269	#reset-cells = <1>;
	270	compatible = "allwinner,sun8i-a23-usb-clk";
	271	reg = <0x01c200cc 0x4>;
	272	clocks = <&osc24M>;
	273	clock-output-names = "usb_phy0", "usb_phy1", "usb_hsic",
	274	"usb_hsic_12M", "usb_ohci0";
	275	};
a0e9e9be VP	276	};
	277
	278	soc@01c00000 {
	279	compatible = "simple-bus";
	280	#address-cells = <1>;
	281	#size-cells = <1>;
	282	ranges;
	283
	284	dma: dma-controller@01c02000 {
	285	compatible = "allwinner,sun8i-a23-dma";
	286	reg = <0x01c02000 0x1000>;
	287	interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
	288	clocks = <&ahb1_gates 6>;
	289	resets = <&ahb1_rst 6>;
	290	#dma-cells = <1>;
	291	};
	292
	293	mmc0: mmc@01c0f000 {
	294	compatible = "allwinner,sun5i-a13-mmc";
	295	reg = <0x01c0f000 0x1000>;
	296	clocks = <&ahb1_gates 8>,
	297	<&mmc0_clk 0>,
	298	<&mmc0_clk 1>,
	299	<&mmc0_clk 2>;
	300	clock-names = "ahb",
	301	"mmc",
	302	"output",
	303	"sample";
	304	resets = <&ahb1_rst 8>;
	305	reset-names = "ahb";
	306	interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
	307	status = "disabled";
	308	#address-cells = <1>;
	309	#size-cells = <0>;
	310	};
	311
	312	mmc1: mmc@01c10000 {
	313	compatible = "allwinner,sun5i-a13-mmc";
	314	reg = <0x01c10000 0x1000>;
	315	clocks = <&ahb1_gates 9>,
	316	<&mmc1_clk 0>,
	317	<&mmc1_clk 1>,
	318	<&mmc1_clk 2>;
	319	clock-names = "ahb",
	320	"mmc",
	321	"output",
	322	"sample";
	323	resets = <&ahb1_rst 9>;
	324	reset-names = "ahb";
	325	interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
	326	status = "disabled";
	327	#address-cells = <1>;
	328	#size-cells = <0>;
	329	};
	330
	331	mmc2: mmc@01c11000 {
	332	compatible = "allwinner,sun5i-a13-mmc";
	333	reg = <0x01c11000 0x1000>;
	334	clocks = <&ahb1_gates 10>,
	335	<&mmc2_clk 0>,
	336	<&mmc2_clk 1>,
	337	<&mmc2_clk 2>;
	338	clock-names = "ahb",
	339	"mmc",
340	"output",
341	"sample";
342	resets = <&ahb1_rst 10>;
343	reset-names = "ahb";
344	interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
345	status = "disabled";
346	#address-cells = <1>;
347	#size-cells = <0>;
348	};
349
350	pio: pinctrl@01c20800 {
351	/* compatible gets set in SoC specific dtsi file */
352	reg = <0x01c20800 0x400>;
353	/* interrupts get set in SoC specific dtsi file */
354	clocks = <&apb1_gates 5>;
355	gpio-controller;
356	interrupt-controller;
357	#address-cells = <1>;
358	#size-cells = <0>;
359	#gpio-cells = <3>;
360
361	uart0_pins_a: uart0@0 {
362	allwinner,pins = "PF2", "PF4";
363	allwinner,function = "uart0";
364	allwinner,drive = <SUN4I_PINCTRL_10_MA>;
365	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
366	};
367
368	mmc0_pins_a: mmc0@0 {
369	allwinner,pins = "PF0", "PF1", "PF2",
370	"PF3", "PF4", "PF5";
371	allwinner,function = "mmc0";
372	allwinner,drive = <SUN4I_PINCTRL_30_MA>;
373	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
374	};
375
376	mmc1_pins_a: mmc1@0 {
377	allwinner,pins = "PG0", "PG1", "PG2",
378	"PG3", "PG4", "PG5";
379	allwinner,function = "mmc1";
380	allwinner,drive = <SUN4I_PINCTRL_30_MA>;
381	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
382	};
383
93b129d6 CYT	384	mmc2_8bit_pins: mmc2_8bit {
	385	allwinner,pins = "PC5", "PC6", "PC8",
	386	"PC9", "PC10", "PC11",
	387	"PC12", "PC13", "PC14",
	388	"PC15";
	389	allwinner,function = "mmc2";
	390	allwinner,drive = <SUN4I_PINCTRL_30_MA>;
	391	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
	392	};
	393
a0e9e9be VP	394	i2c0_pins_a: i2c0@0 {
	395	allwinner,pins = "PH2", "PH3";
	396	allwinner,function = "i2c0";
	397	allwinner,drive = <SUN4I_PINCTRL_10_MA>;
	398	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
	399	};
	400
	401	i2c1_pins_a: i2c1@0 {
	402	allwinner,pins = "PH4", "PH5";
	403	allwinner,function = "i2c1";
	404	allwinner,drive = <SUN4I_PINCTRL_10_MA>;
	405	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
	406	};
	407
	408	i2c2_pins_a: i2c2@0 {
	409	allwinner,pins = "PE12", "PE13";
	410	allwinner,function = "i2c2";
	411	allwinner,drive = <SUN4I_PINCTRL_10_MA>;
	412	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
	413	};
	414	};
	415
	416	ahb1_rst: reset@01c202c0 {
	417	#reset-cells = <1>;
	418	compatible = "allwinner,sun6i-a31-clock-reset";
	419	reg = <0x01c202c0 0xc>;
	420	};
	421
	422	apb1_rst: reset@01c202d0 {
	423	#reset-cells = <1>;
	424	compatible = "allwinner,sun6i-a31-clock-reset";
	425	reg = <0x01c202d0 0x4>;
	426	};
	427
	428	apb2_rst: reset@01c202d8 {
	429	#reset-cells = <1>;
	430	compatible = "allwinner,sun6i-a31-clock-reset";
	431	reg = <0x01c202d8 0x4>;
	432	};
	433
	434	timer@01c20c00 {
	435	compatible = "allwinner,sun4i-a10-timer";
	436	reg = <0x01c20c00 0xa0>;
	437	interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
	438	<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	439	clocks = <&osc24M>;
	440	};
	441
	442	wdt0: watchdog@01c20ca0 {
	443	compatible = "allwinner,sun6i-a31-wdt";
	444	reg = <0x01c20ca0 0x20>;
	445	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
	446	};
	447
	448	lradc: lradc@01c22800 {
	449	compatible = "allwinner,sun4i-a10-lradc-keys";
	450	reg = <0x01c22800 0x100>;
	451	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	452	status = "disabled";
	453	};
	454
	455	uart0: serial@01c28000 {
	456	compatible = "snps,dw-apb-uart";
	457	reg = <0x01c28000 0x400>;
458	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
459	reg-shift = <2>;
460	reg-io-width = <4>;
461	clocks = <&apb2_gates 16>;
462	resets = <&apb2_rst 16>;
463	dmas = <&dma 6>, <&dma 6>;
464	dma-names = "rx", "tx";
465	status = "disabled";
466	};
467
468	uart1: serial@01c28400 {
469	compatible = "snps,dw-apb-uart";
470	reg = <0x01c28400 0x400>;
471	interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
472	reg-shift = <2>;
473	reg-io-width = <4>;
474	clocks = <&apb2_gates 17>;
475	resets = <&apb2_rst 17>;
476	dmas = <&dma 7>, <&dma 7>;
477	dma-names = "rx", "tx";
478	status = "disabled";
479	};
480
481	uart2: serial@01c28800 {
482	compatible = "snps,dw-apb-uart";
483	reg = <0x01c28800 0x400>;
484	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
485	reg-shift = <2>;
486	reg-io-width = <4>;
487	clocks = <&apb2_gates 18>;
488	resets = <&apb2_rst 18>;
489	dmas = <&dma 8>, <&dma 8>;
490	dma-names = "rx", "tx";
491	status = "disabled";
492	};
493
494	uart3: serial@01c28c00 {
495	compatible = "snps,dw-apb-uart";
496	reg = <0x01c28c00 0x400>;
497	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
498	reg-shift = <2>;
499	reg-io-width = <4>;
500	clocks = <&apb2_gates 19>;
501	resets = <&apb2_rst 19>;
502	dmas = <&dma 9>, <&dma 9>;
503	dma-names = "rx", "tx";
504	status = "disabled";
505	};
506
507	uart4: serial@01c29000 {
508	compatible = "snps,dw-apb-uart";
509	reg = <0x01c29000 0x400>;
510	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
511	reg-shift = <2>;
512	reg-io-width = <4>;
513	clocks = <&apb2_gates 20>;
514	resets = <&apb2_rst 20>;
515	dmas = <&dma 10>, <&dma 10>;
516	dma-names = "rx", "tx";
517	status = "disabled";
518	};
519
520	i2c0: i2c@01c2ac00 {
521	compatible = "allwinner,sun6i-a31-i2c";
522	reg = <0x01c2ac00 0x400>;
523	interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
524	clocks = <&apb2_gates 0>;
525	resets = <&apb2_rst 0>;
526	status = "disabled";
527	#address-cells = <1>;
528	#size-cells = <0>;
529	};
530
531	i2c1: i2c@01c2b000 {
532	compatible = "allwinner,sun6i-a31-i2c";
533	reg = <0x01c2b000 0x400>;
534	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
535	clocks = <&apb2_gates 1>;
536	resets = <&apb2_rst 1>;
537	status = "disabled";
538	#address-cells = <1>;
539	#size-cells = <0>;
540	};
541
542	i2c2: i2c@01c2b400 {
543	compatible = "allwinner,sun6i-a31-i2c";
544	reg = <0x01c2b400 0x400>;
545	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
546	clocks = <&apb2_gates 2>;
547	resets = <&apb2_rst 2>;
548	status = "disabled";
549	#address-cells = <1>;
550	#size-cells = <0>;
551	};
552
553	gic: interrupt-controller@01c81000 {
554	compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
555	reg = <0x01c81000 0x1000>,
556	<0x01c82000 0x1000>,
557	<0x01c84000 0x2000>,
558	<0x01c86000 0x2000>;
559	interrupt-controller;
560	#interrupt-cells = <3>;
561	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
562	};
563
564	rtc: rtc@01f00000 {
565	compatible = "allwinner,sun6i-a31-rtc";
566	reg = <0x01f00000 0x54>;
567	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
568	<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
569	};
570
571	prcm@01f01400 {
572	compatible = "allwinner,sun8i-a23-prcm";
573	reg = <0x01f01400 0x200>;
574
575	ar100: ar100_clk {
576	compatible = "fixed-factor-clock";
577	#clock-cells = <0>;
578	clock-div = <1>;
579	clock-mult = <1>;
580	clocks = <&osc24M>;
581	clock-output-names = "ar100";
582	};
583
584	ahb0: ahb0_clk {
585	compatible = "fixed-factor-clock";
586	#clock-cells = <0>;
587	clock-div = <1>;
588	clock-mult = <1>;
589	clocks = <&ar100>;
590	clock-output-names = "ahb0";
591	};
592
593	apb0: apb0_clk {
594	compatible = "allwinner,sun8i-a23-apb0-clk";
595	#clock-cells = <0>;
596	clocks = <&ahb0>;
597	clock-output-names = "apb0";
598	};
599
600	apb0_gates: apb0_gates_clk {
601	compatible = "allwinner,sun8i-a23-apb0-gates-clk";
602	#clock-cells = <1>;
603	clocks = <&apb0>;
604	clock-output-names = "apb0_pio", "apb0_timer",
605	"apb0_rsb", "apb0_uart",
606	"apb0_i2c";
607	};
608
609	apb0_rst: apb0_rst {
610	compatible = "allwinner,sun6i-a31-clock-reset";
611	#reset-cells = <1>;
612	};
613	};
614
615	cpucfg@01f01c00 {
616	compatible = "allwinner,sun8i-a23-cpuconfig";
617	reg = <0x01f01c00 0x300>;
618	};
619
620	r_uart: serial@01f02800 {
621	compatible = "snps,dw-apb-uart";
622	reg = <0x01f02800 0x400>;
623	interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
624	reg-shift = <2>;
625	reg-io-width = <4>;
626	clocks = <&apb0_gates 4>;
627	resets = <&apb0_rst 4>;
628	status = "disabled";
629	};
630
631	r_pio: pinctrl@01f02c00 {
632	compatible = "allwinner,sun8i-a23-r-pinctrl";
633	reg = <0x01f02c00 0x400>;
634	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
635	clocks = <&apb0_gates 0>;
636	resets = <&apb0_rst 0>;
637	gpio-controller;
638	interrupt-controller;
639	#address-cells = <1>;
640	#size-cells = <0>;
641	#gpio-cells = <3>;
642
643	r_uart_pins_a: r_uart@0 {
644	allwinner,pins = "PL2", "PL3";
645	allwinner,function = "s_uart";
646	allwinner,drive = <SUN4I_PINCTRL_10_MA>;
647	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
648	};
649	};
650	};
651	};