[deliverable/linux.git] / arch / arm / boot / dts / sun8i-a83t.dtsi

/*
 * Copyright 2015 Vishnu Patekar
 *
 * Vishnu Patekar <vishnupatekar0510@gmail.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.

 */

#include "skeleton.dtsi"

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/pinctrl/sun4i-a10.h>

/ {
	interrupt-parent = <&gic>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0>;
		};

		cpu@1 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <1>;
		};

		cpu@2 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <2>;
		};

		cpu@3 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <3>;
		};

		cpu@100 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0x100>;
		};

		cpu@101 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0x101>;
		};

		cpu@102 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0x102>;
		};

		cpu@103 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0x103>;
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		osc24M: osc24M_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <24000000>;
			clock-output-names = "osc24M";
		};

		osc32k: osc32k_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32768>;
			clock-output-names = "osc32k";
		};
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		pio: pinctrl@01c20800 {
			compatible = "allwinner,sun8i-a83t-pinctrl";
			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x01c20800 0x400>;
			clocks = <&osc24M>;
			gpio-controller;
			interrupt-controller;
			#interrupt-cells = <3>;
			#gpio-cells = <3>;

			mmc0_pins_a: mmc0@0 {
				allwinner,pins = "PF0", "PF1", "PF2",
						 "PF3", "PF4", "PF5";
				allwinner,function = "mmc0";
				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			uart0_pins_a: uart0@0 {
				allwinner,pins = "PF2", "PF4";
				allwinner,function = "uart0";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			uart0_pins_b: uart0@1 {
				allwinner,pins = "PB9", "PB10";
				allwinner,function = "uart0";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};
		};

		uart0: serial@01c28000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28000 0x400>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&osc24M>;
			status = "disabled";
		};

		gic: interrupt-controller@01c81000 {
			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
			reg = <0x01c81000 0x1000>,
			      <0x01c82000 0x1000>,
			      <0x01c84000 0x2000>,
			      <0x01c86000 0x2000>;
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
		};
	};
};
Commit	Line	Data
7c929aa6 VP	1	/*
	2	* Copyright 2015 Vishnu Patekar
	3	*
	4	* Vishnu Patekar <vishnupatekar0510@gmail.com>
	5	*
	6	* This file is dual-licensed: you can use it either under the terms
	7	* of the GPL or the X11 license, at your option. Note that this dual
	8	* licensing only applies to this file, and not this project as a
	9	* whole.
	10	*
	11	* a) This file is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of the
	14	* License, or (at your option) any later version.
	15	*
	16	* This file is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* Or, alternatively,
	22	*
	23	* b) Permission is hereby granted, free of charge, to any person
	24	* obtaining a copy of this software and associated documentation
	25	* files (the "Software"), to deal in the Software without
	26	* restriction, including without limitation the rights to use,
	27	* copy, modify, merge, publish, distribute, sublicense, and/or
	28	* sell copies of the Software, and to permit persons to whom the
	29	* Software is furnished to do so, subject to the following
	30	* conditions:
	31	*
	32	* The above copyright notice and this permission notice shall be
	33	* included in all copies or substantial portions of the Software.
	34	*
	35	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	36	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	37	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	38	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	39	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	40	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	41	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	42	* OTHER DEALINGS IN THE SOFTWARE.
	43
	44	*/
	45
	46	#include "skeleton.dtsi"
	47
	48	#include <dt-bindings/interrupt-controller/arm-gic.h>
	49
	50	#include <dt-bindings/pinctrl/sun4i-a10.h>
	51
	52	/ {
	53	interrupt-parent = <&gic>;
	54
	55	cpus {
	56	#address-cells = <1>;
	57	#size-cells = <0>;
	58
	59	cpu@0 {
	60	compatible = "arm,cortex-a7";
	61	device_type = "cpu";
	62	reg = <0>;
	63	};
	64
65	cpu@1 {
66	compatible = "arm,cortex-a7";
67	device_type = "cpu";
68	reg = <1>;
69	};
70
71	cpu@2 {
72	compatible = "arm,cortex-a7";
73	device_type = "cpu";
74	reg = <2>;
75	};
76
77	cpu@3 {
78	compatible = "arm,cortex-a7";
79	device_type = "cpu";
80	reg = <3>;
81	};
82
83	cpu@100 {
84	compatible = "arm,cortex-a7";
85	device_type = "cpu";
86	reg = <0x100>;
87	};
88
89	cpu@101 {
90	compatible = "arm,cortex-a7";
91	device_type = "cpu";
92	reg = <0x101>;
93	};
94
95	cpu@102 {
96	compatible = "arm,cortex-a7";
97	device_type = "cpu";
98	reg = <0x102>;
99	};
100
101	cpu@103 {
102	compatible = "arm,cortex-a7";
103	device_type = "cpu";
104	reg = <0x103>;
105	};
106	};
107
108	timer {
109	compatible = "arm,armv7-timer";
110	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_LOW)>,
111	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_LOW)>,
112	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_LOW)>,
113	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_LOW)>;
114	};
115
116	clocks {
117	#address-cells = <1>;
118	#size-cells = <1>;
119	ranges;
120
121	osc24M: osc24M_clk {
122	#clock-cells = <0>;
123	compatible = "fixed-clock";
124	clock-frequency = <24000000>;
125	clock-output-names = "osc24M";
126	};
127
128	osc32k: osc32k_clk {
129	#clock-cells = <0>;
130	compatible = "fixed-clock";
131	clock-frequency = <32768>;
132	clock-output-names = "osc32k";
133	};
134	};
135
136	soc {
137	compatible = "simple-bus";
138	#address-cells = <1>;
139	#size-cells = <1>;
140	ranges;
141
142	pio: pinctrl@01c20800 {
143	compatible = "allwinner,sun8i-a83t-pinctrl";
144	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
145	<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
146	<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
147	reg = <0x01c20800 0x400>;
148	clocks = <&osc24M>;
149	gpio-controller;
150	interrupt-controller;
151	#interrupt-cells = <3>;
152	#gpio-cells = <3>;
153
154	mmc0_pins_a: mmc0@0 {
155	allwinner,pins = "PF0", "PF1", "PF2",
156	"PF3", "PF4", "PF5";
157	allwinner,function = "mmc0";
158	allwinner,drive = <SUN4I_PINCTRL_30_MA>;
159	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
160	};
161
162	uart0_pins_a: uart0@0 {
163	allwinner,pins = "PF2", "PF4";
164	allwinner,function = "uart0";
165	allwinner,drive = <SUN4I_PINCTRL_10_MA>;
166	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
167	};
168
169	uart0_pins_b: uart0@1 {
170	allwinner,pins = "PB9", "PB10";
171	allwinner,function = "uart0";
172	allwinner,drive = <SUN4I_PINCTRL_10_MA>;
173	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
174	};
175	};
176
177	uart0: serial@01c28000 {
178	compatible = "snps,dw-apb-uart";
179	reg = <0x01c28000 0x400>;
180	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
181	reg-shift = <2>;
182	reg-io-width = <4>;
183	clocks = <&osc24M>;
184	status = "disabled";
185	};
186
187	gic: interrupt-controller@01c81000 {
188	compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
189	reg = <0x01c81000 0x1000>,
190	<0x01c82000 0x1000>,
191	<0x01c84000 0x2000>,
192	<0x01c86000 0x2000>;
193	interrupt-controller;
194	#interrupt-cells = <3>;
195	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_HIGH)>;
196	};
197	};
198	};