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Merge branch 'for-4.5' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/percpu
[deliverable/linux.git] / arch / arm / boot / dts / sun9i-a80.dtsi
CommitLineData
4ab328f0
CYT		 1/*
2 * Copyright 2014 Chen-Yu Tsai
3 *
4 * Chen-Yu Tsai <wens@csie.org>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
136d18a8 11 * a) This file is free software; you can redistribute it and/or
4ab328f0
CYT		 12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
136d18a8 16 * This file is distributed in the hope that it will be useful,
4ab328f0
CYT		 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
4ab328f0
CYT		 21 * Or, alternatively,
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
43 */
44
71455701 45#include "skeleton64.dtsi"
4ab328f0 46
19882b84
MR		 47#include <dt-bindings/interrupt-controller/arm-gic.h>
48
092a0c3b 49#include <dt-bindings/pinctrl/sun4i-a10.h>
4ab328f0
CYT		 50
51/ {
52 interrupt-parent = <&gic>;
53
4ab328f0
CYT		 54 cpus {
55 #address-cells = <1>;
56 #size-cells = <0>;
57
58 cpu0: cpu@0 {
59 compatible = "arm,cortex-a7";
60 device_type = "cpu";
61 reg = <0x0>;
62 };
63
64 cpu1: cpu@1 {
65 compatible = "arm,cortex-a7";
66 device_type = "cpu";
67 reg = <0x1>;
68 };
69
70 cpu2: cpu@2 {
71 compatible = "arm,cortex-a7";
72 device_type = "cpu";
73 reg = <0x2>;
74 };
75
76 cpu3: cpu@3 {
77 compatible = "arm,cortex-a7";
78 device_type = "cpu";
79 reg = <0x3>;
80 };
81
82 cpu4: cpu@100 {
83 compatible = "arm,cortex-a15";
84 device_type = "cpu";
85 reg = <0x100>;
86 };
87
88 cpu5: cpu@101 {
89 compatible = "arm,cortex-a15";
90 device_type = "cpu";
91 reg = <0x101>;
92 };
93
94 cpu6: cpu@102 {
95 compatible = "arm,cortex-a15";
96 device_type = "cpu";
97 reg = <0x102>;
98 };
99
100 cpu7: cpu@103 {
101 compatible = "arm,cortex-a15";
102 device_type = "cpu";
103 reg = <0x103>;
104 };
105 };
106
107 memory {
108 /* 8GB max. with LPAE */
109 reg = <0 0x20000000 0x02 0>;
110 };
111
51e9f5ff
CYT		 112 timer {
113 compatible = "arm,armv7-timer";
114 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
115 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
116 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
117 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
118 clock-frequency = <24000000>;
119 arm,cpu-registers-not-fw-configured;
120 };
121
4ab328f0
CYT		 122 clocks {
123 #address-cells = <1>;
124 #size-cells = <1>;
125 /*
126 * map 64 bit address range down to 32 bits,
127 * as the peripherals are all under 512MB.
128 */
129 ranges = <0 0 0 0x20000000>;
130
131 osc24M: osc24M_clk {
132 #clock-cells = <0>;
133 compatible = "fixed-clock";
134 clock-frequency = <24000000>;
135 clock-output-names = "osc24M";
136 };
137
138 osc32k: osc32k_clk {
139 #clock-cells = <0>;
140 compatible = "fixed-clock";
141 clock-frequency = <32768>;
142 clock-output-names = "osc32k";
143 };
ac399a97 144
bc8ffc2d
CYT		 145 usb_mod_clk: clk@00a08000 {
146 #clock-cells = <1>;
147 #reset-cells = <1>;
148 compatible = "allwinner,sun9i-a80-usb-mod-clk";
149 reg = <0x00a08000 0x4>;
150 clocks = <&ahb1_gates 1>;
151 clock-output-names = "usb0_ahb", "usb_ohci0",
152 "usb1_ahb", "usb_ohci1",
153 "usb2_ahb", "usb_ohci2";
154 };
155
156 usb_phy_clk: clk@00a08004 {
157 #clock-cells = <1>;
158 #reset-cells = <1>;
159 compatible = "allwinner,sun9i-a80-usb-phy-clk";
160 reg = <0x00a08004 0x4>;
161 clocks = <&ahb1_gates 1>;
162 clock-output-names = "usb_phy0", "usb_hsic1_480M",
163 "usb_phy1", "usb_hsic2_480M",
164 "usb_phy2", "usb_hsic_12M";
165 };
166
ac399a97
CYT		 167 pll4: clk@0600000c {
168 #clock-cells = <0>;
169 compatible = "allwinner,sun9i-a80-pll4-clk";
170 reg = <0x0600000c 0x4>;
171 clocks = <&osc24M>;
172 clock-output-names = "pll4";
173 };
174
175 pll12: clk@0600002c {
176 #clock-cells = <0>;
177 compatible = "allwinner,sun9i-a80-pll4-clk";
178 reg = <0x0600002c 0x4>;
179 clocks = <&osc24M>;
180 clock-output-names = "pll12";
181 };
182
183 gt_clk: clk@0600005c {
184 #clock-cells = <0>;
185 compatible = "allwinner,sun9i-a80-gt-clk";
186 reg = <0x0600005c 0x4>;
187 clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
188 clock-output-names = "gt";
189 };
190
191 ahb0: clk@06000060 {
192 #clock-cells = <0>;
193 compatible = "allwinner,sun9i-a80-ahb-clk";
194 reg = <0x06000060 0x4>;
195 clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
196 clock-output-names = "ahb0";
197 };
198
199 ahb1: clk@06000064 {
200 #clock-cells = <0>;
201 compatible = "allwinner,sun9i-a80-ahb-clk";
202 reg = <0x06000064 0x4>;
203 clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
204 clock-output-names = "ahb1";
205 };
206
207 ahb2: clk@06000068 {
208 #clock-cells = <0>;
209 compatible = "allwinner,sun9i-a80-ahb-clk";
210 reg = <0x06000068 0x4>;
211 clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
212 clock-output-names = "ahb2";
213 };
214
215 apb0: clk@06000070 {
216 #clock-cells = <0>;
217 compatible = "allwinner,sun9i-a80-apb0-clk";
218 reg = <0x06000070 0x4>;
219 clocks = <&osc24M>, <&pll4>;
220 clock-output-names = "apb0";
221 };
222
223 apb1: clk@06000074 {
224 #clock-cells = <0>;
225 compatible = "allwinner,sun9i-a80-apb1-clk";
226 reg = <0x06000074 0x4>;
227 clocks = <&osc24M>, <&pll4>;
228 clock-output-names = "apb1";
229 };
230
231 cci400_clk: clk@06000078 {
232 #clock-cells = <0>;
233 compatible = "allwinner,sun9i-a80-gt-clk";
234 reg = <0x06000078 0x4>;
235 clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
236 clock-output-names = "cci400";
237 };
238
d2aa6f54
CYT		 239 mmc0_clk: clk@06000410 {
240 #clock-cells = <1>;
241 compatible = "allwinner,sun9i-a80-mmc-clk";
242 reg = <0x06000410 0x4>;
243 clocks = <&osc24M>, <&pll4>;
244 clock-output-names = "mmc0", "mmc0_output",
245 "mmc0_sample";
246 };
247
248 mmc1_clk: clk@06000414 {
249 #clock-cells = <1>;
250 compatible = "allwinner,sun9i-a80-mmc-clk";
251 reg = <0x06000414 0x4>;
252 clocks = <&osc24M>, <&pll4>;
253 clock-output-names = "mmc1", "mmc1_output",
254 "mmc1_sample";
255 };
256
257 mmc2_clk: clk@06000418 {
258 #clock-cells = <1>;
259 compatible = "allwinner,sun9i-a80-mmc-clk";
260 reg = <0x06000418 0x4>;
261 clocks = <&osc24M>, <&pll4>;
262 clock-output-names = "mmc2", "mmc2_output",
263 "mmc2_sample";
264 };
265
266 mmc3_clk: clk@0600041c {
267 #clock-cells = <1>;
268 compatible = "allwinner,sun9i-a80-mmc-clk";
269 reg = <0x0600041c 0x4>;
270 clocks = <&osc24M>, <&pll4>;
271 clock-output-names = "mmc3", "mmc3_output",
272 "mmc3_sample";
273 };
274
ac399a97
CYT		 275 ahb0_gates: clk@06000580 {
276 #clock-cells = <1>;
277 compatible = "allwinner,sun9i-a80-ahb0-gates-clk";
278 reg = <0x06000580 0x4>;
279 clocks = <&ahb0>;
06f28275
MR		 280 clock-indices = <0>, <1>, <3>,
281 <5>, <8>, <12>,
282 <13>, <14>,
283 <15>, <16>, <18>,
284 <20>, <21>, <22>,
285 <23>;
ac399a97
CYT		 286 clock-output-names = "ahb0_fd", "ahb0_ve", "ahb0_gpu",
287 "ahb0_ss", "ahb0_sd", "ahb0_nand1",
288 "ahb0_nand0", "ahb0_sdram",
289 "ahb0_mipi_hsi", "ahb0_sata", "ahb0_ts",
d8cacaa3 290 "ahb0_spi0", "ahb0_spi1", "ahb0_spi2",
ac399a97
CYT		 291 "ahb0_spi3";
292 };
293
294 ahb1_gates: clk@06000584 {
295 #clock-cells = <1>;
296 compatible = "allwinner,sun9i-a80-ahb1-gates-clk";
297 reg = <0x06000584 0x4>;
298 clocks = <&ahb1>;
06f28275
MR		 299 clock-indices = <0>, <1>,
300 <17>, <21>,
301 <22>, <23>,
302 <24>;
ac399a97
CYT		 303 clock-output-names = "ahb1_usbotg", "ahb1_usbhci",
304 "ahb1_gmac", "ahb1_msgbox",
305 "ahb1_spinlock", "ahb1_hstimer",
306 "ahb1_dma";
307 };
308
309 ahb2_gates: clk@06000588 {
310 #clock-cells = <1>;
311 compatible = "allwinner,sun9i-a80-ahb2-gates-clk";
312 reg = <0x06000588 0x4>;
313 clocks = <&ahb2>;
06f28275
MR		 314 clock-indices = <0>, <1>,
315 <2>, <4>, <5>,
316 <7>, <8>, <11>;
ac399a97
CYT		 317 clock-output-names = "ahb2_lcd0", "ahb2_lcd1",
318 "ahb2_edp", "ahb2_csi", "ahb2_hdmi",
319 "ahb2_de", "ahb2_mp", "ahb2_mipi_dsi";
320 };
321
322 apb0_gates: clk@06000590 {
323 #clock-cells = <1>;
324 compatible = "allwinner,sun9i-a80-apb0-gates-clk";
325 reg = <0x06000590 0x4>;
326 clocks = <&apb0>;
06f28275
MR		 327 clock-indices = <1>, <5>,
328 <11>, <12>, <13>,
329 <15>, <17>, <18>,
330 <19>;
ac399a97
CYT		 331 clock-output-names = "apb0_spdif", "apb0_pio",
332 "apb0_ac97", "apb0_i2s0", "apb0_i2s1",
333 "apb0_lradc", "apb0_gpadc", "apb0_twd",
334 "apb0_cirtx";
335 };
336
337 apb1_gates: clk@06000594 {
338 #clock-cells = <1>;
339 compatible = "allwinner,sun9i-a80-apb1-gates-clk";
340 reg = <0x06000594 0x4>;
341 clocks = <&apb1>;
06f28275
MR		 342 clock-indices = <0>, <1>,
343 <2>, <3>, <4>,
344 <16>, <17>,
345 <18>, <19>,
346 <20>, <21>;
ac399a97
CYT		 347 clock-output-names = "apb1_i2c0", "apb1_i2c1",
348 "apb1_i2c2", "apb1_i2c3", "apb1_i2c4",
349 "apb1_uart0", "apb1_uart1",
350 "apb1_uart2", "apb1_uart3",
351 "apb1_uart4", "apb1_uart5";
352 };
4ab328f0
CYT		 353 };
354
355 soc {
356 compatible = "simple-bus";
357 #address-cells = <1>;
358 #size-cells = <1>;
359 /*
360 * map 64 bit address range down to 32 bits,
361 * as the peripherals are all under 512MB.
362 */
363 ranges = <0 0 0 0x20000000>;
364
70472163
CYT		 365 ehci0: usb@00a00000 {
366 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
367 reg = <0x00a00000 0x100>;
368 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
369 clocks = <&usb_mod_clk 1>;
370 resets = <&usb_mod_clk 17>;
371 phys = <&usbphy1>;
372 phy-names = "usb";
373 status = "disabled";
374 };
375
376 ohci0: usb@00a00400 {
377 compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
378 reg = <0x00a00400 0x100>;
379 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
380 clocks = <&usb_mod_clk 1>, <&usb_mod_clk 2>;
381 resets = <&usb_mod_clk 17>;
382 phys = <&usbphy1>;
383 phy-names = "usb";
384 status = "disabled";
385 };
386
1af5d192
CYT		 387 usbphy1: phy@00a00800 {
388 compatible = "allwinner,sun9i-a80-usb-phy";
389 reg = <0x00a00800 0x4>;
390 clocks = <&usb_phy_clk 1>;
391 clock-names = "phy";
392 resets = <&usb_phy_clk 17>;
393 reset-names = "phy";
394 status = "disabled";
395 #phy-cells = <0>;
396 };
397
70472163
CYT		 398 ehci1: usb@00a01000 {
399 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
400 reg = <0x00a01000 0x100>;
401 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
402 clocks = <&usb_mod_clk 3>;
403 resets = <&usb_mod_clk 18>;
404 phys = <&usbphy2>;
405 phy-names = "usb";
406 status = "disabled";
407 };
408
1af5d192
CYT		 409 usbphy2: phy@00a01800 {
410 compatible = "allwinner,sun9i-a80-usb-phy";
411 reg = <0x00a01800 0x4>;
412 clocks = <&usb_phy_clk 2>, <&usb_phy_clk 10>,
413 <&usb_phy_clk 3>;
414 clock-names = "hsic_480M", "hsic_12M", "phy";
415 resets = <&usb_phy_clk 18>, <&usb_phy_clk 19>;
416 reset-names = "hsic", "phy";
417 status = "disabled";
418 #phy-cells = <0>;
419 /* usb1 is always used with HSIC */
420 phy_type = "hsic";
421 };
422
70472163
CYT		 423 ehci2: usb@00a02000 {
424 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
425 reg = <0x00a02000 0x100>;
426 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
427 clocks = <&usb_mod_clk 5>;
428 resets = <&usb_mod_clk 19>;
429 phys = <&usbphy3>;
430 phy-names = "usb";
431 status = "disabled";
432 };
433
434 ohci2: usb@00a02400 {
435 compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
436 reg = <0x00a02400 0x100>;
437 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
438 clocks = <&usb_mod_clk 5>, <&usb_mod_clk 6>;
439 resets = <&usb_mod_clk 19>;
440 phys = <&usbphy3>;
441 phy-names = "usb";
442 status = "disabled";
443 };
444
1af5d192
CYT		 445 usbphy3: phy@00a02800 {
446 compatible = "allwinner,sun9i-a80-usb-phy";
447 reg = <0x00a02800 0x4>;
448 clocks = <&usb_phy_clk 4>, <&usb_phy_clk 10>,
449 <&usb_phy_clk 5>;
450 clock-names = "hsic_480M", "hsic_12M", "phy";
451 resets = <&usb_phy_clk 20>, <&usb_phy_clk 21>;
452 reset-names = "hsic", "phy";
453 status = "disabled";
454 #phy-cells = <0>;
455 };
456
2f6941cd
CYT		 457 mmc0: mmc@01c0f000 {
458 compatible = "allwinner,sun5i-a13-mmc";
459 reg = <0x01c0f000 0x1000>;
460 clocks = <&mmc_config_clk 0>, <&mmc0_clk 0>,
461 <&mmc0_clk 1>, <&mmc0_clk 2>;
462 clock-names = "ahb", "mmc", "output", "sample";
463 resets = <&mmc_config_clk 0>;
464 reset-names = "ahb";
465 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
466 status = "disabled";
4c1bb9c3
HG		 467 #address-cells = <1>;
468 #size-cells = <0>;
2f6941cd
CYT		 469 };
470
471 mmc1: mmc@01c10000 {
472 compatible = "allwinner,sun5i-a13-mmc";
473 reg = <0x01c10000 0x1000>;
474 clocks = <&mmc_config_clk 1>, <&mmc1_clk 0>,
475 <&mmc1_clk 1>, <&mmc1_clk 2>;
476 clock-names = "ahb", "mmc", "output", "sample";
477 resets = <&mmc_config_clk 1>;
478 reset-names = "ahb";
479 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
480 status = "disabled";
4c1bb9c3
HG		 481 #address-cells = <1>;
482 #size-cells = <0>;
2f6941cd
CYT		 483 };
484
485 mmc2: mmc@01c11000 {
486 compatible = "allwinner,sun5i-a13-mmc";
487 reg = <0x01c11000 0x1000>;
488 clocks = <&mmc_config_clk 2>, <&mmc2_clk 0>,
489 <&mmc2_clk 1>, <&mmc2_clk 2>;
490 clock-names = "ahb", "mmc", "output", "sample";
491 resets = <&mmc_config_clk 2>;
492 reset-names = "ahb";
493 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
494 status = "disabled";
4c1bb9c3
HG		 495 #address-cells = <1>;
496 #size-cells = <0>;
2f6941cd
CYT		 497 };
498
499 mmc3: mmc@01c12000 {
500 compatible = "allwinner,sun5i-a13-mmc";
501 reg = <0x01c12000 0x1000>;
502 clocks = <&mmc_config_clk 3>, <&mmc3_clk 0>,
503 <&mmc3_clk 1>, <&mmc3_clk 2>;
504 clock-names = "ahb", "mmc", "output", "sample";
505 resets = <&mmc_config_clk 3>;
506 reset-names = "ahb";
507 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
508 status = "disabled";
4c1bb9c3
HG		 509 #address-cells = <1>;
510 #size-cells = <0>;
2f6941cd
CYT		 511 };
512
9c56f3f3
CYT		 513 mmc_config_clk: clk@01c13000 {
514 compatible = "allwinner,sun9i-a80-mmc-config-clk";
515 reg = <0x01c13000 0x10>;
516 clocks = <&ahb0_gates 8>;
517 clock-names = "ahb";
518 resets = <&ahb0_resets 8>;
519 reset-names = "ahb";
520 #clock-cells = <1>;
521 #reset-cells = <1>;
522 clock-output-names = "mmc0_config", "mmc1_config",
523 "mmc2_config", "mmc3_config";
524 };
525
4ab328f0
CYT		 526 gic: interrupt-controller@01c41000 {
527 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
528 reg = <0x01c41000 0x1000>,
529 <0x01c42000 0x1000>,
530 <0x01c44000 0x2000>,
531 <0x01c46000 0x2000>;
532 interrupt-controller;
533 #interrupt-cells = <3>;
19882b84 534 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
4ab328f0
CYT		 535 };
536
ac399a97
CYT		 537 ahb0_resets: reset@060005a0 {
538 #reset-cells = <1>;
539 compatible = "allwinner,sun6i-a31-clock-reset";
540 reg = <0x060005a0 0x4>;
541 };
542
543 ahb1_resets: reset@060005a4 {
544 #reset-cells = <1>;
545 compatible = "allwinner,sun6i-a31-clock-reset";
546 reg = <0x060005a4 0x4>;
547 };
548
549 ahb2_resets: reset@060005a8 {
550 #reset-cells = <1>;
551 compatible = "allwinner,sun6i-a31-clock-reset";
552 reg = <0x060005a8 0x4>;
553 };
554
555 apb0_resets: reset@060005b0 {
556 #reset-cells = <1>;
557 compatible = "allwinner,sun6i-a31-clock-reset";
558 reg = <0x060005b0 0x4>;
559 };
560
561 apb1_resets: reset@060005b4 {
562 #reset-cells = <1>;
563 compatible = "allwinner,sun6i-a31-clock-reset";
564 reg = <0x060005b4 0x4>;
565 };
566
4ab328f0
CYT		 567 timer@06000c00 {
568 compatible = "allwinner,sun4i-a10-timer";
569 reg = <0x06000c00 0xa0>;
19882b84
MR		 570 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
571 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
572 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
573 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
574 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
575 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
4ab328f0
CYT		 576
577 clocks = <&osc24M>;
578 };
579
6d6693c8
CYT		 580 wdt: watchdog@06000ca0 {
581 compatible = "allwinner,sun6i-a31-wdt";
582 reg = <0x06000ca0 0x20>;
583 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
584 };
585
43d024d3
MR		 586 pio: pinctrl@06000800 {
587 compatible = "allwinner,sun9i-a80-pinctrl";
588 reg = <0x06000800 0x400>;
19882b84
MR		 589 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
590 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
591 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
592 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
593 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
43d024d3
MR		 594 clocks = <&apb0_gates 5>;
595 gpio-controller;
596 interrupt-controller;
6d55d339 597 #interrupt-cells = <3>;
43d024d3
MR		 598 #size-cells = <0>;
599 #gpio-cells = <3>;
888366fa 600
6657a058
CYT		 601 i2c3_pins_a: i2c3@0 {
602 allwinner,pins = "PG10", "PG11";
603 allwinner,function = "i2c3";
092a0c3b
MR		 604 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
605 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
6657a058
CYT		 606 };
607
cd23e2e5
CYT		 608 mmc0_pins: mmc0 {
609 allwinner,pins = "PF0", "PF1" ,"PF2", "PF3",
610 "PF4", "PF5";
611 allwinner,function = "mmc0";
612 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
613 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
614 };
615
23a602b6
CYT		 616 mmc2_8bit_pins: mmc2_8bit {
617 allwinner,pins = "PC6", "PC7", "PC8", "PC9",
618 "PC10", "PC11", "PC12",
619 "PC13", "PC14", "PC15";
620 allwinner,function = "mmc2";
621 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
622 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
6657a058
CYT		 623 };
624
888366fa
MR		 625 uart0_pins_a: uart0@0 {
626 allwinner,pins = "PH12", "PH13";
627 allwinner,function = "uart0";
092a0c3b
MR		 628 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
629 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
888366fa 630 };
2a950b2c
CYT		 631
632 uart4_pins_a: uart4@0 {
633 allwinner,pins = "PG12", "PG13", "PG14", "PG15";
634 allwinner,function = "uart4";
092a0c3b
MR		 635 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
636 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
2a950b2c 637 };
43d024d3
MR		 638 };
639
4ab328f0
CYT		 640 uart0: serial@07000000 {
641 compatible = "snps,dw-apb-uart";
642 reg = <0x07000000 0x400>;
19882b84 643 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
4ab328f0
CYT		 644 reg-shift = <2>;
645 reg-io-width = <4>;
ac399a97
CYT		 646 clocks = <&apb1_gates 16>;
647 resets = <&apb1_resets 16>;
4ab328f0
CYT		 648 status = "disabled";
649 };
650
651 uart1: serial@07000400 {
652 compatible = "snps,dw-apb-uart";
653 reg = <0x07000400 0x400>;
19882b84 654 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
4ab328f0
CYT		 655 reg-shift = <2>;
656 reg-io-width = <4>;
ac399a97
CYT		 657 clocks = <&apb1_gates 17>;
658 resets = <&apb1_resets 17>;
4ab328f0
CYT		 659 status = "disabled";
660 };
661
662 uart2: serial@07000800 {
663 compatible = "snps,dw-apb-uart";
664 reg = <0x07000800 0x400>;
19882b84 665 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
4ab328f0
CYT		 666 reg-shift = <2>;
667 reg-io-width = <4>;
ac399a97
CYT		 668 clocks = <&apb1_gates 18>;
669 resets = <&apb1_resets 18>;
4ab328f0
CYT		 670 status = "disabled";
671 };
672
673 uart3: serial@07000c00 {
674 compatible = "snps,dw-apb-uart";
675 reg = <0x07000c00 0x400>;
19882b84 676 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
4ab328f0
CYT		 677 reg-shift = <2>;
678 reg-io-width = <4>;
ac399a97
CYT		 679 clocks = <&apb1_gates 19>;
680 resets = <&apb1_resets 19>;
4ab328f0
CYT		 681 status = "disabled";
682 };
683
684 uart4: serial@07001000 {
685 compatible = "snps,dw-apb-uart";
686 reg = <0x07001000 0x400>;
19882b84 687 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
4ab328f0
CYT		 688 reg-shift = <2>;
689 reg-io-width = <4>;
ac399a97
CYT		 690 clocks = <&apb1_gates 20>;
691 resets = <&apb1_resets 20>;
4ab328f0
CYT		 692 status = "disabled";
693 };
694
695 uart5: serial@07001400 {
696 compatible = "snps,dw-apb-uart";
697 reg = <0x07001400 0x400>;
19882b84 698 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4ab328f0
CYT		 699 reg-shift = <2>;
700 reg-io-width = <4>;
ac399a97
CYT		 701 clocks = <&apb1_gates 21>;
702 resets = <&apb1_resets 21>;
4ab328f0
CYT		 703 status = "disabled";
704 };
705
e4aa753a
CYT		 706 i2c0: i2c@07002800 {
707 compatible = "allwinner,sun6i-a31-i2c";
708 reg = <0x07002800 0x400>;
19882b84 709 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
e4aa753a
CYT		 710 clocks = <&apb1_gates 0>;
711 resets = <&apb1_resets 0>;
712 status = "disabled";
713 #address-cells = <1>;
714 #size-cells = <0>;
715 };
716
717 i2c1: i2c@07002c00 {
718 compatible = "allwinner,sun6i-a31-i2c";
719 reg = <0x07002c00 0x400>;
19882b84 720 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
e4aa753a
CYT		 721 clocks = <&apb1_gates 1>;
722 resets = <&apb1_resets 1>;
723 status = "disabled";
724 #address-cells = <1>;
725 #size-cells = <0>;
726 };
727
728 i2c2: i2c@07003000 {
729 compatible = "allwinner,sun6i-a31-i2c";
730 reg = <0x07003000 0x400>;
19882b84 731 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
e4aa753a
CYT		 732 clocks = <&apb1_gates 2>;
733 resets = <&apb1_resets 2>;
734 status = "disabled";
735 #address-cells = <1>;
736 #size-cells = <0>;
737 };
738
739 i2c3: i2c@07003400 {
740 compatible = "allwinner,sun6i-a31-i2c";
741 reg = <0x07003400 0x400>;
19882b84 742 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
e4aa753a
CYT		 743 clocks = <&apb1_gates 3>;
744 resets = <&apb1_resets 3>;
745 status = "disabled";
746 #address-cells = <1>;
747 #size-cells = <0>;
748 };
749
750 i2c4: i2c@07003800 {
751 compatible = "allwinner,sun6i-a31-i2c";
752 reg = <0x07003800 0x400>;
19882b84 753 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
e4aa753a
CYT		 754 clocks = <&apb1_gates 4>;
755 resets = <&apb1_resets 4>;
756 status = "disabled";
757 #address-cells = <1>;
758 #size-cells = <0>;
759 };
760
4ab328f0
CYT		 761 r_wdt: watchdog@08001000 {
762 compatible = "allwinner,sun6i-a31-wdt";
763 reg = <0x08001000 0x20>;
19882b84 764 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
4ab328f0
CYT		 765 };
766
767 r_uart: serial@08002800 {
768 compatible = "snps,dw-apb-uart";
769 reg = <0x08002800 0x400>;
19882b84 770 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
4ab328f0
CYT		 771 reg-shift = <2>;
772 reg-io-width = <4>;
773 clocks = <&osc24M>;
774 status = "disabled";
775 };
776 };
777};
Linux kernel - Deliverables
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