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ARM: dts: sun8i: Enable ARM architected timer on A23
[deliverable/linux.git] / arch / arm / boot / dts / sun9i-a80.dtsi
CommitLineData
4ab328f0
CYT		 1/*
2 * Copyright 2014 Chen-Yu Tsai
3 *
4 * Chen-Yu Tsai <wens@csie.org>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
136d18a8 11 * a) This file is free software; you can redistribute it and/or
4ab328f0
CYT		 12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
136d18a8 16 * This file is distributed in the hope that it will be useful,
4ab328f0
CYT		 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
136d18a8 22 * License along with this file; if not, write to the Free
4ab328f0
CYT		 23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
48 */
49
71455701 50#include "skeleton64.dtsi"
4ab328f0 51
19882b84
MR		 52#include <dt-bindings/interrupt-controller/arm-gic.h>
53
092a0c3b 54#include <dt-bindings/pinctrl/sun4i-a10.h>
4ab328f0
CYT		 55
56/ {
57 interrupt-parent = <&gic>;
58
4ab328f0
CYT		 59 cpus {
60 #address-cells = <1>;
61 #size-cells = <0>;
62
63 cpu0: cpu@0 {
64 compatible = "arm,cortex-a7";
65 device_type = "cpu";
66 reg = <0x0>;
67 };
68
69 cpu1: cpu@1 {
70 compatible = "arm,cortex-a7";
71 device_type = "cpu";
72 reg = <0x1>;
73 };
74
75 cpu2: cpu@2 {
76 compatible = "arm,cortex-a7";
77 device_type = "cpu";
78 reg = <0x2>;
79 };
80
81 cpu3: cpu@3 {
82 compatible = "arm,cortex-a7";
83 device_type = "cpu";
84 reg = <0x3>;
85 };
86
87 cpu4: cpu@100 {
88 compatible = "arm,cortex-a15";
89 device_type = "cpu";
90 reg = <0x100>;
91 };
92
93 cpu5: cpu@101 {
94 compatible = "arm,cortex-a15";
95 device_type = "cpu";
96 reg = <0x101>;
97 };
98
99 cpu6: cpu@102 {
100 compatible = "arm,cortex-a15";
101 device_type = "cpu";
102 reg = <0x102>;
103 };
104
105 cpu7: cpu@103 {
106 compatible = "arm,cortex-a15";
107 device_type = "cpu";
108 reg = <0x103>;
109 };
110 };
111
112 memory {
113 /* 8GB max. with LPAE */
114 reg = <0 0x20000000 0x02 0>;
115 };
116
117 clocks {
118 #address-cells = <1>;
119 #size-cells = <1>;
120 /*
121 * map 64 bit address range down to 32 bits,
122 * as the peripherals are all under 512MB.
123 */
124 ranges = <0 0 0 0x20000000>;
125
126 osc24M: osc24M_clk {
127 #clock-cells = <0>;
128 compatible = "fixed-clock";
129 clock-frequency = <24000000>;
130 clock-output-names = "osc24M";
131 };
132
133 osc32k: osc32k_clk {
134 #clock-cells = <0>;
135 compatible = "fixed-clock";
136 clock-frequency = <32768>;
137 clock-output-names = "osc32k";
138 };
ac399a97 139
bc8ffc2d
CYT		 140 usb_mod_clk: clk@00a08000 {
141 #clock-cells = <1>;
142 #reset-cells = <1>;
143 compatible = "allwinner,sun9i-a80-usb-mod-clk";
144 reg = <0x00a08000 0x4>;
145 clocks = <&ahb1_gates 1>;
146 clock-output-names = "usb0_ahb", "usb_ohci0",
147 "usb1_ahb", "usb_ohci1",
148 "usb2_ahb", "usb_ohci2";
149 };
150
151 usb_phy_clk: clk@00a08004 {
152 #clock-cells = <1>;
153 #reset-cells = <1>;
154 compatible = "allwinner,sun9i-a80-usb-phy-clk";
155 reg = <0x00a08004 0x4>;
156 clocks = <&ahb1_gates 1>;
157 clock-output-names = "usb_phy0", "usb_hsic1_480M",
158 "usb_phy1", "usb_hsic2_480M",
159 "usb_phy2", "usb_hsic_12M";
160 };
161
ac399a97
CYT		 162 pll4: clk@0600000c {
163 #clock-cells = <0>;
164 compatible = "allwinner,sun9i-a80-pll4-clk";
165 reg = <0x0600000c 0x4>;
166 clocks = <&osc24M>;
167 clock-output-names = "pll4";
168 };
169
170 pll12: clk@0600002c {
171 #clock-cells = <0>;
172 compatible = "allwinner,sun9i-a80-pll4-clk";
173 reg = <0x0600002c 0x4>;
174 clocks = <&osc24M>;
175 clock-output-names = "pll12";
176 };
177
178 gt_clk: clk@0600005c {
179 #clock-cells = <0>;
180 compatible = "allwinner,sun9i-a80-gt-clk";
181 reg = <0x0600005c 0x4>;
182 clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
183 clock-output-names = "gt";
184 };
185
186 ahb0: clk@06000060 {
187 #clock-cells = <0>;
188 compatible = "allwinner,sun9i-a80-ahb-clk";
189 reg = <0x06000060 0x4>;
190 clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
191 clock-output-names = "ahb0";
192 };
193
194 ahb1: clk@06000064 {
195 #clock-cells = <0>;
196 compatible = "allwinner,sun9i-a80-ahb-clk";
197 reg = <0x06000064 0x4>;
198 clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
199 clock-output-names = "ahb1";
200 };
201
202 ahb2: clk@06000068 {
203 #clock-cells = <0>;
204 compatible = "allwinner,sun9i-a80-ahb-clk";
205 reg = <0x06000068 0x4>;
206 clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
207 clock-output-names = "ahb2";
208 };
209
210 apb0: clk@06000070 {
211 #clock-cells = <0>;
212 compatible = "allwinner,sun9i-a80-apb0-clk";
213 reg = <0x06000070 0x4>;
214 clocks = <&osc24M>, <&pll4>;
215 clock-output-names = "apb0";
216 };
217
218 apb1: clk@06000074 {
219 #clock-cells = <0>;
220 compatible = "allwinner,sun9i-a80-apb1-clk";
221 reg = <0x06000074 0x4>;
222 clocks = <&osc24M>, <&pll4>;
223 clock-output-names = "apb1";
224 };
225
226 cci400_clk: clk@06000078 {
227 #clock-cells = <0>;
228 compatible = "allwinner,sun9i-a80-gt-clk";
229 reg = <0x06000078 0x4>;
230 clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
231 clock-output-names = "cci400";
232 };
233
d2aa6f54
CYT		 234 mmc0_clk: clk@06000410 {
235 #clock-cells = <1>;
236 compatible = "allwinner,sun9i-a80-mmc-clk";
237 reg = <0x06000410 0x4>;
238 clocks = <&osc24M>, <&pll4>;
239 clock-output-names = "mmc0", "mmc0_output",
240 "mmc0_sample";
241 };
242
243 mmc1_clk: clk@06000414 {
244 #clock-cells = <1>;
245 compatible = "allwinner,sun9i-a80-mmc-clk";
246 reg = <0x06000414 0x4>;
247 clocks = <&osc24M>, <&pll4>;
248 clock-output-names = "mmc1", "mmc1_output",
249 "mmc1_sample";
250 };
251
252 mmc2_clk: clk@06000418 {
253 #clock-cells = <1>;
254 compatible = "allwinner,sun9i-a80-mmc-clk";
255 reg = <0x06000418 0x4>;
256 clocks = <&osc24M>, <&pll4>;
257 clock-output-names = "mmc2", "mmc2_output",
258 "mmc2_sample";
259 };
260
261 mmc3_clk: clk@0600041c {
262 #clock-cells = <1>;
263 compatible = "allwinner,sun9i-a80-mmc-clk";
264 reg = <0x0600041c 0x4>;
265 clocks = <&osc24M>, <&pll4>;
266 clock-output-names = "mmc3", "mmc3_output",
267 "mmc3_sample";
268 };
269
ac399a97
CYT		 270 ahb0_gates: clk@06000580 {
271 #clock-cells = <1>;
272 compatible = "allwinner,sun9i-a80-ahb0-gates-clk";
273 reg = <0x06000580 0x4>;
274 clocks = <&ahb0>;
203c6883
CYT		 275 clock-indices = <0>, <1>, <3>, <5>, <8>, <12>, <13>,
276 <14>, <15>, <16>, <18>, <20>, <21>,
277 <22>, <23>;
ac399a97
CYT		 278 clock-output-names = "ahb0_fd", "ahb0_ve", "ahb0_gpu",
279 "ahb0_ss", "ahb0_sd", "ahb0_nand1",
280 "ahb0_nand0", "ahb0_sdram",
281 "ahb0_mipi_hsi", "ahb0_sata", "ahb0_ts",
282 "ahb0_spi0","ahb0_spi1", "ahb0_spi2",
283 "ahb0_spi3";
284 };
285
286 ahb1_gates: clk@06000584 {
287 #clock-cells = <1>;
288 compatible = "allwinner,sun9i-a80-ahb1-gates-clk";
289 reg = <0x06000584 0x4>;
290 clocks = <&ahb1>;
203c6883 291 clock-indices = <0>, <1>, <17>, <21>, <22>, <23>, <24>;
ac399a97
CYT		 292 clock-output-names = "ahb1_usbotg", "ahb1_usbhci",
293 "ahb1_gmac", "ahb1_msgbox",
294 "ahb1_spinlock", "ahb1_hstimer",
295 "ahb1_dma";
296 };
297
298 ahb2_gates: clk@06000588 {
299 #clock-cells = <1>;
300 compatible = "allwinner,sun9i-a80-ahb2-gates-clk";
301 reg = <0x06000588 0x4>;
302 clocks = <&ahb2>;
203c6883
CYT		 303 clock-indices = <0>, <1>, <2>, <4>, <5>, <7>, <8>,
304 <11>;
ac399a97
CYT		 305 clock-output-names = "ahb2_lcd0", "ahb2_lcd1",
306 "ahb2_edp", "ahb2_csi", "ahb2_hdmi",
307 "ahb2_de", "ahb2_mp", "ahb2_mipi_dsi";
308 };
309
310 apb0_gates: clk@06000590 {
311 #clock-cells = <1>;
312 compatible = "allwinner,sun9i-a80-apb0-gates-clk";
313 reg = <0x06000590 0x4>;
314 clocks = <&apb0>;
203c6883
CYT		 315 clock-indices = <1>, <5>, <11>, <12>, <13>, <15>,
316 <17>, <18>, <19>;
ac399a97
CYT		 317 clock-output-names = "apb0_spdif", "apb0_pio",
318 "apb0_ac97", "apb0_i2s0", "apb0_i2s1",
319 "apb0_lradc", "apb0_gpadc", "apb0_twd",
320 "apb0_cirtx";
321 };
322
323 apb1_gates: clk@06000594 {
324 #clock-cells = <1>;
325 compatible = "allwinner,sun9i-a80-apb1-gates-clk";
326 reg = <0x06000594 0x4>;
327 clocks = <&apb1>;
203c6883
CYT		 328 clock-indices = <0>, <1>, <2>, <3>, <4>,
329 <16>, <17>, <18>, <19>, <20>, <21>;
ac399a97
CYT		 330 clock-output-names = "apb1_i2c0", "apb1_i2c1",
331 "apb1_i2c2", "apb1_i2c3", "apb1_i2c4",
332 "apb1_uart0", "apb1_uart1",
333 "apb1_uart2", "apb1_uart3",
334 "apb1_uart4", "apb1_uart5";
335 };
4ab328f0
CYT		 336 };
337
338 soc {
339 compatible = "simple-bus";
340 #address-cells = <1>;
341 #size-cells = <1>;
342 /*
343 * map 64 bit address range down to 32 bits,
344 * as the peripherals are all under 512MB.
345 */
346 ranges = <0 0 0 0x20000000>;
347
70472163
CYT		 348 ehci0: usb@00a00000 {
349 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
350 reg = <0x00a00000 0x100>;
351 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
352 clocks = <&usb_mod_clk 1>;
353 resets = <&usb_mod_clk 17>;
354 phys = <&usbphy1>;
355 phy-names = "usb";
356 status = "disabled";
357 };
358
359 ohci0: usb@00a00400 {
360 compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
361 reg = <0x00a00400 0x100>;
362 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
363 clocks = <&usb_mod_clk 1>, <&usb_mod_clk 2>;
364 resets = <&usb_mod_clk 17>;
365 phys = <&usbphy1>;
366 phy-names = "usb";
367 status = "disabled";
368 };
369
1af5d192
CYT		 370 usbphy1: phy@00a00800 {
371 compatible = "allwinner,sun9i-a80-usb-phy";
372 reg = <0x00a00800 0x4>;
373 clocks = <&usb_phy_clk 1>;
374 clock-names = "phy";
375 resets = <&usb_phy_clk 17>;
376 reset-names = "phy";
377 status = "disabled";
378 #phy-cells = <0>;
379 };
380
70472163
CYT		 381 ehci1: usb@00a01000 {
382 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
383 reg = <0x00a01000 0x100>;
384 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
385 clocks = <&usb_mod_clk 3>;
386 resets = <&usb_mod_clk 18>;
387 phys = <&usbphy2>;
388 phy-names = "usb";
389 status = "disabled";
390 };
391
1af5d192
CYT		 392 usbphy2: phy@00a01800 {
393 compatible = "allwinner,sun9i-a80-usb-phy";
394 reg = <0x00a01800 0x4>;
395 clocks = <&usb_phy_clk 2>, <&usb_phy_clk 10>,
396 <&usb_phy_clk 3>;
397 clock-names = "hsic_480M", "hsic_12M", "phy";
398 resets = <&usb_phy_clk 18>, <&usb_phy_clk 19>;
399 reset-names = "hsic", "phy";
400 status = "disabled";
401 #phy-cells = <0>;
402 /* usb1 is always used with HSIC */
403 phy_type = "hsic";
404 };
405
70472163
CYT		 406 ehci2: usb@00a02000 {
407 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
408 reg = <0x00a02000 0x100>;
409 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
410 clocks = <&usb_mod_clk 5>;
411 resets = <&usb_mod_clk 19>;
412 phys = <&usbphy3>;
413 phy-names = "usb";
414 status = "disabled";
415 };
416
417 ohci2: usb@00a02400 {
418 compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
419 reg = <0x00a02400 0x100>;
420 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
421 clocks = <&usb_mod_clk 5>, <&usb_mod_clk 6>;
422 resets = <&usb_mod_clk 19>;
423 phys = <&usbphy3>;
424 phy-names = "usb";
425 status = "disabled";
426 };
427
1af5d192
CYT		 428 usbphy3: phy@00a02800 {
429 compatible = "allwinner,sun9i-a80-usb-phy";
430 reg = <0x00a02800 0x4>;
431 clocks = <&usb_phy_clk 4>, <&usb_phy_clk 10>,
432 <&usb_phy_clk 5>;
433 clock-names = "hsic_480M", "hsic_12M", "phy";
434 resets = <&usb_phy_clk 20>, <&usb_phy_clk 21>;
435 reset-names = "hsic", "phy";
436 status = "disabled";
437 #phy-cells = <0>;
438 };
439
2f6941cd
CYT		 440 mmc0: mmc@01c0f000 {
441 compatible = "allwinner,sun5i-a13-mmc";
442 reg = <0x01c0f000 0x1000>;
443 clocks = <&mmc_config_clk 0>, <&mmc0_clk 0>,
444 <&mmc0_clk 1>, <&mmc0_clk 2>;
445 clock-names = "ahb", "mmc", "output", "sample";
446 resets = <&mmc_config_clk 0>;
447 reset-names = "ahb";
448 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
449 status = "disabled";
4c1bb9c3
HG		 450 #address-cells = <1>;
451 #size-cells = <0>;
2f6941cd
CYT		 452 };
453
454 mmc1: mmc@01c10000 {
455 compatible = "allwinner,sun5i-a13-mmc";
456 reg = <0x01c10000 0x1000>;
457 clocks = <&mmc_config_clk 1>, <&mmc1_clk 0>,
458 <&mmc1_clk 1>, <&mmc1_clk 2>;
459 clock-names = "ahb", "mmc", "output", "sample";
460 resets = <&mmc_config_clk 1>;
461 reset-names = "ahb";
462 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
463 status = "disabled";
4c1bb9c3
HG		 464 #address-cells = <1>;
465 #size-cells = <0>;
2f6941cd
CYT		 466 };
467
468 mmc2: mmc@01c11000 {
469 compatible = "allwinner,sun5i-a13-mmc";
470 reg = <0x01c11000 0x1000>;
471 clocks = <&mmc_config_clk 2>, <&mmc2_clk 0>,
472 <&mmc2_clk 1>, <&mmc2_clk 2>;
473 clock-names = "ahb", "mmc", "output", "sample";
474 resets = <&mmc_config_clk 2>;
475 reset-names = "ahb";
476 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
477 status = "disabled";
4c1bb9c3
HG		 478 #address-cells = <1>;
479 #size-cells = <0>;
2f6941cd
CYT		 480 };
481
482 mmc3: mmc@01c12000 {
483 compatible = "allwinner,sun5i-a13-mmc";
484 reg = <0x01c12000 0x1000>;
485 clocks = <&mmc_config_clk 3>, <&mmc3_clk 0>,
486 <&mmc3_clk 1>, <&mmc3_clk 2>;
487 clock-names = "ahb", "mmc", "output", "sample";
488 resets = <&mmc_config_clk 3>;
489 reset-names = "ahb";
490 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
491 status = "disabled";
4c1bb9c3
HG		 492 #address-cells = <1>;
493 #size-cells = <0>;
2f6941cd
CYT		 494 };
495
9c56f3f3
CYT		 496 mmc_config_clk: clk@01c13000 {
497 compatible = "allwinner,sun9i-a80-mmc-config-clk";
498 reg = <0x01c13000 0x10>;
499 clocks = <&ahb0_gates 8>;
500 clock-names = "ahb";
501 resets = <&ahb0_resets 8>;
502 reset-names = "ahb";
503 #clock-cells = <1>;
504 #reset-cells = <1>;
505 clock-output-names = "mmc0_config", "mmc1_config",
506 "mmc2_config", "mmc3_config";
507 };
508
4ab328f0
CYT		 509 gic: interrupt-controller@01c41000 {
510 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
511 reg = <0x01c41000 0x1000>,
512 <0x01c42000 0x1000>,
513 <0x01c44000 0x2000>,
514 <0x01c46000 0x2000>;
515 interrupt-controller;
516 #interrupt-cells = <3>;
19882b84 517 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
4ab328f0
CYT		 518 };
519
ac399a97
CYT		 520 ahb0_resets: reset@060005a0 {
521 #reset-cells = <1>;
522 compatible = "allwinner,sun6i-a31-clock-reset";
523 reg = <0x060005a0 0x4>;
524 };
525
526 ahb1_resets: reset@060005a4 {
527 #reset-cells = <1>;
528 compatible = "allwinner,sun6i-a31-clock-reset";
529 reg = <0x060005a4 0x4>;
530 };
531
532 ahb2_resets: reset@060005a8 {
533 #reset-cells = <1>;
534 compatible = "allwinner,sun6i-a31-clock-reset";
535 reg = <0x060005a8 0x4>;
536 };
537
538 apb0_resets: reset@060005b0 {
539 #reset-cells = <1>;
540 compatible = "allwinner,sun6i-a31-clock-reset";
541 reg = <0x060005b0 0x4>;
542 };
543
544 apb1_resets: reset@060005b4 {
545 #reset-cells = <1>;
546 compatible = "allwinner,sun6i-a31-clock-reset";
547 reg = <0x060005b4 0x4>;
548 };
549
4ab328f0
CYT		 550 timer@06000c00 {
551 compatible = "allwinner,sun4i-a10-timer";
552 reg = <0x06000c00 0xa0>;
19882b84
MR		 553 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
554 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
555 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
556 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
557 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
558 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
4ab328f0
CYT		 559
560 clocks = <&osc24M>;
561 };
562
43d024d3
MR		 563 pio: pinctrl@06000800 {
564 compatible = "allwinner,sun9i-a80-pinctrl";
565 reg = <0x06000800 0x400>;
19882b84
MR		 566 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
567 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
568 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
569 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
570 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
43d024d3
MR		 571 clocks = <&apb0_gates 5>;
572 gpio-controller;
573 interrupt-controller;
574 #interrupt-cells = <2>;
575 #size-cells = <0>;
576 #gpio-cells = <3>;
888366fa 577
6657a058
CYT		 578 i2c3_pins_a: i2c3@0 {
579 allwinner,pins = "PG10", "PG11";
580 allwinner,function = "i2c3";
092a0c3b
MR		 581 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
582 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
6657a058
CYT		 583 };
584
cd23e2e5
CYT		 585 mmc0_pins: mmc0 {
586 allwinner,pins = "PF0", "PF1" ,"PF2", "PF3",
587 "PF4", "PF5";
588 allwinner,function = "mmc0";
589 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
590 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
591 };
592
23a602b6
CYT		 593 mmc2_8bit_pins: mmc2_8bit {
594 allwinner,pins = "PC6", "PC7", "PC8", "PC9",
595 "PC10", "PC11", "PC12",
596 "PC13", "PC14", "PC15";
597 allwinner,function = "mmc2";
598 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
599 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
6657a058
CYT		 600 };
601
888366fa
MR		 602 uart0_pins_a: uart0@0 {
603 allwinner,pins = "PH12", "PH13";
604 allwinner,function = "uart0";
092a0c3b
MR		 605 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
606 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
888366fa 607 };
2a950b2c
CYT		 608
609 uart4_pins_a: uart4@0 {
610 allwinner,pins = "PG12", "PG13", "PG14", "PG15";
611 allwinner,function = "uart4";
092a0c3b
MR		 612 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
613 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
2a950b2c 614 };
43d024d3
MR		 615 };
616
4ab328f0
CYT		 617 uart0: serial@07000000 {
618 compatible = "snps,dw-apb-uart";
619 reg = <0x07000000 0x400>;
19882b84 620 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
4ab328f0
CYT		 621 reg-shift = <2>;
622 reg-io-width = <4>;
ac399a97
CYT		 623 clocks = <&apb1_gates 16>;
624 resets = <&apb1_resets 16>;
4ab328f0
CYT		 625 status = "disabled";
626 };
627
628 uart1: serial@07000400 {
629 compatible = "snps,dw-apb-uart";
630 reg = <0x07000400 0x400>;
19882b84 631 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
4ab328f0
CYT		 632 reg-shift = <2>;
633 reg-io-width = <4>;
ac399a97
CYT		 634 clocks = <&apb1_gates 17>;
635 resets = <&apb1_resets 17>;
4ab328f0
CYT		 636 status = "disabled";
637 };
638
639 uart2: serial@07000800 {
640 compatible = "snps,dw-apb-uart";
641 reg = <0x07000800 0x400>;
19882b84 642 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
4ab328f0
CYT		 643 reg-shift = <2>;
644 reg-io-width = <4>;
ac399a97
CYT		 645 clocks = <&apb1_gates 18>;
646 resets = <&apb1_resets 18>;
4ab328f0
CYT		 647 status = "disabled";
648 };
649
650 uart3: serial@07000c00 {
651 compatible = "snps,dw-apb-uart";
652 reg = <0x07000c00 0x400>;
19882b84 653 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
4ab328f0
CYT		 654 reg-shift = <2>;
655 reg-io-width = <4>;
ac399a97
CYT		 656 clocks = <&apb1_gates 19>;
657 resets = <&apb1_resets 19>;
4ab328f0
CYT		 658 status = "disabled";
659 };
660
661 uart4: serial@07001000 {
662 compatible = "snps,dw-apb-uart";
663 reg = <0x07001000 0x400>;
19882b84 664 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
4ab328f0
CYT		 665 reg-shift = <2>;
666 reg-io-width = <4>;
ac399a97
CYT		 667 clocks = <&apb1_gates 20>;
668 resets = <&apb1_resets 20>;
4ab328f0
CYT		 669 status = "disabled";
670 };
671
672 uart5: serial@07001400 {
673 compatible = "snps,dw-apb-uart";
674 reg = <0x07001400 0x400>;
19882b84 675 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4ab328f0
CYT		 676 reg-shift = <2>;
677 reg-io-width = <4>;
ac399a97
CYT		 678 clocks = <&apb1_gates 21>;
679 resets = <&apb1_resets 21>;
4ab328f0
CYT		 680 status = "disabled";
681 };
682
e4aa753a
CYT		 683 i2c0: i2c@07002800 {
684 compatible = "allwinner,sun6i-a31-i2c";
685 reg = <0x07002800 0x400>;
19882b84 686 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
e4aa753a
CYT		 687 clocks = <&apb1_gates 0>;
688 resets = <&apb1_resets 0>;
689 status = "disabled";
690 #address-cells = <1>;
691 #size-cells = <0>;
692 };
693
694 i2c1: i2c@07002c00 {
695 compatible = "allwinner,sun6i-a31-i2c";
696 reg = <0x07002c00 0x400>;
19882b84 697 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
e4aa753a
CYT		 698 clocks = <&apb1_gates 1>;
699 resets = <&apb1_resets 1>;
700 status = "disabled";
701 #address-cells = <1>;
702 #size-cells = <0>;
703 };
704
705 i2c2: i2c@07003000 {
706 compatible = "allwinner,sun6i-a31-i2c";
707 reg = <0x07003000 0x400>;
19882b84 708 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
e4aa753a
CYT		 709 clocks = <&apb1_gates 2>;
710 resets = <&apb1_resets 2>;
711 status = "disabled";
712 #address-cells = <1>;
713 #size-cells = <0>;
714 };
715
716 i2c3: i2c@07003400 {
717 compatible = "allwinner,sun6i-a31-i2c";
718 reg = <0x07003400 0x400>;
19882b84 719 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
e4aa753a
CYT		 720 clocks = <&apb1_gates 3>;
721 resets = <&apb1_resets 3>;
722 status = "disabled";
723 #address-cells = <1>;
724 #size-cells = <0>;
725 };
726
727 i2c4: i2c@07003800 {
728 compatible = "allwinner,sun6i-a31-i2c";
729 reg = <0x07003800 0x400>;
19882b84 730 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
e4aa753a
CYT		 731 clocks = <&apb1_gates 4>;
732 resets = <&apb1_resets 4>;
733 status = "disabled";
734 #address-cells = <1>;
735 #size-cells = <0>;
736 };
737
4ab328f0
CYT		 738 r_wdt: watchdog@08001000 {
739 compatible = "allwinner,sun6i-a31-wdt";
740 reg = <0x08001000 0x20>;
19882b84 741 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
4ab328f0
CYT		 742 };
743
744 r_uart: serial@08002800 {
745 compatible = "snps,dw-apb-uart";
746 reg = <0x08002800 0x400>;
19882b84 747 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
4ab328f0
CYT		 748 reg-shift = <2>;
749 reg-io-width = <4>;
750 clocks = <&osc24M>;
751 status = "disabled";
752 };
753 };
754};
Linux kernel - Deliverables
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