[deliverable/linux.git] / arch / arm / boot / dts / sun9i-a80.dtsi

/*
 * Copyright 2014 Chen-Yu Tsai
 *
 * Chen-Yu Tsai <wens@csie.org>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 *     You should have received a copy of the GNU General Public
 *     License along with this file; if not, write to the Free
 *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
 *     MA 02110-1301 USA
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include "skeleton64.dtsi"

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/pinctrl/sun4i-a10.h>

/ {
	interrupt-parent = <&gic>;

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
		serial4 = &uart4;
		serial5 = &uart5;
		serial6 = &r_uart;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0x0>;
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0x1>;
		};

		cpu2: cpu@2 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0x2>;
		};

		cpu3: cpu@3 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0x3>;
		};

		cpu4: cpu@100 {
			compatible = "arm,cortex-a15";
			device_type = "cpu";
			reg = <0x100>;
		};

		cpu5: cpu@101 {
			compatible = "arm,cortex-a15";
			device_type = "cpu";
			reg = <0x101>;
		};

		cpu6: cpu@102 {
			compatible = "arm,cortex-a15";
			device_type = "cpu";
			reg = <0x102>;
		};

		cpu7: cpu@103 {
			compatible = "arm,cortex-a15";
			device_type = "cpu";
			reg = <0x103>;
		};
	};

	memory {
		/* 8GB max. with LPAE */
		reg = <0 0x20000000 0x02 0>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		/*
		 * map 64 bit address range down to 32 bits,
		 * as the peripherals are all under 512MB.
		 */
		ranges = <0 0 0 0x20000000>;

		osc24M: osc24M_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <24000000>;
			clock-output-names = "osc24M";
		};

		osc32k: osc32k_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32768>;
			clock-output-names = "osc32k";
		};

		pll4: clk@0600000c {
			#clock-cells = <0>;
			compatible = "allwinner,sun9i-a80-pll4-clk";
			reg = <0x0600000c 0x4>;
			clocks = <&osc24M>;
			clock-output-names = "pll4";
		};

		pll12: clk@0600002c {
			#clock-cells = <0>;
			compatible = "allwinner,sun9i-a80-pll4-clk";
			reg = <0x0600002c 0x4>;
			clocks = <&osc24M>;
			clock-output-names = "pll12";
		};

		gt_clk: clk@0600005c {
			#clock-cells = <0>;
			compatible = "allwinner,sun9i-a80-gt-clk";
			reg = <0x0600005c 0x4>;
			clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
			clock-output-names = "gt";
		};

		ahb0: clk@06000060 {
			#clock-cells = <0>;
			compatible = "allwinner,sun9i-a80-ahb-clk";
			reg = <0x06000060 0x4>;
			clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
			clock-output-names = "ahb0";
		};

		ahb1: clk@06000064 {
			#clock-cells = <0>;
			compatible = "allwinner,sun9i-a80-ahb-clk";
			reg = <0x06000064 0x4>;
			clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
			clock-output-names = "ahb1";
		};

		ahb2: clk@06000068 {
			#clock-cells = <0>;
			compatible = "allwinner,sun9i-a80-ahb-clk";
			reg = <0x06000068 0x4>;
			clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
			clock-output-names = "ahb2";
		};

		apb0: clk@06000070 {
			#clock-cells = <0>;
			compatible = "allwinner,sun9i-a80-apb0-clk";
			reg = <0x06000070 0x4>;
			clocks = <&osc24M>, <&pll4>;
			clock-output-names = "apb0";
		};

		apb1: clk@06000074 {
			#clock-cells = <0>;
			compatible = "allwinner,sun9i-a80-apb1-clk";
			reg = <0x06000074 0x4>;
			clocks = <&osc24M>, <&pll4>;
			clock-output-names = "apb1";
		};

		cci400_clk: clk@06000078 {
			#clock-cells = <0>;
			compatible = "allwinner,sun9i-a80-gt-clk";
			reg = <0x06000078 0x4>;
			clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
			clock-output-names = "cci400";
		};

		mmc0_clk: clk@06000410 {
			#clock-cells = <1>;
			compatible = "allwinner,sun9i-a80-mmc-clk";
			reg = <0x06000410 0x4>;
			clocks = <&osc24M>, <&pll4>;
			clock-output-names = "mmc0", "mmc0_output",
					     "mmc0_sample";
		};

		mmc1_clk: clk@06000414 {
			#clock-cells = <1>;
			compatible = "allwinner,sun9i-a80-mmc-clk";
			reg = <0x06000414 0x4>;
			clocks = <&osc24M>, <&pll4>;
			clock-output-names = "mmc1", "mmc1_output",
					     "mmc1_sample";
		};

		mmc2_clk: clk@06000418 {
			#clock-cells = <1>;
			compatible = "allwinner,sun9i-a80-mmc-clk";
			reg = <0x06000418 0x4>;
			clocks = <&osc24M>, <&pll4>;
			clock-output-names = "mmc2", "mmc2_output",
					     "mmc2_sample";
		};

		mmc3_clk: clk@0600041c {
			#clock-cells = <1>;
			compatible = "allwinner,sun9i-a80-mmc-clk";
			reg = <0x0600041c 0x4>;
			clocks = <&osc24M>, <&pll4>;
			clock-output-names = "mmc3", "mmc3_output",
					     "mmc3_sample";
		};

		ahb0_gates: clk@06000580 {
			#clock-cells = <1>;
			compatible = "allwinner,sun9i-a80-ahb0-gates-clk";
			reg = <0x06000580 0x4>;
			clocks = <&ahb0>;
			clock-indices = <0>, <1>, <3>, <5>, <8>, <12>, <13>,
					<14>, <15>, <16>, <18>, <20>, <21>,
					<22>, <23>;
			clock-output-names = "ahb0_fd", "ahb0_ve", "ahb0_gpu",
					"ahb0_ss", "ahb0_sd", "ahb0_nand1",
					"ahb0_nand0", "ahb0_sdram",
					"ahb0_mipi_hsi", "ahb0_sata", "ahb0_ts",
					"ahb0_spi0","ahb0_spi1", "ahb0_spi2",
					"ahb0_spi3";
		};

		ahb1_gates: clk@06000584 {
			#clock-cells = <1>;
			compatible = "allwinner,sun9i-a80-ahb1-gates-clk";
			reg = <0x06000584 0x4>;
			clocks = <&ahb1>;
			clock-indices = <0>, <1>, <17>, <21>, <22>, <23>, <24>;
			clock-output-names = "ahb1_usbotg", "ahb1_usbhci",
					"ahb1_gmac", "ahb1_msgbox",
					"ahb1_spinlock", "ahb1_hstimer",
					"ahb1_dma";
		};

		ahb2_gates: clk@06000588 {
			#clock-cells = <1>;
			compatible = "allwinner,sun9i-a80-ahb2-gates-clk";
			reg = <0x06000588 0x4>;
			clocks = <&ahb2>;
			clock-indices = <0>, <1>, <2>, <4>, <5>, <7>, <8>,
					<11>;
			clock-output-names = "ahb2_lcd0", "ahb2_lcd1",
					"ahb2_edp", "ahb2_csi", "ahb2_hdmi",
					"ahb2_de", "ahb2_mp", "ahb2_mipi_dsi";
		};

		apb0_gates: clk@06000590 {
			#clock-cells = <1>;
			compatible = "allwinner,sun9i-a80-apb0-gates-clk";
			reg = <0x06000590 0x4>;
			clocks = <&apb0>;
			clock-indices = <1>, <5>, <11>, <12>, <13>, <15>,
					<17>, <18>, <19>;
			clock-output-names = "apb0_spdif", "apb0_pio",
					"apb0_ac97", "apb0_i2s0", "apb0_i2s1",
					"apb0_lradc", "apb0_gpadc", "apb0_twd",
					"apb0_cirtx";
		};

		apb1_gates: clk@06000594 {
			#clock-cells = <1>;
			compatible = "allwinner,sun9i-a80-apb1-gates-clk";
			reg = <0x06000594 0x4>;
			clocks = <&apb1>;
			clock-indices = <0>, <1>, <2>, <3>, <4>,
					<16>, <17>, <18>, <19>, <20>, <21>;
			clock-output-names = "apb1_i2c0", "apb1_i2c1",
					"apb1_i2c2", "apb1_i2c3", "apb1_i2c4",
					"apb1_uart0", "apb1_uart1",
					"apb1_uart2", "apb1_uart3",
					"apb1_uart4", "apb1_uart5";
		};
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		/*
		 * map 64 bit address range down to 32 bits,
		 * as the peripherals are all under 512MB.
		 */
		ranges = <0 0 0 0x20000000>;

		gic: interrupt-controller@01c41000 {
			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
			reg = <0x01c41000 0x1000>,
			      <0x01c42000 0x1000>,
			      <0x01c44000 0x2000>,
			      <0x01c46000 0x2000>;
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
		};

		ahb0_resets: reset@060005a0 {
			#reset-cells = <1>;
			compatible = "allwinner,sun6i-a31-clock-reset";
			reg = <0x060005a0 0x4>;
		};

		ahb1_resets: reset@060005a4 {
			#reset-cells = <1>;
			compatible = "allwinner,sun6i-a31-clock-reset";
			reg = <0x060005a4 0x4>;
		};

		ahb2_resets: reset@060005a8 {
			#reset-cells = <1>;
			compatible = "allwinner,sun6i-a31-clock-reset";
			reg = <0x060005a8 0x4>;
		};

		apb0_resets: reset@060005b0 {
			#reset-cells = <1>;
			compatible = "allwinner,sun6i-a31-clock-reset";
			reg = <0x060005b0 0x4>;
		};

		apb1_resets: reset@060005b4 {
			#reset-cells = <1>;
			compatible = "allwinner,sun6i-a31-clock-reset";
			reg = <0x060005b4 0x4>;
		};

		timer@06000c00 {
			compatible = "allwinner,sun4i-a10-timer";
			reg = <0x06000c00 0xa0>;
			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&osc24M>;
		};

		pio: pinctrl@06000800 {
			compatible = "allwinner,sun9i-a80-pinctrl";
			reg = <0x06000800 0x400>;
			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&apb0_gates 5>;
			gpio-controller;
			interrupt-controller;
			#interrupt-cells = <2>;
			#size-cells = <0>;
			#gpio-cells = <3>;

			i2c3_pins_a: i2c3@0 {
				allwinner,pins = "PG10", "PG11";
				allwinner,function = "i2c3";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			uart0_pins_a: uart0@0 {
				allwinner,pins = "PH12", "PH13";
				allwinner,function = "uart0";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			uart4_pins_a: uart4@0 {
				allwinner,pins = "PG12", "PG13", "PG14", "PG15";
				allwinner,function = "uart4";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};
		};

		uart0: serial@07000000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x07000000 0x400>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 16>;
			resets = <&apb1_resets 16>;
			status = "disabled";
		};

		uart1: serial@07000400 {
			compatible = "snps,dw-apb-uart";
			reg = <0x07000400 0x400>;
			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 17>;
			resets = <&apb1_resets 17>;
			status = "disabled";
		};

		uart2: serial@07000800 {
			compatible = "snps,dw-apb-uart";
			reg = <0x07000800 0x400>;
			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 18>;
			resets = <&apb1_resets 18>;
			status = "disabled";
		};

		uart3: serial@07000c00 {
			compatible = "snps,dw-apb-uart";
			reg = <0x07000c00 0x400>;
			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 19>;
			resets = <&apb1_resets 19>;
			status = "disabled";
		};

		uart4: serial@07001000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x07001000 0x400>;
			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 20>;
			resets = <&apb1_resets 20>;
			status = "disabled";
		};

		uart5: serial@07001400 {
			compatible = "snps,dw-apb-uart";
			reg = <0x07001400 0x400>;
			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 21>;
			resets = <&apb1_resets 21>;
			status = "disabled";
		};

		i2c0: i2c@07002800 {
			compatible = "allwinner,sun6i-a31-i2c";
			reg = <0x07002800 0x400>;
			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&apb1_gates 0>;
			resets = <&apb1_resets 0>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c1: i2c@07002c00 {
			compatible = "allwinner,sun6i-a31-i2c";
			reg = <0x07002c00 0x400>;
			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&apb1_gates 1>;
			resets = <&apb1_resets 1>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c2: i2c@07003000 {
			compatible = "allwinner,sun6i-a31-i2c";
			reg = <0x07003000 0x400>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&apb1_gates 2>;
			resets = <&apb1_resets 2>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c3: i2c@07003400 {
			compatible = "allwinner,sun6i-a31-i2c";
			reg = <0x07003400 0x400>;
			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&apb1_gates 3>;
			resets = <&apb1_resets 3>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c4: i2c@07003800 {
			compatible = "allwinner,sun6i-a31-i2c";
			reg = <0x07003800 0x400>;
			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&apb1_gates 4>;
			resets = <&apb1_resets 4>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		r_wdt: watchdog@08001000 {
			compatible = "allwinner,sun6i-a31-wdt";
			reg = <0x08001000 0x20>;
			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
		};

		r_uart: serial@08002800 {
			compatible = "snps,dw-apb-uart";
			reg = <0x08002800 0x400>;
			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&osc24M>;
			status = "disabled";
		};
	};
};
Commit	Line	Data
4ab328f0 CYT	1	/*
	2	* Copyright 2014 Chen-Yu Tsai
	3	*
	4	* Chen-Yu Tsai <wens@csie.org>
	5	*
	6	* This file is dual-licensed: you can use it either under the terms
	7	* of the GPL or the X11 license, at your option. Note that this dual
	8	* licensing only applies to this file, and not this project as a
	9	* whole.
	10	*
136d18a8	11	* a) This file is free software; you can redistribute it and/or
4ab328f0 CYT	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of the
	14	* License, or (at your option) any later version.
	15	*
136d18a8	16	* This file is distributed in the hope that it will be useful,
4ab328f0 CYT	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public
136d18a8	22	* License along with this file; if not, write to the Free
4ab328f0 CYT	23	* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
	24	* MA 02110-1301 USA
	25	*
	26	* Or, alternatively,
	27	*
	28	* b) Permission is hereby granted, free of charge, to any person
	29	* obtaining a copy of this software and associated documentation
	30	* files (the "Software"), to deal in the Software without
	31	* restriction, including without limitation the rights to use,
	32	* copy, modify, merge, publish, distribute, sublicense, and/or
	33	* sell copies of the Software, and to permit persons to whom the
	34	* Software is furnished to do so, subject to the following
	35	* conditions:
	36	*
	37	* The above copyright notice and this permission notice shall be
	38	* included in all copies or substantial portions of the Software.
	39	*
	40	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	41	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	42	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	43	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	44	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	45	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	46	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	47	* OTHER DEALINGS IN THE SOFTWARE.
	48	*/
	49
71455701	50	#include "skeleton64.dtsi"
4ab328f0	51
19882b84 MR	52	#include <dt-bindings/interrupt-controller/arm-gic.h>
19882b84 MR	53
092a0c3b MR	54	#include <dt-bindings/pinctrl/sun4i-a10.h>
092a0c3b MR	55
4ab328f0 CYT	56	/ {
	57	interrupt-parent = <&gic>;
	58
	59	aliases {
	60	serial0 = &uart0;
	61	serial1 = &uart1;
	62	serial2 = &uart2;
	63	serial3 = &uart3;
	64	serial4 = &uart4;
	65	serial5 = &uart5;
	66	serial6 = &r_uart;
	67	};
	68
	69	cpus {
	70	#address-cells = <1>;
	71	#size-cells = <0>;
	72
	73	cpu0: cpu@0 {
	74	compatible = "arm,cortex-a7";
	75	device_type = "cpu";
	76	reg = <0x0>;
	77	};
	78
	79	cpu1: cpu@1 {
	80	compatible = "arm,cortex-a7";
	81	device_type = "cpu";
	82	reg = <0x1>;
	83	};
	84
	85	cpu2: cpu@2 {
	86	compatible = "arm,cortex-a7";
	87	device_type = "cpu";
	88	reg = <0x2>;
	89	};
	90
	91	cpu3: cpu@3 {
	92	compatible = "arm,cortex-a7";
	93	device_type = "cpu";
	94	reg = <0x3>;
	95	};
	96
	97	cpu4: cpu@100 {
	98	compatible = "arm,cortex-a15";
	99	device_type = "cpu";
	100	reg = <0x100>;
	101	};
	102
	103	cpu5: cpu@101 {
	104	compatible = "arm,cortex-a15";
	105	device_type = "cpu";
	106	reg = <0x101>;
	107	};
	108
	109	cpu6: cpu@102 {
	110	compatible = "arm,cortex-a15";
	111	device_type = "cpu";
	112	reg = <0x102>;
	113	};
	114
	115	cpu7: cpu@103 {
	116	compatible = "arm,cortex-a15";
	117	device_type = "cpu";
	118	reg = <0x103>;
	119	};
120	};
121
122	memory {
123	/* 8GB max. with LPAE */
124	reg = <0 0x20000000 0x02 0>;
125	};
126
127	clocks {
128	#address-cells = <1>;
129	#size-cells = <1>;
130	/*
131	* map 64 bit address range down to 32 bits,
132	* as the peripherals are all under 512MB.
133	*/
134	ranges = <0 0 0 0x20000000>;
135
136	osc24M: osc24M_clk {
137	#clock-cells = <0>;
138	compatible = "fixed-clock";
139	clock-frequency = <24000000>;
140	clock-output-names = "osc24M";
141	};
142
143	osc32k: osc32k_clk {
144	#clock-cells = <0>;
145	compatible = "fixed-clock";
146	clock-frequency = <32768>;
147	clock-output-names = "osc32k";
148	};
ac399a97 CYT	149
	150	pll4: clk@0600000c {
	151	#clock-cells = <0>;
	152	compatible = "allwinner,sun9i-a80-pll4-clk";
	153	reg = <0x0600000c 0x4>;
	154	clocks = <&osc24M>;
	155	clock-output-names = "pll4";
	156	};
	157
	158	pll12: clk@0600002c {
	159	#clock-cells = <0>;
	160	compatible = "allwinner,sun9i-a80-pll4-clk";
	161	reg = <0x0600002c 0x4>;
	162	clocks = <&osc24M>;
	163	clock-output-names = "pll12";
	164	};
	165
	166	gt_clk: clk@0600005c {
	167	#clock-cells = <0>;
	168	compatible = "allwinner,sun9i-a80-gt-clk";
	169	reg = <0x0600005c 0x4>;
	170	clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
	171	clock-output-names = "gt";
	172	};
	173
	174	ahb0: clk@06000060 {
	175	#clock-cells = <0>;
	176	compatible = "allwinner,sun9i-a80-ahb-clk";
	177	reg = <0x06000060 0x4>;
	178	clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
	179	clock-output-names = "ahb0";
	180	};
	181
	182	ahb1: clk@06000064 {
	183	#clock-cells = <0>;
	184	compatible = "allwinner,sun9i-a80-ahb-clk";
	185	reg = <0x06000064 0x4>;
	186	clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
	187	clock-output-names = "ahb1";
	188	};
	189
	190	ahb2: clk@06000068 {
	191	#clock-cells = <0>;
	192	compatible = "allwinner,sun9i-a80-ahb-clk";
	193	reg = <0x06000068 0x4>;
	194	clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
	195	clock-output-names = "ahb2";
	196	};
	197
	198	apb0: clk@06000070 {
	199	#clock-cells = <0>;
	200	compatible = "allwinner,sun9i-a80-apb0-clk";
	201	reg = <0x06000070 0x4>;
	202	clocks = <&osc24M>, <&pll4>;
	203	clock-output-names = "apb0";
	204	};
	205
	206	apb1: clk@06000074 {
	207	#clock-cells = <0>;
	208	compatible = "allwinner,sun9i-a80-apb1-clk";
	209	reg = <0x06000074 0x4>;
	210	clocks = <&osc24M>, <&pll4>;
	211	clock-output-names = "apb1";
	212	};
213
214	cci400_clk: clk@06000078 {
215	#clock-cells = <0>;
216	compatible = "allwinner,sun9i-a80-gt-clk";
217	reg = <0x06000078 0x4>;
218	clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
219	clock-output-names = "cci400";
220	};
221
d2aa6f54 CYT	222	mmc0_clk: clk@06000410 {
	223	#clock-cells = <1>;
	224	compatible = "allwinner,sun9i-a80-mmc-clk";
	225	reg = <0x06000410 0x4>;
	226	clocks = <&osc24M>, <&pll4>;
	227	clock-output-names = "mmc0", "mmc0_output",
	228	"mmc0_sample";
	229	};
	230
	231	mmc1_clk: clk@06000414 {
	232	#clock-cells = <1>;
	233	compatible = "allwinner,sun9i-a80-mmc-clk";
	234	reg = <0x06000414 0x4>;
	235	clocks = <&osc24M>, <&pll4>;
	236	clock-output-names = "mmc1", "mmc1_output",
	237	"mmc1_sample";
	238	};
	239
	240	mmc2_clk: clk@06000418 {
	241	#clock-cells = <1>;
	242	compatible = "allwinner,sun9i-a80-mmc-clk";
	243	reg = <0x06000418 0x4>;
	244	clocks = <&osc24M>, <&pll4>;
	245	clock-output-names = "mmc2", "mmc2_output",
	246	"mmc2_sample";
	247	};
	248
	249	mmc3_clk: clk@0600041c {
	250	#clock-cells = <1>;
	251	compatible = "allwinner,sun9i-a80-mmc-clk";
	252	reg = <0x0600041c 0x4>;
	253	clocks = <&osc24M>, <&pll4>;
	254	clock-output-names = "mmc3", "mmc3_output",
	255	"mmc3_sample";
	256	};
	257
ac399a97 CYT	258	ahb0_gates: clk@06000580 {
	259	#clock-cells = <1>;
	260	compatible = "allwinner,sun9i-a80-ahb0-gates-clk";
	261	reg = <0x06000580 0x4>;
	262	clocks = <&ahb0>;
203c6883 CYT	263	clock-indices = <0>, <1>, <3>, <5>, <8>, <12>, <13>,
	264	<14>, <15>, <16>, <18>, <20>, <21>,
	265	<22>, <23>;
ac399a97 CYT	266	clock-output-names = "ahb0_fd", "ahb0_ve", "ahb0_gpu",
	267	"ahb0_ss", "ahb0_sd", "ahb0_nand1",
	268	"ahb0_nand0", "ahb0_sdram",
	269	"ahb0_mipi_hsi", "ahb0_sata", "ahb0_ts",
	270	"ahb0_spi0","ahb0_spi1", "ahb0_spi2",
	271	"ahb0_spi3";
	272	};
	273
	274	ahb1_gates: clk@06000584 {
	275	#clock-cells = <1>;
	276	compatible = "allwinner,sun9i-a80-ahb1-gates-clk";
	277	reg = <0x06000584 0x4>;
	278	clocks = <&ahb1>;
203c6883	279	clock-indices = <0>, <1>, <17>, <21>, <22>, <23>, <24>;
ac399a97 CYT	280	clock-output-names = "ahb1_usbotg", "ahb1_usbhci",
	281	"ahb1_gmac", "ahb1_msgbox",
	282	"ahb1_spinlock", "ahb1_hstimer",
	283	"ahb1_dma";
	284	};
	285
	286	ahb2_gates: clk@06000588 {
	287	#clock-cells = <1>;
	288	compatible = "allwinner,sun9i-a80-ahb2-gates-clk";
	289	reg = <0x06000588 0x4>;
	290	clocks = <&ahb2>;
203c6883 CYT	291	clock-indices = <0>, <1>, <2>, <4>, <5>, <7>, <8>,
203c6883 CYT	292	<11>;
ac399a97 CYT	293	clock-output-names = "ahb2_lcd0", "ahb2_lcd1",
	294	"ahb2_edp", "ahb2_csi", "ahb2_hdmi",
	295	"ahb2_de", "ahb2_mp", "ahb2_mipi_dsi";
	296	};
	297
	298	apb0_gates: clk@06000590 {
	299	#clock-cells = <1>;
	300	compatible = "allwinner,sun9i-a80-apb0-gates-clk";
	301	reg = <0x06000590 0x4>;
	302	clocks = <&apb0>;
203c6883 CYT	303	clock-indices = <1>, <5>, <11>, <12>, <13>, <15>,
203c6883 CYT	304	<17>, <18>, <19>;
ac399a97 CYT	305	clock-output-names = "apb0_spdif", "apb0_pio",
	306	"apb0_ac97", "apb0_i2s0", "apb0_i2s1",
	307	"apb0_lradc", "apb0_gpadc", "apb0_twd",
	308	"apb0_cirtx";
	309	};
	310
	311	apb1_gates: clk@06000594 {
	312	#clock-cells = <1>;
	313	compatible = "allwinner,sun9i-a80-apb1-gates-clk";
	314	reg = <0x06000594 0x4>;
	315	clocks = <&apb1>;
203c6883 CYT	316	clock-indices = <0>, <1>, <2>, <3>, <4>,
203c6883 CYT	317	<16>, <17>, <18>, <19>, <20>, <21>;
ac399a97 CYT	318	clock-output-names = "apb1_i2c0", "apb1_i2c1",
	319	"apb1_i2c2", "apb1_i2c3", "apb1_i2c4",
	320	"apb1_uart0", "apb1_uart1",
	321	"apb1_uart2", "apb1_uart3",
	322	"apb1_uart4", "apb1_uart5";
	323	};
4ab328f0 CYT	324	};
	325
	326	soc {
	327	compatible = "simple-bus";
	328	#address-cells = <1>;
	329	#size-cells = <1>;
	330	/*
	331	* map 64 bit address range down to 32 bits,
	332	* as the peripherals are all under 512MB.
	333	*/
	334	ranges = <0 0 0 0x20000000>;
	335
	336	gic: interrupt-controller@01c41000 {
	337	compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
	338	reg = <0x01c41000 0x1000>,
	339	<0x01c42000 0x1000>,
	340	<0x01c44000 0x2000>,
	341	<0x01c46000 0x2000>;
	342	interrupt-controller;
	343	#interrupt-cells = <3>;
19882b84	344	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
4ab328f0 CYT	345	};
4ab328f0 CYT	346
ac399a97 CYT	347	ahb0_resets: reset@060005a0 {
	348	#reset-cells = <1>;
	349	compatible = "allwinner,sun6i-a31-clock-reset";
	350	reg = <0x060005a0 0x4>;
	351	};
	352
	353	ahb1_resets: reset@060005a4 {
	354	#reset-cells = <1>;
	355	compatible = "allwinner,sun6i-a31-clock-reset";
	356	reg = <0x060005a4 0x4>;
	357	};
	358
	359	ahb2_resets: reset@060005a8 {
	360	#reset-cells = <1>;
	361	compatible = "allwinner,sun6i-a31-clock-reset";
	362	reg = <0x060005a8 0x4>;
	363	};
	364
	365	apb0_resets: reset@060005b0 {
	366	#reset-cells = <1>;
	367	compatible = "allwinner,sun6i-a31-clock-reset";
	368	reg = <0x060005b0 0x4>;
	369	};
	370
	371	apb1_resets: reset@060005b4 {
	372	#reset-cells = <1>;
	373	compatible = "allwinner,sun6i-a31-clock-reset";
	374	reg = <0x060005b4 0x4>;
	375	};
	376
4ab328f0 CYT	377	timer@06000c00 {
	378	compatible = "allwinner,sun4i-a10-timer";
	379	reg = <0x06000c00 0xa0>;
19882b84 MR	380	interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
	381	<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
	382	<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
	383	<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
	384	<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
	385	<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
4ab328f0 CYT	386
	387	clocks = <&osc24M>;
	388	};
	389
43d024d3 MR	390	pio: pinctrl@06000800 {
	391	compatible = "allwinner,sun9i-a80-pinctrl";
	392	reg = <0x06000800 0x400>;
19882b84 MR	393	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
	394	<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
	395	<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
	396	<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
	397	<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
43d024d3 MR	398	clocks = <&apb0_gates 5>;
	399	gpio-controller;
	400	interrupt-controller;
	401	#interrupt-cells = <2>;
	402	#size-cells = <0>;
	403	#gpio-cells = <3>;
888366fa	404
6657a058 CYT	405	i2c3_pins_a: i2c3@0 {
	406	allwinner,pins = "PG10", "PG11";
	407	allwinner,function = "i2c3";
092a0c3b MR	408	allwinner,drive = <SUN4I_PINCTRL_10_MA>;
092a0c3b MR	409	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
6657a058 CYT	410	};
6657a058 CYT	411
888366fa MR	412	uart0_pins_a: uart0@0 {
	413	allwinner,pins = "PH12", "PH13";
	414	allwinner,function = "uart0";
092a0c3b MR	415	allwinner,drive = <SUN4I_PINCTRL_10_MA>;
092a0c3b MR	416	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
888366fa	417	};
2a950b2c CYT	418
	419	uart4_pins_a: uart4@0 {
	420	allwinner,pins = "PG12", "PG13", "PG14", "PG15";
	421	allwinner,function = "uart4";
092a0c3b MR	422	allwinner,drive = <SUN4I_PINCTRL_10_MA>;
092a0c3b MR	423	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
2a950b2c	424	};
43d024d3 MR	425	};
43d024d3 MR	426
4ab328f0 CYT	427	uart0: serial@07000000 {
	428	compatible = "snps,dw-apb-uart";
	429	reg = <0x07000000 0x400>;
19882b84	430	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
4ab328f0 CYT	431	reg-shift = <2>;
4ab328f0 CYT	432	reg-io-width = <4>;
ac399a97 CYT	433	clocks = <&apb1_gates 16>;
ac399a97 CYT	434	resets = <&apb1_resets 16>;
4ab328f0 CYT	435	status = "disabled";
	436	};
	437
	438	uart1: serial@07000400 {
	439	compatible = "snps,dw-apb-uart";
	440	reg = <0x07000400 0x400>;
19882b84	441	interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
4ab328f0 CYT	442	reg-shift = <2>;
4ab328f0 CYT	443	reg-io-width = <4>;
ac399a97 CYT	444	clocks = <&apb1_gates 17>;
ac399a97 CYT	445	resets = <&apb1_resets 17>;
4ab328f0 CYT	446	status = "disabled";
	447	};
	448
	449	uart2: serial@07000800 {
	450	compatible = "snps,dw-apb-uart";
	451	reg = <0x07000800 0x400>;
19882b84	452	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
4ab328f0 CYT	453	reg-shift = <2>;
4ab328f0 CYT	454	reg-io-width = <4>;
ac399a97 CYT	455	clocks = <&apb1_gates 18>;
ac399a97 CYT	456	resets = <&apb1_resets 18>;
4ab328f0 CYT	457	status = "disabled";
	458	};
	459
	460	uart3: serial@07000c00 {
	461	compatible = "snps,dw-apb-uart";
	462	reg = <0x07000c00 0x400>;
19882b84	463	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
4ab328f0 CYT	464	reg-shift = <2>;
4ab328f0 CYT	465	reg-io-width = <4>;
ac399a97 CYT	466	clocks = <&apb1_gates 19>;
ac399a97 CYT	467	resets = <&apb1_resets 19>;
4ab328f0 CYT	468	status = "disabled";
	469	};
	470
	471	uart4: serial@07001000 {
	472	compatible = "snps,dw-apb-uart";
	473	reg = <0x07001000 0x400>;
19882b84	474	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
4ab328f0 CYT	475	reg-shift = <2>;
4ab328f0 CYT	476	reg-io-width = <4>;
ac399a97 CYT	477	clocks = <&apb1_gates 20>;
ac399a97 CYT	478	resets = <&apb1_resets 20>;
4ab328f0 CYT	479	status = "disabled";
	480	};
	481
	482	uart5: serial@07001400 {
	483	compatible = "snps,dw-apb-uart";
	484	reg = <0x07001400 0x400>;
19882b84	485	interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4ab328f0 CYT	486	reg-shift = <2>;
4ab328f0 CYT	487	reg-io-width = <4>;
ac399a97 CYT	488	clocks = <&apb1_gates 21>;
ac399a97 CYT	489	resets = <&apb1_resets 21>;
4ab328f0 CYT	490	status = "disabled";
	491	};
	492
e4aa753a CYT	493	i2c0: i2c@07002800 {
	494	compatible = "allwinner,sun6i-a31-i2c";
	495	reg = <0x07002800 0x400>;
19882b84	496	interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
e4aa753a CYT	497	clocks = <&apb1_gates 0>;
	498	resets = <&apb1_resets 0>;
	499	status = "disabled";
	500	#address-cells = <1>;
	501	#size-cells = <0>;
	502	};
	503
	504	i2c1: i2c@07002c00 {
	505	compatible = "allwinner,sun6i-a31-i2c";
	506	reg = <0x07002c00 0x400>;
19882b84	507	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
e4aa753a CYT	508	clocks = <&apb1_gates 1>;
	509	resets = <&apb1_resets 1>;
	510	status = "disabled";
	511	#address-cells = <1>;
	512	#size-cells = <0>;
	513	};
	514
	515	i2c2: i2c@07003000 {
	516	compatible = "allwinner,sun6i-a31-i2c";
	517	reg = <0x07003000 0x400>;
19882b84	518	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
e4aa753a CYT	519	clocks = <&apb1_gates 2>;
	520	resets = <&apb1_resets 2>;
	521	status = "disabled";
	522	#address-cells = <1>;
	523	#size-cells = <0>;
	524	};
	525
	526	i2c3: i2c@07003400 {
	527	compatible = "allwinner,sun6i-a31-i2c";
	528	reg = <0x07003400 0x400>;
19882b84	529	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
e4aa753a CYT	530	clocks = <&apb1_gates 3>;
	531	resets = <&apb1_resets 3>;
	532	status = "disabled";
	533	#address-cells = <1>;
	534	#size-cells = <0>;
	535	};
	536
	537	i2c4: i2c@07003800 {
	538	compatible = "allwinner,sun6i-a31-i2c";
	539	reg = <0x07003800 0x400>;
19882b84	540	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
e4aa753a CYT	541	clocks = <&apb1_gates 4>;
	542	resets = <&apb1_resets 4>;
	543	status = "disabled";
	544	#address-cells = <1>;
	545	#size-cells = <0>;
	546	};
	547
4ab328f0 CYT	548	r_wdt: watchdog@08001000 {
	549	compatible = "allwinner,sun6i-a31-wdt";
	550	reg = <0x08001000 0x20>;
19882b84	551	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
4ab328f0 CYT	552	};
	553
	554	r_uart: serial@08002800 {
	555	compatible = "snps,dw-apb-uart";
	556	reg = <0x08002800 0x400>;
19882b84	557	interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
4ab328f0 CYT	558	reg-shift = <2>;
	559	reg-io-width = <4>;
	560	clocks = <&osc24M>;
	561	status = "disabled";
	562	};
	563	};
	564	};