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4ab328f0 CYT |
1 | /* |
2 | * Copyright 2014 Chen-Yu Tsai | |
3 | * | |
4 | * Chen-Yu Tsai <wens@csie.org> | |
5 | * | |
6 | * This file is dual-licensed: you can use it either under the terms | |
7 | * of the GPL or the X11 license, at your option. Note that this dual | |
8 | * licensing only applies to this file, and not this project as a | |
9 | * whole. | |
10 | * | |
136d18a8 | 11 | * a) This file is free software; you can redistribute it and/or |
4ab328f0 CYT |
12 | * modify it under the terms of the GNU General Public License as |
13 | * published by the Free Software Foundation; either version 2 of the | |
14 | * License, or (at your option) any later version. | |
15 | * | |
136d18a8 | 16 | * This file is distributed in the hope that it will be useful, |
4ab328f0 CYT |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public | |
136d18a8 | 22 | * License along with this file; if not, write to the Free |
4ab328f0 CYT |
23 | * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, |
24 | * MA 02110-1301 USA | |
25 | * | |
26 | * Or, alternatively, | |
27 | * | |
28 | * b) Permission is hereby granted, free of charge, to any person | |
29 | * obtaining a copy of this software and associated documentation | |
30 | * files (the "Software"), to deal in the Software without | |
31 | * restriction, including without limitation the rights to use, | |
32 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
33 | * sell copies of the Software, and to permit persons to whom the | |
34 | * Software is furnished to do so, subject to the following | |
35 | * conditions: | |
36 | * | |
37 | * The above copyright notice and this permission notice shall be | |
38 | * included in all copies or substantial portions of the Software. | |
39 | * | |
40 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
41 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
42 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
43 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
44 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
45 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
46 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
47 | * OTHER DEALINGS IN THE SOFTWARE. | |
48 | */ | |
49 | ||
71455701 | 50 | #include "skeleton64.dtsi" |
4ab328f0 | 51 | |
19882b84 MR |
52 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
53 | ||
092a0c3b | 54 | #include <dt-bindings/pinctrl/sun4i-a10.h> |
4ab328f0 CYT |
55 | |
56 | / { | |
57 | interrupt-parent = <&gic>; | |
58 | ||
4ab328f0 CYT |
59 | cpus { |
60 | #address-cells = <1>; | |
61 | #size-cells = <0>; | |
62 | ||
63 | cpu0: cpu@0 { | |
64 | compatible = "arm,cortex-a7"; | |
65 | device_type = "cpu"; | |
66 | reg = <0x0>; | |
67 | }; | |
68 | ||
69 | cpu1: cpu@1 { | |
70 | compatible = "arm,cortex-a7"; | |
71 | device_type = "cpu"; | |
72 | reg = <0x1>; | |
73 | }; | |
74 | ||
75 | cpu2: cpu@2 { | |
76 | compatible = "arm,cortex-a7"; | |
77 | device_type = "cpu"; | |
78 | reg = <0x2>; | |
79 | }; | |
80 | ||
81 | cpu3: cpu@3 { | |
82 | compatible = "arm,cortex-a7"; | |
83 | device_type = "cpu"; | |
84 | reg = <0x3>; | |
85 | }; | |
86 | ||
87 | cpu4: cpu@100 { | |
88 | compatible = "arm,cortex-a15"; | |
89 | device_type = "cpu"; | |
90 | reg = <0x100>; | |
91 | }; | |
92 | ||
93 | cpu5: cpu@101 { | |
94 | compatible = "arm,cortex-a15"; | |
95 | device_type = "cpu"; | |
96 | reg = <0x101>; | |
97 | }; | |
98 | ||
99 | cpu6: cpu@102 { | |
100 | compatible = "arm,cortex-a15"; | |
101 | device_type = "cpu"; | |
102 | reg = <0x102>; | |
103 | }; | |
104 | ||
105 | cpu7: cpu@103 { | |
106 | compatible = "arm,cortex-a15"; | |
107 | device_type = "cpu"; | |
108 | reg = <0x103>; | |
109 | }; | |
110 | }; | |
111 | ||
112 | memory { | |
113 | /* 8GB max. with LPAE */ | |
114 | reg = <0 0x20000000 0x02 0>; | |
115 | }; | |
116 | ||
117 | clocks { | |
118 | #address-cells = <1>; | |
119 | #size-cells = <1>; | |
120 | /* | |
121 | * map 64 bit address range down to 32 bits, | |
122 | * as the peripherals are all under 512MB. | |
123 | */ | |
124 | ranges = <0 0 0 0x20000000>; | |
125 | ||
126 | osc24M: osc24M_clk { | |
127 | #clock-cells = <0>; | |
128 | compatible = "fixed-clock"; | |
129 | clock-frequency = <24000000>; | |
130 | clock-output-names = "osc24M"; | |
131 | }; | |
132 | ||
133 | osc32k: osc32k_clk { | |
134 | #clock-cells = <0>; | |
135 | compatible = "fixed-clock"; | |
136 | clock-frequency = <32768>; | |
137 | clock-output-names = "osc32k"; | |
138 | }; | |
ac399a97 | 139 | |
bc8ffc2d CYT |
140 | usb_mod_clk: clk@00a08000 { |
141 | #clock-cells = <1>; | |
142 | #reset-cells = <1>; | |
143 | compatible = "allwinner,sun9i-a80-usb-mod-clk"; | |
144 | reg = <0x00a08000 0x4>; | |
145 | clocks = <&ahb1_gates 1>; | |
146 | clock-output-names = "usb0_ahb", "usb_ohci0", | |
147 | "usb1_ahb", "usb_ohci1", | |
148 | "usb2_ahb", "usb_ohci2"; | |
149 | }; | |
150 | ||
151 | usb_phy_clk: clk@00a08004 { | |
152 | #clock-cells = <1>; | |
153 | #reset-cells = <1>; | |
154 | compatible = "allwinner,sun9i-a80-usb-phy-clk"; | |
155 | reg = <0x00a08004 0x4>; | |
156 | clocks = <&ahb1_gates 1>; | |
157 | clock-output-names = "usb_phy0", "usb_hsic1_480M", | |
158 | "usb_phy1", "usb_hsic2_480M", | |
159 | "usb_phy2", "usb_hsic_12M"; | |
160 | }; | |
161 | ||
ac399a97 CYT |
162 | pll4: clk@0600000c { |
163 | #clock-cells = <0>; | |
164 | compatible = "allwinner,sun9i-a80-pll4-clk"; | |
165 | reg = <0x0600000c 0x4>; | |
166 | clocks = <&osc24M>; | |
167 | clock-output-names = "pll4"; | |
168 | }; | |
169 | ||
170 | pll12: clk@0600002c { | |
171 | #clock-cells = <0>; | |
172 | compatible = "allwinner,sun9i-a80-pll4-clk"; | |
173 | reg = <0x0600002c 0x4>; | |
174 | clocks = <&osc24M>; | |
175 | clock-output-names = "pll12"; | |
176 | }; | |
177 | ||
178 | gt_clk: clk@0600005c { | |
179 | #clock-cells = <0>; | |
180 | compatible = "allwinner,sun9i-a80-gt-clk"; | |
181 | reg = <0x0600005c 0x4>; | |
182 | clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>; | |
183 | clock-output-names = "gt"; | |
184 | }; | |
185 | ||
186 | ahb0: clk@06000060 { | |
187 | #clock-cells = <0>; | |
188 | compatible = "allwinner,sun9i-a80-ahb-clk"; | |
189 | reg = <0x06000060 0x4>; | |
190 | clocks = <>_clk>, <&pll4>, <&pll12>, <&pll12>; | |
191 | clock-output-names = "ahb0"; | |
192 | }; | |
193 | ||
194 | ahb1: clk@06000064 { | |
195 | #clock-cells = <0>; | |
196 | compatible = "allwinner,sun9i-a80-ahb-clk"; | |
197 | reg = <0x06000064 0x4>; | |
198 | clocks = <>_clk>, <&pll4>, <&pll12>, <&pll12>; | |
199 | clock-output-names = "ahb1"; | |
200 | }; | |
201 | ||
202 | ahb2: clk@06000068 { | |
203 | #clock-cells = <0>; | |
204 | compatible = "allwinner,sun9i-a80-ahb-clk"; | |
205 | reg = <0x06000068 0x4>; | |
206 | clocks = <>_clk>, <&pll4>, <&pll12>, <&pll12>; | |
207 | clock-output-names = "ahb2"; | |
208 | }; | |
209 | ||
210 | apb0: clk@06000070 { | |
211 | #clock-cells = <0>; | |
212 | compatible = "allwinner,sun9i-a80-apb0-clk"; | |
213 | reg = <0x06000070 0x4>; | |
214 | clocks = <&osc24M>, <&pll4>; | |
215 | clock-output-names = "apb0"; | |
216 | }; | |
217 | ||
218 | apb1: clk@06000074 { | |
219 | #clock-cells = <0>; | |
220 | compatible = "allwinner,sun9i-a80-apb1-clk"; | |
221 | reg = <0x06000074 0x4>; | |
222 | clocks = <&osc24M>, <&pll4>; | |
223 | clock-output-names = "apb1"; | |
224 | }; | |
225 | ||
226 | cci400_clk: clk@06000078 { | |
227 | #clock-cells = <0>; | |
228 | compatible = "allwinner,sun9i-a80-gt-clk"; | |
229 | reg = <0x06000078 0x4>; | |
230 | clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>; | |
231 | clock-output-names = "cci400"; | |
232 | }; | |
233 | ||
d2aa6f54 CYT |
234 | mmc0_clk: clk@06000410 { |
235 | #clock-cells = <1>; | |
236 | compatible = "allwinner,sun9i-a80-mmc-clk"; | |
237 | reg = <0x06000410 0x4>; | |
238 | clocks = <&osc24M>, <&pll4>; | |
239 | clock-output-names = "mmc0", "mmc0_output", | |
240 | "mmc0_sample"; | |
241 | }; | |
242 | ||
243 | mmc1_clk: clk@06000414 { | |
244 | #clock-cells = <1>; | |
245 | compatible = "allwinner,sun9i-a80-mmc-clk"; | |
246 | reg = <0x06000414 0x4>; | |
247 | clocks = <&osc24M>, <&pll4>; | |
248 | clock-output-names = "mmc1", "mmc1_output", | |
249 | "mmc1_sample"; | |
250 | }; | |
251 | ||
252 | mmc2_clk: clk@06000418 { | |
253 | #clock-cells = <1>; | |
254 | compatible = "allwinner,sun9i-a80-mmc-clk"; | |
255 | reg = <0x06000418 0x4>; | |
256 | clocks = <&osc24M>, <&pll4>; | |
257 | clock-output-names = "mmc2", "mmc2_output", | |
258 | "mmc2_sample"; | |
259 | }; | |
260 | ||
261 | mmc3_clk: clk@0600041c { | |
262 | #clock-cells = <1>; | |
263 | compatible = "allwinner,sun9i-a80-mmc-clk"; | |
264 | reg = <0x0600041c 0x4>; | |
265 | clocks = <&osc24M>, <&pll4>; | |
266 | clock-output-names = "mmc3", "mmc3_output", | |
267 | "mmc3_sample"; | |
268 | }; | |
269 | ||
ac399a97 CYT |
270 | ahb0_gates: clk@06000580 { |
271 | #clock-cells = <1>; | |
272 | compatible = "allwinner,sun9i-a80-ahb0-gates-clk"; | |
273 | reg = <0x06000580 0x4>; | |
274 | clocks = <&ahb0>; | |
203c6883 CYT |
275 | clock-indices = <0>, <1>, <3>, <5>, <8>, <12>, <13>, |
276 | <14>, <15>, <16>, <18>, <20>, <21>, | |
277 | <22>, <23>; | |
ac399a97 CYT |
278 | clock-output-names = "ahb0_fd", "ahb0_ve", "ahb0_gpu", |
279 | "ahb0_ss", "ahb0_sd", "ahb0_nand1", | |
280 | "ahb0_nand0", "ahb0_sdram", | |
281 | "ahb0_mipi_hsi", "ahb0_sata", "ahb0_ts", | |
282 | "ahb0_spi0","ahb0_spi1", "ahb0_spi2", | |
283 | "ahb0_spi3"; | |
284 | }; | |
285 | ||
286 | ahb1_gates: clk@06000584 { | |
287 | #clock-cells = <1>; | |
288 | compatible = "allwinner,sun9i-a80-ahb1-gates-clk"; | |
289 | reg = <0x06000584 0x4>; | |
290 | clocks = <&ahb1>; | |
203c6883 | 291 | clock-indices = <0>, <1>, <17>, <21>, <22>, <23>, <24>; |
ac399a97 CYT |
292 | clock-output-names = "ahb1_usbotg", "ahb1_usbhci", |
293 | "ahb1_gmac", "ahb1_msgbox", | |
294 | "ahb1_spinlock", "ahb1_hstimer", | |
295 | "ahb1_dma"; | |
296 | }; | |
297 | ||
298 | ahb2_gates: clk@06000588 { | |
299 | #clock-cells = <1>; | |
300 | compatible = "allwinner,sun9i-a80-ahb2-gates-clk"; | |
301 | reg = <0x06000588 0x4>; | |
302 | clocks = <&ahb2>; | |
203c6883 CYT |
303 | clock-indices = <0>, <1>, <2>, <4>, <5>, <7>, <8>, |
304 | <11>; | |
ac399a97 CYT |
305 | clock-output-names = "ahb2_lcd0", "ahb2_lcd1", |
306 | "ahb2_edp", "ahb2_csi", "ahb2_hdmi", | |
307 | "ahb2_de", "ahb2_mp", "ahb2_mipi_dsi"; | |
308 | }; | |
309 | ||
310 | apb0_gates: clk@06000590 { | |
311 | #clock-cells = <1>; | |
312 | compatible = "allwinner,sun9i-a80-apb0-gates-clk"; | |
313 | reg = <0x06000590 0x4>; | |
314 | clocks = <&apb0>; | |
203c6883 CYT |
315 | clock-indices = <1>, <5>, <11>, <12>, <13>, <15>, |
316 | <17>, <18>, <19>; | |
ac399a97 CYT |
317 | clock-output-names = "apb0_spdif", "apb0_pio", |
318 | "apb0_ac97", "apb0_i2s0", "apb0_i2s1", | |
319 | "apb0_lradc", "apb0_gpadc", "apb0_twd", | |
320 | "apb0_cirtx"; | |
321 | }; | |
322 | ||
323 | apb1_gates: clk@06000594 { | |
324 | #clock-cells = <1>; | |
325 | compatible = "allwinner,sun9i-a80-apb1-gates-clk"; | |
326 | reg = <0x06000594 0x4>; | |
327 | clocks = <&apb1>; | |
203c6883 CYT |
328 | clock-indices = <0>, <1>, <2>, <3>, <4>, |
329 | <16>, <17>, <18>, <19>, <20>, <21>; | |
ac399a97 CYT |
330 | clock-output-names = "apb1_i2c0", "apb1_i2c1", |
331 | "apb1_i2c2", "apb1_i2c3", "apb1_i2c4", | |
332 | "apb1_uart0", "apb1_uart1", | |
333 | "apb1_uart2", "apb1_uart3", | |
334 | "apb1_uart4", "apb1_uart5"; | |
335 | }; | |
4ab328f0 CYT |
336 | }; |
337 | ||
338 | soc { | |
339 | compatible = "simple-bus"; | |
340 | #address-cells = <1>; | |
341 | #size-cells = <1>; | |
342 | /* | |
343 | * map 64 bit address range down to 32 bits, | |
344 | * as the peripherals are all under 512MB. | |
345 | */ | |
346 | ranges = <0 0 0 0x20000000>; | |
347 | ||
70472163 CYT |
348 | ehci0: usb@00a00000 { |
349 | compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; | |
350 | reg = <0x00a00000 0x100>; | |
351 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; | |
352 | clocks = <&usb_mod_clk 1>; | |
353 | resets = <&usb_mod_clk 17>; | |
354 | phys = <&usbphy1>; | |
355 | phy-names = "usb"; | |
356 | status = "disabled"; | |
357 | }; | |
358 | ||
359 | ohci0: usb@00a00400 { | |
360 | compatible = "allwinner,sun9i-a80-ohci", "generic-ohci"; | |
361 | reg = <0x00a00400 0x100>; | |
362 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; | |
363 | clocks = <&usb_mod_clk 1>, <&usb_mod_clk 2>; | |
364 | resets = <&usb_mod_clk 17>; | |
365 | phys = <&usbphy1>; | |
366 | phy-names = "usb"; | |
367 | status = "disabled"; | |
368 | }; | |
369 | ||
1af5d192 CYT |
370 | usbphy1: phy@00a00800 { |
371 | compatible = "allwinner,sun9i-a80-usb-phy"; | |
372 | reg = <0x00a00800 0x4>; | |
373 | clocks = <&usb_phy_clk 1>; | |
374 | clock-names = "phy"; | |
375 | resets = <&usb_phy_clk 17>; | |
376 | reset-names = "phy"; | |
377 | status = "disabled"; | |
378 | #phy-cells = <0>; | |
379 | }; | |
380 | ||
70472163 CYT |
381 | ehci1: usb@00a01000 { |
382 | compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; | |
383 | reg = <0x00a01000 0x100>; | |
384 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; | |
385 | clocks = <&usb_mod_clk 3>; | |
386 | resets = <&usb_mod_clk 18>; | |
387 | phys = <&usbphy2>; | |
388 | phy-names = "usb"; | |
389 | status = "disabled"; | |
390 | }; | |
391 | ||
1af5d192 CYT |
392 | usbphy2: phy@00a01800 { |
393 | compatible = "allwinner,sun9i-a80-usb-phy"; | |
394 | reg = <0x00a01800 0x4>; | |
395 | clocks = <&usb_phy_clk 2>, <&usb_phy_clk 10>, | |
396 | <&usb_phy_clk 3>; | |
397 | clock-names = "hsic_480M", "hsic_12M", "phy"; | |
398 | resets = <&usb_phy_clk 18>, <&usb_phy_clk 19>; | |
399 | reset-names = "hsic", "phy"; | |
400 | status = "disabled"; | |
401 | #phy-cells = <0>; | |
402 | /* usb1 is always used with HSIC */ | |
403 | phy_type = "hsic"; | |
404 | }; | |
405 | ||
70472163 CYT |
406 | ehci2: usb@00a02000 { |
407 | compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; | |
408 | reg = <0x00a02000 0x100>; | |
409 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; | |
410 | clocks = <&usb_mod_clk 5>; | |
411 | resets = <&usb_mod_clk 19>; | |
412 | phys = <&usbphy3>; | |
413 | phy-names = "usb"; | |
414 | status = "disabled"; | |
415 | }; | |
416 | ||
417 | ohci2: usb@00a02400 { | |
418 | compatible = "allwinner,sun9i-a80-ohci", "generic-ohci"; | |
419 | reg = <0x00a02400 0x100>; | |
420 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; | |
421 | clocks = <&usb_mod_clk 5>, <&usb_mod_clk 6>; | |
422 | resets = <&usb_mod_clk 19>; | |
423 | phys = <&usbphy3>; | |
424 | phy-names = "usb"; | |
425 | status = "disabled"; | |
426 | }; | |
427 | ||
1af5d192 CYT |
428 | usbphy3: phy@00a02800 { |
429 | compatible = "allwinner,sun9i-a80-usb-phy"; | |
430 | reg = <0x00a02800 0x4>; | |
431 | clocks = <&usb_phy_clk 4>, <&usb_phy_clk 10>, | |
432 | <&usb_phy_clk 5>; | |
433 | clock-names = "hsic_480M", "hsic_12M", "phy"; | |
434 | resets = <&usb_phy_clk 20>, <&usb_phy_clk 21>; | |
435 | reset-names = "hsic", "phy"; | |
436 | status = "disabled"; | |
437 | #phy-cells = <0>; | |
438 | }; | |
439 | ||
2f6941cd CYT |
440 | mmc0: mmc@01c0f000 { |
441 | compatible = "allwinner,sun5i-a13-mmc"; | |
442 | reg = <0x01c0f000 0x1000>; | |
443 | clocks = <&mmc_config_clk 0>, <&mmc0_clk 0>, | |
444 | <&mmc0_clk 1>, <&mmc0_clk 2>; | |
445 | clock-names = "ahb", "mmc", "output", "sample"; | |
446 | resets = <&mmc_config_clk 0>; | |
447 | reset-names = "ahb"; | |
448 | interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; | |
449 | status = "disabled"; | |
450 | }; | |
451 | ||
452 | mmc1: mmc@01c10000 { | |
453 | compatible = "allwinner,sun5i-a13-mmc"; | |
454 | reg = <0x01c10000 0x1000>; | |
455 | clocks = <&mmc_config_clk 1>, <&mmc1_clk 0>, | |
456 | <&mmc1_clk 1>, <&mmc1_clk 2>; | |
457 | clock-names = "ahb", "mmc", "output", "sample"; | |
458 | resets = <&mmc_config_clk 1>; | |
459 | reset-names = "ahb"; | |
460 | interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; | |
461 | status = "disabled"; | |
462 | }; | |
463 | ||
464 | mmc2: mmc@01c11000 { | |
465 | compatible = "allwinner,sun5i-a13-mmc"; | |
466 | reg = <0x01c11000 0x1000>; | |
467 | clocks = <&mmc_config_clk 2>, <&mmc2_clk 0>, | |
468 | <&mmc2_clk 1>, <&mmc2_clk 2>; | |
469 | clock-names = "ahb", "mmc", "output", "sample"; | |
470 | resets = <&mmc_config_clk 2>; | |
471 | reset-names = "ahb"; | |
472 | interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; | |
473 | status = "disabled"; | |
474 | }; | |
475 | ||
476 | mmc3: mmc@01c12000 { | |
477 | compatible = "allwinner,sun5i-a13-mmc"; | |
478 | reg = <0x01c12000 0x1000>; | |
479 | clocks = <&mmc_config_clk 3>, <&mmc3_clk 0>, | |
480 | <&mmc3_clk 1>, <&mmc3_clk 2>; | |
481 | clock-names = "ahb", "mmc", "output", "sample"; | |
482 | resets = <&mmc_config_clk 3>; | |
483 | reset-names = "ahb"; | |
484 | interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; | |
485 | status = "disabled"; | |
486 | }; | |
487 | ||
9c56f3f3 CYT |
488 | mmc_config_clk: clk@01c13000 { |
489 | compatible = "allwinner,sun9i-a80-mmc-config-clk"; | |
490 | reg = <0x01c13000 0x10>; | |
491 | clocks = <&ahb0_gates 8>; | |
492 | clock-names = "ahb"; | |
493 | resets = <&ahb0_resets 8>; | |
494 | reset-names = "ahb"; | |
495 | #clock-cells = <1>; | |
496 | #reset-cells = <1>; | |
497 | clock-output-names = "mmc0_config", "mmc1_config", | |
498 | "mmc2_config", "mmc3_config"; | |
499 | }; | |
500 | ||
4ab328f0 CYT |
501 | gic: interrupt-controller@01c41000 { |
502 | compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; | |
503 | reg = <0x01c41000 0x1000>, | |
504 | <0x01c42000 0x1000>, | |
505 | <0x01c44000 0x2000>, | |
506 | <0x01c46000 0x2000>; | |
507 | interrupt-controller; | |
508 | #interrupt-cells = <3>; | |
19882b84 | 509 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
4ab328f0 CYT |
510 | }; |
511 | ||
ac399a97 CYT |
512 | ahb0_resets: reset@060005a0 { |
513 | #reset-cells = <1>; | |
514 | compatible = "allwinner,sun6i-a31-clock-reset"; | |
515 | reg = <0x060005a0 0x4>; | |
516 | }; | |
517 | ||
518 | ahb1_resets: reset@060005a4 { | |
519 | #reset-cells = <1>; | |
520 | compatible = "allwinner,sun6i-a31-clock-reset"; | |
521 | reg = <0x060005a4 0x4>; | |
522 | }; | |
523 | ||
524 | ahb2_resets: reset@060005a8 { | |
525 | #reset-cells = <1>; | |
526 | compatible = "allwinner,sun6i-a31-clock-reset"; | |
527 | reg = <0x060005a8 0x4>; | |
528 | }; | |
529 | ||
530 | apb0_resets: reset@060005b0 { | |
531 | #reset-cells = <1>; | |
532 | compatible = "allwinner,sun6i-a31-clock-reset"; | |
533 | reg = <0x060005b0 0x4>; | |
534 | }; | |
535 | ||
536 | apb1_resets: reset@060005b4 { | |
537 | #reset-cells = <1>; | |
538 | compatible = "allwinner,sun6i-a31-clock-reset"; | |
539 | reg = <0x060005b4 0x4>; | |
540 | }; | |
541 | ||
4ab328f0 CYT |
542 | timer@06000c00 { |
543 | compatible = "allwinner,sun4i-a10-timer"; | |
544 | reg = <0x06000c00 0xa0>; | |
19882b84 MR |
545 | interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, |
546 | <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, | |
547 | <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, | |
548 | <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, | |
549 | <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, | |
550 | <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | |
4ab328f0 CYT |
551 | |
552 | clocks = <&osc24M>; | |
553 | }; | |
554 | ||
43d024d3 MR |
555 | pio: pinctrl@06000800 { |
556 | compatible = "allwinner,sun9i-a80-pinctrl"; | |
557 | reg = <0x06000800 0x400>; | |
19882b84 MR |
558 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, |
559 | <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, | |
560 | <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, | |
561 | <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, | |
562 | <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; | |
43d024d3 MR |
563 | clocks = <&apb0_gates 5>; |
564 | gpio-controller; | |
565 | interrupt-controller; | |
566 | #interrupt-cells = <2>; | |
567 | #size-cells = <0>; | |
568 | #gpio-cells = <3>; | |
888366fa | 569 | |
6657a058 CYT |
570 | i2c3_pins_a: i2c3@0 { |
571 | allwinner,pins = "PG10", "PG11"; | |
572 | allwinner,function = "i2c3"; | |
092a0c3b MR |
573 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
574 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
6657a058 CYT |
575 | }; |
576 | ||
cd23e2e5 CYT |
577 | mmc0_pins: mmc0 { |
578 | allwinner,pins = "PF0", "PF1" ,"PF2", "PF3", | |
579 | "PF4", "PF5"; | |
580 | allwinner,function = "mmc0"; | |
581 | allwinner,drive = <SUN4I_PINCTRL_30_MA>; | |
582 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
583 | }; | |
584 | ||
23a602b6 CYT |
585 | mmc2_8bit_pins: mmc2_8bit { |
586 | allwinner,pins = "PC6", "PC7", "PC8", "PC9", | |
587 | "PC10", "PC11", "PC12", | |
588 | "PC13", "PC14", "PC15"; | |
589 | allwinner,function = "mmc2"; | |
590 | allwinner,drive = <SUN4I_PINCTRL_30_MA>; | |
591 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
6657a058 CYT |
592 | }; |
593 | ||
888366fa MR |
594 | uart0_pins_a: uart0@0 { |
595 | allwinner,pins = "PH12", "PH13"; | |
596 | allwinner,function = "uart0"; | |
092a0c3b MR |
597 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
598 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
888366fa | 599 | }; |
2a950b2c CYT |
600 | |
601 | uart4_pins_a: uart4@0 { | |
602 | allwinner,pins = "PG12", "PG13", "PG14", "PG15"; | |
603 | allwinner,function = "uart4"; | |
092a0c3b MR |
604 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
605 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
2a950b2c | 606 | }; |
43d024d3 MR |
607 | }; |
608 | ||
4ab328f0 CYT |
609 | uart0: serial@07000000 { |
610 | compatible = "snps,dw-apb-uart"; | |
611 | reg = <0x07000000 0x400>; | |
19882b84 | 612 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; |
4ab328f0 CYT |
613 | reg-shift = <2>; |
614 | reg-io-width = <4>; | |
ac399a97 CYT |
615 | clocks = <&apb1_gates 16>; |
616 | resets = <&apb1_resets 16>; | |
4ab328f0 CYT |
617 | status = "disabled"; |
618 | }; | |
619 | ||
620 | uart1: serial@07000400 { | |
621 | compatible = "snps,dw-apb-uart"; | |
622 | reg = <0x07000400 0x400>; | |
19882b84 | 623 | interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; |
4ab328f0 CYT |
624 | reg-shift = <2>; |
625 | reg-io-width = <4>; | |
ac399a97 CYT |
626 | clocks = <&apb1_gates 17>; |
627 | resets = <&apb1_resets 17>; | |
4ab328f0 CYT |
628 | status = "disabled"; |
629 | }; | |
630 | ||
631 | uart2: serial@07000800 { | |
632 | compatible = "snps,dw-apb-uart"; | |
633 | reg = <0x07000800 0x400>; | |
19882b84 | 634 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
4ab328f0 CYT |
635 | reg-shift = <2>; |
636 | reg-io-width = <4>; | |
ac399a97 CYT |
637 | clocks = <&apb1_gates 18>; |
638 | resets = <&apb1_resets 18>; | |
4ab328f0 CYT |
639 | status = "disabled"; |
640 | }; | |
641 | ||
642 | uart3: serial@07000c00 { | |
643 | compatible = "snps,dw-apb-uart"; | |
644 | reg = <0x07000c00 0x400>; | |
19882b84 | 645 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; |
4ab328f0 CYT |
646 | reg-shift = <2>; |
647 | reg-io-width = <4>; | |
ac399a97 CYT |
648 | clocks = <&apb1_gates 19>; |
649 | resets = <&apb1_resets 19>; | |
4ab328f0 CYT |
650 | status = "disabled"; |
651 | }; | |
652 | ||
653 | uart4: serial@07001000 { | |
654 | compatible = "snps,dw-apb-uart"; | |
655 | reg = <0x07001000 0x400>; | |
19882b84 | 656 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; |
4ab328f0 CYT |
657 | reg-shift = <2>; |
658 | reg-io-width = <4>; | |
ac399a97 CYT |
659 | clocks = <&apb1_gates 20>; |
660 | resets = <&apb1_resets 20>; | |
4ab328f0 CYT |
661 | status = "disabled"; |
662 | }; | |
663 | ||
664 | uart5: serial@07001400 { | |
665 | compatible = "snps,dw-apb-uart"; | |
666 | reg = <0x07001400 0x400>; | |
19882b84 | 667 | interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; |
4ab328f0 CYT |
668 | reg-shift = <2>; |
669 | reg-io-width = <4>; | |
ac399a97 CYT |
670 | clocks = <&apb1_gates 21>; |
671 | resets = <&apb1_resets 21>; | |
4ab328f0 CYT |
672 | status = "disabled"; |
673 | }; | |
674 | ||
e4aa753a CYT |
675 | i2c0: i2c@07002800 { |
676 | compatible = "allwinner,sun6i-a31-i2c"; | |
677 | reg = <0x07002800 0x400>; | |
19882b84 | 678 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
e4aa753a CYT |
679 | clocks = <&apb1_gates 0>; |
680 | resets = <&apb1_resets 0>; | |
681 | status = "disabled"; | |
682 | #address-cells = <1>; | |
683 | #size-cells = <0>; | |
684 | }; | |
685 | ||
686 | i2c1: i2c@07002c00 { | |
687 | compatible = "allwinner,sun6i-a31-i2c"; | |
688 | reg = <0x07002c00 0x400>; | |
19882b84 | 689 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
e4aa753a CYT |
690 | clocks = <&apb1_gates 1>; |
691 | resets = <&apb1_resets 1>; | |
692 | status = "disabled"; | |
693 | #address-cells = <1>; | |
694 | #size-cells = <0>; | |
695 | }; | |
696 | ||
697 | i2c2: i2c@07003000 { | |
698 | compatible = "allwinner,sun6i-a31-i2c"; | |
699 | reg = <0x07003000 0x400>; | |
19882b84 | 700 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; |
e4aa753a CYT |
701 | clocks = <&apb1_gates 2>; |
702 | resets = <&apb1_resets 2>; | |
703 | status = "disabled"; | |
704 | #address-cells = <1>; | |
705 | #size-cells = <0>; | |
706 | }; | |
707 | ||
708 | i2c3: i2c@07003400 { | |
709 | compatible = "allwinner,sun6i-a31-i2c"; | |
710 | reg = <0x07003400 0x400>; | |
19882b84 | 711 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
e4aa753a CYT |
712 | clocks = <&apb1_gates 3>; |
713 | resets = <&apb1_resets 3>; | |
714 | status = "disabled"; | |
715 | #address-cells = <1>; | |
716 | #size-cells = <0>; | |
717 | }; | |
718 | ||
719 | i2c4: i2c@07003800 { | |
720 | compatible = "allwinner,sun6i-a31-i2c"; | |
721 | reg = <0x07003800 0x400>; | |
19882b84 | 722 | interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
e4aa753a CYT |
723 | clocks = <&apb1_gates 4>; |
724 | resets = <&apb1_resets 4>; | |
725 | status = "disabled"; | |
726 | #address-cells = <1>; | |
727 | #size-cells = <0>; | |
728 | }; | |
729 | ||
4ab328f0 CYT |
730 | r_wdt: watchdog@08001000 { |
731 | compatible = "allwinner,sun6i-a31-wdt"; | |
732 | reg = <0x08001000 0x20>; | |
19882b84 | 733 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
4ab328f0 CYT |
734 | }; |
735 | ||
736 | r_uart: serial@08002800 { | |
737 | compatible = "snps,dw-apb-uart"; | |
738 | reg = <0x08002800 0x400>; | |
19882b84 | 739 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
4ab328f0 CYT |
740 | reg-shift = <2>; |
741 | reg-io-width = <4>; | |
742 | clocks = <&osc24M>; | |
743 | status = "disabled"; | |
744 | }; | |
745 | }; | |
746 | }; |