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Merge remote-tracking branches 'asoc/topic/da7213', 'asoc/topic/da732x', 'asoc/topic...
[deliverable/linux.git] / arch / arm / boot / dts / tegra114-dalmore.dts
CommitLineData
a71c03e7
HD		 1/dts-v1/;
2
e6e646e6 3#include <dt-bindings/input/input.h>
1bd0bd49 4#include "tegra114.dtsi"
a71c03e7
HD		 5
6/ {
7 model = "NVIDIA Tegra114 Dalmore evaluation board";
8 compatible = "nvidia,dalmore", "nvidia,tegra114";
9
553c0a20
SW		 10 aliases {
11 rtc0 = "/i2c@7000d000/tps65913@58";
12 rtc1 = "/rtc@7000e000";
13 };
14
a71c03e7
HD		 15 memory {
16 reg = <0x80000000 0x40000000>;
17 };
18
48b90117 19 host1x@50000000 {
f044d6fa
MP		 20 hdmi@54280000 {
21 status = "okay";
22
23 vdd-supply = <&vdd_hdmi_reg>;
24 pll-supply = <&palmas_smps3_reg>;
25
26 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
27 nvidia,hpd-gpio =
28 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
29 };
30
48b90117
TR		 31 dsi@54300000 {
32 status = "okay";
33
34 panel@0 {
35 compatible = "panasonic,vvx10f004b00",
36 "simple-panel";
37 reg = <0>;
38
39 power-supply = <&avdd_lcd_reg>;
40 backlight = <&backlight>;
41 };
42 };
43 };
44
58ecb23f 45 pinmux@70000868 {
2c314d5c
PR		 46 pinctrl-names = "default";
47 pinctrl-0 = <&state_default>;
48
49 state_default: pinmux {
50 clk1_out_pw4 {
51 nvidia,pins = "clk1_out_pw4";
52 nvidia,function = "extperiph1";
5fc6b0dd
LD		 53 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
54 nvidia,tristate = <TEGRA_PIN_DISABLE>;
55 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 56 };
57 dap1_din_pn1 {
58 nvidia,pins = "dap1_din_pn1";
59 nvidia,function = "i2s0";
5fc6b0dd
LD		 60 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
61 nvidia,tristate = <TEGRA_PIN_ENABLE>;
62 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 63 };
64 dap1_dout_pn2 {
65 nvidia,pins = "dap1_dout_pn2",
66 "dap1_fs_pn0",
67 "dap1_sclk_pn3";
68 nvidia,function = "i2s0";
5fc6b0dd
LD		 69 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
70 nvidia,tristate = <TEGRA_PIN_DISABLE>;
71 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 72 };
73 dap2_din_pa4 {
74 nvidia,pins = "dap2_din_pa4";
75 nvidia,function = "i2s1";
5fc6b0dd
LD		 76 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
77 nvidia,tristate = <TEGRA_PIN_ENABLE>;
78 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 79 };
80 dap2_dout_pa5 {
81 nvidia,pins = "dap2_dout_pa5",
82 "dap2_fs_pa2",
83 "dap2_sclk_pa3";
84 nvidia,function = "i2s1";
5fc6b0dd
LD		 85 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
86 nvidia,tristate = <TEGRA_PIN_DISABLE>;
87 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 88 };
89 dap4_din_pp5 {
90 nvidia,pins = "dap4_din_pp5",
91 "dap4_dout_pp6",
92 "dap4_fs_pp4",
93 "dap4_sclk_pp7";
94 nvidia,function = "i2s3";
5fc6b0dd
LD		 95 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
96 nvidia,tristate = <TEGRA_PIN_DISABLE>;
97 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 98 };
99 dvfs_pwm_px0 {
100 nvidia,pins = "dvfs_pwm_px0",
101 "dvfs_clk_px2";
102 nvidia,function = "cldvfs";
5fc6b0dd
LD		 103 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
104 nvidia,tristate = <TEGRA_PIN_DISABLE>;
105 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 106 };
107 ulpi_clk_py0 {
108 nvidia,pins = "ulpi_clk_py0",
109 "ulpi_data0_po1",
110 "ulpi_data1_po2",
111 "ulpi_data2_po3",
112 "ulpi_data3_po4",
113 "ulpi_data4_po5",
114 "ulpi_data5_po6",
115 "ulpi_data6_po7",
116 "ulpi_data7_po0";
117 nvidia,function = "ulpi";
5fc6b0dd
LD		 118 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
119 nvidia,tristate = <TEGRA_PIN_DISABLE>;
120 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 121 };
122 ulpi_dir_py1 {
123 nvidia,pins = "ulpi_dir_py1",
124 "ulpi_nxt_py2";
125 nvidia,function = "ulpi";
5fc6b0dd
LD		 126 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
127 nvidia,tristate = <TEGRA_PIN_ENABLE>;
128 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 129 };
130 ulpi_stp_py3 {
131 nvidia,pins = "ulpi_stp_py3";
132 nvidia,function = "ulpi";
5fc6b0dd
LD		 133 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
134 nvidia,tristate = <TEGRA_PIN_DISABLE>;
135 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 136 };
137 cam_i2c_scl_pbb1 {
138 nvidia,pins = "cam_i2c_scl_pbb1",
139 "cam_i2c_sda_pbb2";
140 nvidia,function = "i2c3";
5fc6b0dd
LD		 141 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
142 nvidia,tristate = <TEGRA_PIN_DISABLE>;
143 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
144 nvidia,lock = <TEGRA_PIN_DISABLE>;
145 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 146 };
147 cam_mclk_pcc0 {
148 nvidia,pins = "cam_mclk_pcc0",
149 "pbb0";
150 nvidia,function = "vi_alt3";
5fc6b0dd
LD		 151 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
152 nvidia,tristate = <TEGRA_PIN_DISABLE>;
153 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
154 nvidia,lock = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 155 };
156 gen2_i2c_scl_pt5 {
157 nvidia,pins = "gen2_i2c_scl_pt5",
158 "gen2_i2c_sda_pt6";
159 nvidia,function = "i2c2";
5fc6b0dd
LD		 160 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
161 nvidia,tristate = <TEGRA_PIN_DISABLE>;
162 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
163 nvidia,lock = <TEGRA_PIN_DISABLE>;
164 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 165 };
166 gmi_a16_pj7 {
167 nvidia,pins = "gmi_a16_pj7";
168 nvidia,function = "uartd";
5fc6b0dd
LD		 169 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
170 nvidia,tristate = <TEGRA_PIN_DISABLE>;
171 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 172 };
173 gmi_a17_pb0 {
174 nvidia,pins = "gmi_a17_pb0",
175 "gmi_a18_pb1";
176 nvidia,function = "uartd";
5fc6b0dd
LD		 177 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
178 nvidia,tristate = <TEGRA_PIN_ENABLE>;
179 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 180 };
181 gmi_a19_pk7 {
182 nvidia,pins = "gmi_a19_pk7";
183 nvidia,function = "uartd";
5fc6b0dd
LD		 184 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
185 nvidia,tristate = <TEGRA_PIN_DISABLE>;
186 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 187 };
188 gmi_ad5_pg5 {
189 nvidia,pins = "gmi_ad5_pg5",
190 "gmi_cs6_n_pi3",
191 "gmi_wr_n_pi0";
192 nvidia,function = "spi4";
5fc6b0dd
LD		 193 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
194 nvidia,tristate = <TEGRA_PIN_DISABLE>;
195 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 196 };
197 gmi_ad6_pg6 {
198 nvidia,pins = "gmi_ad6_pg6",
199 "gmi_ad7_pg7";
200 nvidia,function = "spi4";
5fc6b0dd
LD		 201 nvidia,pull = <TEGRA_PIN_PULL_UP>;
202 nvidia,tristate = <TEGRA_PIN_DISABLE>;
203 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 204 };
205 gmi_ad12_ph4 {
206 nvidia,pins = "gmi_ad12_ph4";
207 nvidia,function = "rsvd4";
5fc6b0dd
LD		 208 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
209 nvidia,tristate = <TEGRA_PIN_DISABLE>;
210 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 211 };
212 gmi_ad9_ph1 {
213 nvidia,pins = "gmi_ad9_ph1";
214 nvidia,function = "pwm1";
5fc6b0dd
LD		 215 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
216 nvidia,tristate = <TEGRA_PIN_DISABLE>;
217 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 218 };
219 gmi_cs1_n_pj2 {
220 nvidia,pins = "gmi_cs1_n_pj2",
221 "gmi_oe_n_pi1";
222 nvidia,function = "soc";
5fc6b0dd
LD		 223 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
224 nvidia,tristate = <TEGRA_PIN_ENABLE>;
225 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 226 };
227 clk2_out_pw5 {
228 nvidia,pins = "clk2_out_pw5";
229 nvidia,function = "extperiph2";
5fc6b0dd
LD		 230 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
231 nvidia,tristate = <TEGRA_PIN_DISABLE>;
232 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 233 };
234 sdmmc1_clk_pz0 {
235 nvidia,pins = "sdmmc1_clk_pz0";
236 nvidia,function = "sdmmc1";
5fc6b0dd
LD		 237 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
238 nvidia,tristate = <TEGRA_PIN_DISABLE>;
239 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 240 };
241 sdmmc1_cmd_pz1 {
242 nvidia,pins = "sdmmc1_cmd_pz1",
243 "sdmmc1_dat0_py7",
244 "sdmmc1_dat1_py6",
245 "sdmmc1_dat2_py5",
246 "sdmmc1_dat3_py4";
247 nvidia,function = "sdmmc1";
5fc6b0dd
LD		 248 nvidia,pull = <TEGRA_PIN_PULL_UP>;
249 nvidia,tristate = <TEGRA_PIN_DISABLE>;
250 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 251 };
252 sdmmc1_wp_n_pv3 {
253 nvidia,pins = "sdmmc1_wp_n_pv3";
254 nvidia,function = "spi4";
5fc6b0dd
LD		 255 nvidia,pull = <TEGRA_PIN_PULL_UP>;
256 nvidia,tristate = <TEGRA_PIN_DISABLE>;
257 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 258 };
259 sdmmc3_clk_pa6 {
260 nvidia,pins = "sdmmc3_clk_pa6";
261 nvidia,function = "sdmmc3";
5fc6b0dd
LD		 262 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
263 nvidia,tristate = <TEGRA_PIN_DISABLE>;
264 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 265 };
266 sdmmc3_cmd_pa7 {
267 nvidia,pins = "sdmmc3_cmd_pa7",
268 "sdmmc3_dat0_pb7",
269 "sdmmc3_dat1_pb6",
270 "sdmmc3_dat2_pb5",
271 "sdmmc3_dat3_pb4",
272 "kb_col4_pq4",
273 "sdmmc3_clk_lb_out_pee4",
274 "sdmmc3_clk_lb_in_pee5";
275 nvidia,function = "sdmmc3";
5fc6b0dd
LD		 276 nvidia,pull = <TEGRA_PIN_PULL_UP>;
277 nvidia,tristate = <TEGRA_PIN_DISABLE>;
278 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 279 };
280 sdmmc4_clk_pcc4 {
281 nvidia,pins = "sdmmc4_clk_pcc4";
282 nvidia,function = "sdmmc4";
5fc6b0dd
LD		 283 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
284 nvidia,tristate = <TEGRA_PIN_DISABLE>;
285 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 286 };
287 sdmmc4_cmd_pt7 {
288 nvidia,pins = "sdmmc4_cmd_pt7",
289 "sdmmc4_dat0_paa0",
290 "sdmmc4_dat1_paa1",
291 "sdmmc4_dat2_paa2",
292 "sdmmc4_dat3_paa3",
293 "sdmmc4_dat4_paa4",
294 "sdmmc4_dat5_paa5",
295 "sdmmc4_dat6_paa6",
296 "sdmmc4_dat7_paa7";
297 nvidia,function = "sdmmc4";
5fc6b0dd
LD		 298 nvidia,pull = <TEGRA_PIN_PULL_UP>;
299 nvidia,tristate = <TEGRA_PIN_DISABLE>;
300 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 301 };
302 clk_32k_out_pa0 {
303 nvidia,pins = "clk_32k_out_pa0";
304 nvidia,function = "blink";
5fc6b0dd
LD		 305 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
306 nvidia,tristate = <TEGRA_PIN_DISABLE>;
307 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 308 };
309 kb_col0_pq0 {
310 nvidia,pins = "kb_col0_pq0",
311 "kb_col1_pq1",
312 "kb_col2_pq2",
313 "kb_row0_pr0",
314 "kb_row1_pr1",
315 "kb_row2_pr2";
316 nvidia,function = "kbc";
5fc6b0dd
LD		 317 nvidia,pull = <TEGRA_PIN_PULL_UP>;
318 nvidia,tristate = <TEGRA_PIN_DISABLE>;
319 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 320 };
321 dap3_din_pp1 {
322 nvidia,pins = "dap3_din_pp1",
323 "dap3_sclk_pp3";
324 nvidia,function = "displayb";
5fc6b0dd
LD		 325 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
326 nvidia,tristate = <TEGRA_PIN_ENABLE>;
327 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 328 };
329 pv0 {
330 nvidia,pins = "pv0";
331 nvidia,function = "rsvd4";
5fc6b0dd
LD		 332 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
333 nvidia,tristate = <TEGRA_PIN_ENABLE>;
334 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 335 };
336 kb_row7_pr7 {
337 nvidia,pins = "kb_row7_pr7";
338 nvidia,function = "rsvd2";
5fc6b0dd
LD		 339 nvidia,pull = <TEGRA_PIN_PULL_UP>;
340 nvidia,tristate = <TEGRA_PIN_DISABLE>;
341 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 342 };
343 kb_row10_ps2 {
344 nvidia,pins = "kb_row10_ps2";
345 nvidia,function = "uarta";
5fc6b0dd
LD		 346 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
347 nvidia,tristate = <TEGRA_PIN_ENABLE>;
348 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 349 };
350 kb_row9_ps1 {
351 nvidia,pins = "kb_row9_ps1";
352 nvidia,function = "uarta";
5fc6b0dd
LD		 353 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
354 nvidia,tristate = <TEGRA_PIN_DISABLE>;
355 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 356 };
357 pwr_i2c_scl_pz6 {
358 nvidia,pins = "pwr_i2c_scl_pz6",
359 "pwr_i2c_sda_pz7";
360 nvidia,function = "i2cpwr";
5fc6b0dd
LD		 361 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
362 nvidia,tristate = <TEGRA_PIN_DISABLE>;
363 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
364 nvidia,lock = <TEGRA_PIN_DISABLE>;
365 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 366 };
367 sys_clk_req_pz5 {
368 nvidia,pins = "sys_clk_req_pz5";
369 nvidia,function = "sysclk";
5fc6b0dd
LD		 370 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
371 nvidia,tristate = <TEGRA_PIN_DISABLE>;
372 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 373 };
374 core_pwr_req {
375 nvidia,pins = "core_pwr_req";
376 nvidia,function = "pwron";
5fc6b0dd
LD		 377 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
378 nvidia,tristate = <TEGRA_PIN_DISABLE>;
379 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 380 };
381 cpu_pwr_req {
382 nvidia,pins = "cpu_pwr_req";
383 nvidia,function = "cpu";
5fc6b0dd
LD		 384 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
385 nvidia,tristate = <TEGRA_PIN_DISABLE>;
386 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 387 };
388 pwr_int_n {
389 nvidia,pins = "pwr_int_n";
390 nvidia,function = "pmi";
5fc6b0dd
LD		 391 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
392 nvidia,tristate = <TEGRA_PIN_ENABLE>;
393 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 394 };
395 reset_out_n {
396 nvidia,pins = "reset_out_n";
397 nvidia,function = "reset_out_n";
5fc6b0dd
LD		 398 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
399 nvidia,tristate = <TEGRA_PIN_DISABLE>;
400 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 401 };
402 clk3_out_pee0 {
403 nvidia,pins = "clk3_out_pee0";
404 nvidia,function = "extperiph3";
5fc6b0dd
LD		 405 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
406 nvidia,tristate = <TEGRA_PIN_DISABLE>;
407 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 408 };
409 gen1_i2c_scl_pc4 {
410 nvidia,pins = "gen1_i2c_scl_pc4",
411 "gen1_i2c_sda_pc5";
412 nvidia,function = "i2c1";
5fc6b0dd
LD		 413 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
414 nvidia,tristate = <TEGRA_PIN_DISABLE>;
415 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
416 nvidia,lock = <TEGRA_PIN_DISABLE>;
417 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 418 };
419 uart2_cts_n_pj5 {
420 nvidia,pins = "uart2_cts_n_pj5";
421 nvidia,function = "uartb";
5fc6b0dd
LD		 422 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
423 nvidia,tristate = <TEGRA_PIN_ENABLE>;
424 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 425 };
426 uart2_rts_n_pj6 {
427 nvidia,pins = "uart2_rts_n_pj6";
428 nvidia,function = "uartb";
5fc6b0dd
LD		 429 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
430 nvidia,tristate = <TEGRA_PIN_DISABLE>;
431 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 432 };
433 uart2_rxd_pc3 {
434 nvidia,pins = "uart2_rxd_pc3";
435 nvidia,function = "irda";
5fc6b0dd
LD		 436 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
437 nvidia,tristate = <TEGRA_PIN_ENABLE>;
438 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 439 };
440 uart2_txd_pc2 {
441 nvidia,pins = "uart2_txd_pc2";
442 nvidia,function = "irda";
5fc6b0dd
LD		 443 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
444 nvidia,tristate = <TEGRA_PIN_DISABLE>;
445 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 446 };
447 uart3_cts_n_pa1 {
448 nvidia,pins = "uart3_cts_n_pa1",
449 "uart3_rxd_pw7";
450 nvidia,function = "uartc";
5fc6b0dd
LD		 451 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
452 nvidia,tristate = <TEGRA_PIN_ENABLE>;
453 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 454 };
455 uart3_rts_n_pc0 {
456 nvidia,pins = "uart3_rts_n_pc0",
457 "uart3_txd_pw6";
458 nvidia,function = "uartc";
5fc6b0dd
LD		 459 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
460 nvidia,tristate = <TEGRA_PIN_DISABLE>;
461 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 462 };
463 owr {
464 nvidia,pins = "owr";
465 nvidia,function = "owr";
5fc6b0dd
LD		 466 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
467 nvidia,tristate = <TEGRA_PIN_DISABLE>;
468 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 469 };
470 hdmi_cec_pee3 {
471 nvidia,pins = "hdmi_cec_pee3";
472 nvidia,function = "cec";
5fc6b0dd
LD		 473 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
474 nvidia,tristate = <TEGRA_PIN_DISABLE>;
475 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
476 nvidia,lock = <TEGRA_PIN_DISABLE>;
477 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 478 };
479 ddc_scl_pv4 {
480 nvidia,pins = "ddc_scl_pv4",
481 "ddc_sda_pv5";
482 nvidia,function = "i2c4";
5fc6b0dd
LD		 483 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
484 nvidia,tristate = <TEGRA_PIN_DISABLE>;
485 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
486 nvidia,lock = <TEGRA_PIN_DISABLE>;
487 nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 488 };
489 spdif_in_pk6 {
490 nvidia,pins = "spdif_in_pk6";
491 nvidia,function = "usb";
5fc6b0dd
LD		 492 nvidia,pull = <TEGRA_PIN_PULL_UP>;
493 nvidia,tristate = <TEGRA_PIN_DISABLE>;
494 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
495 nvidia,lock = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 496 };
497 usb_vbus_en0_pn4 {
498 nvidia,pins = "usb_vbus_en0_pn4";
499 nvidia,function = "usb";
5fc6b0dd
LD		 500 nvidia,pull = <TEGRA_PIN_PULL_UP>;
501 nvidia,tristate = <TEGRA_PIN_DISABLE>;
502 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
503 nvidia,lock = <TEGRA_PIN_DISABLE>;
504 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 505 };
506 gpio_x6_aud_px6 {
507 nvidia,pins = "gpio_x6_aud_px6";
508 nvidia,function = "spi6";
5fc6b0dd
LD		 509 nvidia,pull = <TEGRA_PIN_PULL_UP>;
510 nvidia,tristate = <TEGRA_PIN_ENABLE>;
511 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 512 };
513 gpio_x4_aud_px4 {
514 nvidia,pins = "gpio_x4_aud_px4",
515 "gpio_x7_aud_px7";
516 nvidia,function = "rsvd1";
5fc6b0dd
LD		 517 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
518 nvidia,tristate = <TEGRA_PIN_DISABLE>;
519 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 520 };
521 gpio_x5_aud_px5 {
522 nvidia,pins = "gpio_x5_aud_px5";
523 nvidia,function = "rsvd1";
5fc6b0dd
LD		 524 nvidia,pull = <TEGRA_PIN_PULL_UP>;
525 nvidia,tristate = <TEGRA_PIN_DISABLE>;
526 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 527 };
528 gpio_w2_aud_pw2 {
529 nvidia,pins = "gpio_w2_aud_pw2";
530 nvidia,function = "rsvd2";
5fc6b0dd
LD		 531 nvidia,pull = <TEGRA_PIN_PULL_UP>;
532 nvidia,tristate = <TEGRA_PIN_DISABLE>;
533 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 534 };
535 gpio_w3_aud_pw3 {
536 nvidia,pins = "gpio_w3_aud_pw3";
537 nvidia,function = "spi6";
5fc6b0dd
LD		 538 nvidia,pull = <TEGRA_PIN_PULL_UP>;
539 nvidia,tristate = <TEGRA_PIN_DISABLE>;
540 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 541 };
542 gpio_x1_aud_px1 {
543 nvidia,pins = "gpio_x1_aud_px1";
544 nvidia,function = "rsvd4";
5fc6b0dd
LD		 545 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
546 nvidia,tristate = <TEGRA_PIN_DISABLE>;
547 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 548 };
549 gpio_x3_aud_px3 {
550 nvidia,pins = "gpio_x3_aud_px3";
551 nvidia,function = "rsvd4";
5fc6b0dd
LD		 552 nvidia,pull = <TEGRA_PIN_PULL_UP>;
553 nvidia,tristate = <TEGRA_PIN_DISABLE>;
554 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 555 };
556 dap3_fs_pp0 {
557 nvidia,pins = "dap3_fs_pp0";
558 nvidia,function = "i2s2";
5fc6b0dd
LD		 559 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
560 nvidia,tristate = <TEGRA_PIN_DISABLE>;
561 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 562 };
563 dap3_dout_pp2 {
564 nvidia,pins = "dap3_dout_pp2";
565 nvidia,function = "i2s2";
5fc6b0dd
LD		 566 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
567 nvidia,tristate = <TEGRA_PIN_DISABLE>;
568 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 569 };
570 pv1 {
571 nvidia,pins = "pv1";
572 nvidia,function = "rsvd1";
5fc6b0dd
LD		 573 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
574 nvidia,tristate = <TEGRA_PIN_DISABLE>;
575 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 576 };
577 pbb3 {
578 nvidia,pins = "pbb3",
579 "pbb5",
580 "pbb6",
581 "pbb7";
582 nvidia,function = "rsvd4";
5fc6b0dd
LD		 583 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
584 nvidia,tristate = <TEGRA_PIN_DISABLE>;
585 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 586 };
587 pcc1 {
588 nvidia,pins = "pcc1",
589 "pcc2";
590 nvidia,function = "rsvd4";
5fc6b0dd
LD		 591 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
592 nvidia,tristate = <TEGRA_PIN_DISABLE>;
593 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 594 };
595 gmi_ad0_pg0 {
596 nvidia,pins = "gmi_ad0_pg0",
597 "gmi_ad1_pg1";
598 nvidia,function = "gmi";
5fc6b0dd
LD		 599 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
600 nvidia,tristate = <TEGRA_PIN_DISABLE>;
601 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 602 };
603 gmi_ad10_ph2 {
604 nvidia,pins = "gmi_ad10_ph2",
605 "gmi_ad11_ph3",
606 "gmi_ad13_ph5",
607 "gmi_ad8_ph0",
608 "gmi_clk_pk1";
609 nvidia,function = "gmi";
5fc6b0dd
LD		 610 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
611 nvidia,tristate = <TEGRA_PIN_DISABLE>;
612 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 613 };
614 gmi_ad2_pg2 {
615 nvidia,pins = "gmi_ad2_pg2",
616 "gmi_ad3_pg3";
617 nvidia,function = "gmi";
5fc6b0dd
LD		 618 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
619 nvidia,tristate = <TEGRA_PIN_DISABLE>;
620 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 621 };
622 gmi_adv_n_pk0 {
623 nvidia,pins = "gmi_adv_n_pk0",
624 "gmi_cs0_n_pj0",
625 "gmi_cs2_n_pk3",
626 "gmi_cs4_n_pk2",
627 "gmi_cs7_n_pi6",
628 "gmi_dqs_p_pj3",
629 "gmi_iordy_pi5",
630 "gmi_wp_n_pc7";
631 nvidia,function = "gmi";
5fc6b0dd
LD		 632 nvidia,pull = <TEGRA_PIN_PULL_UP>;
633 nvidia,tristate = <TEGRA_PIN_DISABLE>;
634 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 635 };
636 gmi_cs3_n_pk4 {
637 nvidia,pins = "gmi_cs3_n_pk4";
638 nvidia,function = "gmi";
5fc6b0dd
LD		 639 nvidia,pull = <TEGRA_PIN_PULL_UP>;
640 nvidia,tristate = <TEGRA_PIN_DISABLE>;
641 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 642 };
643 clk2_req_pcc5 {
644 nvidia,pins = "clk2_req_pcc5";
645 nvidia,function = "rsvd4";
5fc6b0dd
LD		 646 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
647 nvidia,tristate = <TEGRA_PIN_DISABLE>;
648 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 649 };
650 kb_col3_pq3 {
651 nvidia,pins = "kb_col3_pq3",
652 "kb_col6_pq6",
653 "kb_col7_pq7";
654 nvidia,function = "kbc";
5fc6b0dd
LD		 655 nvidia,pull = <TEGRA_PIN_PULL_UP>;
656 nvidia,tristate = <TEGRA_PIN_DISABLE>;
657 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 658 };
659 kb_col5_pq5 {
660 nvidia,pins = "kb_col5_pq5";
661 nvidia,function = "kbc";
5fc6b0dd
LD		 662 nvidia,pull = <TEGRA_PIN_PULL_UP>;
663 nvidia,tristate = <TEGRA_PIN_DISABLE>;
664 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 665 };
666 kb_row3_pr3 {
667 nvidia,pins = "kb_row3_pr3",
668 "kb_row4_pr4",
669 "kb_row6_pr6",
670 "kb_row8_ps0";
671 nvidia,function = "kbc";
5fc6b0dd
LD		 672 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
673 nvidia,tristate = <TEGRA_PIN_DISABLE>;
674 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 675 };
676 clk3_req_pee1 {
677 nvidia,pins = "clk3_req_pee1";
678 nvidia,function = "rsvd4";
5fc6b0dd
LD		 679 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
680 nvidia,tristate = <TEGRA_PIN_DISABLE>;
681 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 682 };
683 pu4 {
684 nvidia,pins = "pu4";
685 nvidia,function = "displayb";
5fc6b0dd
LD		 686 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
687 nvidia,tristate = <TEGRA_PIN_DISABLE>;
688 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 689 };
690 pu5 {
691 nvidia,pins = "pu5",
692 "pu6";
693 nvidia,function = "displayb";
5fc6b0dd
LD		 694 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
695 nvidia,tristate = <TEGRA_PIN_DISABLE>;
696 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 697 };
698 hdmi_int_pn7 {
699 nvidia,pins = "hdmi_int_pn7";
700 nvidia,function = "rsvd1";
5fc6b0dd
LD		 701 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
702 nvidia,tristate = <TEGRA_PIN_DISABLE>;
703 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 704 };
705 clk1_req_pee2 {
706 nvidia,pins = "clk1_req_pee2",
707 "usb_vbus_en1_pn5";
708 nvidia,function = "rsvd4";
5fc6b0dd
LD		 709 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
710 nvidia,tristate = <TEGRA_PIN_ENABLE>;
711 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 712 };
713
714 drive_sdio1 {
715 nvidia,pins = "drive_sdio1";
5fc6b0dd
LD		 716 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
717 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
718 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
2c314d5c
PR		 719 nvidia,pull-down-strength = <36>;
720 nvidia,pull-up-strength = <20>;
5fc6b0dd
LD		 721 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>;
722 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>;
2c314d5c
PR		 723 };
724 drive_sdio3 {
725 nvidia,pins = "drive_sdio3";
5fc6b0dd
LD		 726 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
727 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
728 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
2c314d5c
PR		 729 nvidia,pull-down-strength = <22>;
730 nvidia,pull-up-strength = <36>;
5fc6b0dd
LD		 731 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
732 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
2c314d5c
PR		 733 };
734 drive_gma {
735 nvidia,pins = "drive_gma";
5fc6b0dd
LD		 736 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
737 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
738 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
2c314d5c
PR		 739 nvidia,pull-down-strength = <2>;
740 nvidia,pull-up-strength = <1>;
5fc6b0dd
LD		 741 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
742 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
2c314d5c
PR		 743 nvidia,drive-type = <1>;
744 };
745 };
746 };
747
a71c03e7
HD		 748 serial@70006300 {
749 status = "okay";
a71c03e7
HD		 750 };
751
48b90117
TR		 752 pwm@7000a000 {
753 status = "okay";
754 };
755
33eb271e
RK		 756 i2c@7000c000 {
757 status = "okay";
758 clock-frequency = <100000>;
759
58ecb23f 760 battery: smart-battery@b {
33eb271e
RK		 761 compatible = "ti,bq20z45", "sbs,sbs-battery";
762 reg = <0xb>;
763 battery-name = "battery";
764 sbs,i2c-retry-count = <2>;
765 sbs,poll-retry-count = <100>;
d5284a67 766 power-supplies = <&charger>;
33eb271e 767 };
aa5ae424 768
58ecb23f 769 rt5640: rt5640@1c {
aa5ae424
SW		 770 compatible = "realtek,rt5640";
771 reg = <0x1c>;
772 interrupt-parent = <&gpio>;
773 interrupts = <TEGRA_GPIO(W, 3) GPIO_ACTIVE_HIGH>;
774 realtek,ldo1-en-gpios =
775 <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
776 };
99bda7b9
WN		 777
778 temperature-sensor@4c {
779 compatible = "onnn,nct1008";
780 reg = <0x4c>;
781 vcc-supply = <&palmas_ldo6_reg>;
782 interrupt-parent = <&gpio>;
783 interrupts = <TEGRA_GPIO(O, 4) IRQ_TYPE_LEVEL_LOW>;
784 };
33eb271e
RK		 785 };
786
f044d6fa
MP		 787 hdmi_ddc: i2c@7000c700 {
788 status = "okay";
789 };
790
da204ee2
LD		 791 i2c@7000d000 {
792 status = "okay";
793 clock-frequency = <400000>;
794
58ecb23f 795 tps51632@43 {
da204ee2
LD		 796 compatible = "ti,tps51632";
797 reg = <0x43>;
798 regulator-name = "vdd-cpu";
799 regulator-min-microvolt = <500000>;
800 regulator-max-microvolt = <1520000>;
801 regulator-boot-on;
802 regulator-always-on;
803 };
81c6c56c 804
58ecb23f 805 tps65090@48 {
81c6c56c
LD		 806 compatible = "ti,tps65090";
807 reg = <0x48>;
808 interrupt-parent = <&gpio>;
6cecf916 809 interrupts = <TEGRA_GPIO(J, 0) IRQ_TYPE_LEVEL_HIGH>;
81c6c56c
LD		 810
811 vsys1-supply = <&vdd_ac_bat_reg>;
812 vsys2-supply = <&vdd_ac_bat_reg>;
813 vsys3-supply = <&vdd_ac_bat_reg>;
814 infet1-supply = <&vdd_ac_bat_reg>;
815 infet2-supply = <&vdd_ac_bat_reg>;
816 infet3-supply = <&tps65090_dcdc2_reg>;
817 infet4-supply = <&tps65090_dcdc2_reg>;
818 infet5-supply = <&tps65090_dcdc2_reg>;
819 infet6-supply = <&tps65090_dcdc2_reg>;
820 infet7-supply = <&tps65090_dcdc2_reg>;
821 vsys-l1-supply = <&vdd_ac_bat_reg>;
822 vsys-l2-supply = <&vdd_ac_bat_reg>;
823
d5284a67 824 charger: charger {
1a99ece9
RK		 825 compatible = "ti,tps65090-charger";
826 ti,enable-low-current-chrg;
827 };
828
81c6c56c 829 regulators {
fcf0b3a6 830 tps65090_dcdc1_reg: dcdc1 {
81c6c56c
LD		 831 regulator-name = "vdd-sys-5v0";
832 regulator-always-on;
833 regulator-boot-on;
834 };
835
836 tps65090_dcdc2_reg: dcdc2 {
837 regulator-name = "vdd-sys-3v3";
838 regulator-always-on;
839 regulator-boot-on;
840 };
841
c321d968 842 tps65090_dcdc3_reg: dcdc3 {
81c6c56c
LD		 843 regulator-name = "vdd-ao";
844 regulator-always-on;
845 regulator-boot-on;
846 };
847
48b90117 848 vdd_bl_reg: fet1 {
81c6c56c
LD		 849 regulator-name = "vdd-lcd-bl";
850 };
851
852 fet3 {
853 regulator-name = "vdd-modem-3v3";
854 };
855
48b90117 856 avdd_lcd_reg: fet4 {
81c6c56c
LD		 857 regulator-name = "avdd-lcd";
858 };
859
860 fet5 {
861 regulator-name = "vdd-lvds";
862 };
863
864 fet6 {
865 regulator-name = "vdd-sd-slot";
15d5ef4d 866 regulator-always-on;
81c6c56c
LD		 867 regulator-boot-on;
868 };
869
870 fet7 {
871 regulator-name = "vdd-com-3v3";
872 };
873
874 ldo1 {
875 regulator-name = "vdd-sby-5v0";
876 regulator-always-on;
877 regulator-boot-on;
878 };
879
880 ldo2 {
881 regulator-name = "vdd-sby-3v3";
882 regulator-always-on;
883 regulator-boot-on;
884 };
885 };
886 };
c321d968 887
58ecb23f 888 palmas: tps65913@58 {
c321d968
LD		 889 compatible = "ti,palmas";
890 reg = <0x58>;
eca8f98e 891 interrupts = <0 86 IRQ_TYPE_LEVEL_LOW>;
c321d968
LD		 892
893 #interrupt-cells = <2>;
894 interrupt-controller;
895
27cf5d14
BH		 896 ti,system-power-controller;
897
c321d968
LD		 898 palmas_gpio: gpio {
899 compatible = "ti,palmas-gpio";
900 gpio-controller;
901 #gpio-cells = <2>;
902 };
903
904 pmic {
905 compatible = "ti,tps65913-pmic", "ti,palmas-pmic";
906 smps1-in-supply = <&tps65090_dcdc3_reg>;
907 smps3-in-supply = <&tps65090_dcdc3_reg>;
908 smps4-in-supply = <&tps65090_dcdc2_reg>;
909 smps7-in-supply = <&tps65090_dcdc2_reg>;
910 smps8-in-supply = <&tps65090_dcdc2_reg>;
911 smps9-in-supply = <&tps65090_dcdc2_reg>;
912 ldo1-in-supply = <&tps65090_dcdc2_reg>;
913 ldo2-in-supply = <&tps65090_dcdc2_reg>;
914 ldo3-in-supply = <&palmas_smps3_reg>;
915 ldo4-in-supply = <&tps65090_dcdc2_reg>;
916 ldo5-in-supply = <&vdd_ac_bat_reg>;
917 ldo6-in-supply = <&tps65090_dcdc2_reg>;
918 ldo7-in-supply = <&tps65090_dcdc2_reg>;
919 ldo8-in-supply = <&tps65090_dcdc3_reg>;
920 ldo9-in-supply = <&palmas_smps9_reg>;
921 ldoln-in-supply = <&tps65090_dcdc1_reg>;
922 ldousb-in-supply = <&tps65090_dcdc1_reg>;
923
924 regulators {
925 smps12 {
926 regulator-name = "vddio-ddr";
927 regulator-min-microvolt = <1350000>;
928 regulator-max-microvolt = <1350000>;
929 regulator-always-on;
930 regulator-boot-on;
931 };
932
933 palmas_smps3_reg: smps3 {
934 regulator-name = "vddio-1v8";
935 regulator-min-microvolt = <1800000>;
936 regulator-max-microvolt = <1800000>;
937 regulator-always-on;
938 regulator-boot-on;
939 };
940
941 smps45 {
942 regulator-name = "vdd-core";
943 regulator-min-microvolt = <900000>;
944 regulator-max-microvolt = <1400000>;
945 regulator-always-on;
946 regulator-boot-on;
947 };
948
949 smps457 {
950 regulator-name = "vdd-core";
951 regulator-min-microvolt = <900000>;
952 regulator-max-microvolt = <1400000>;
953 regulator-always-on;
954 regulator-boot-on;
955 };
956
957 smps8 {
958 regulator-name = "avdd-pll";
959 regulator-min-microvolt = <1050000>;
960 regulator-max-microvolt = <1050000>;
961 regulator-always-on;
962 regulator-boot-on;
963 };
964
965 palmas_smps9_reg: smps9 {
966 regulator-name = "sdhci-vdd-sd-slot";
967 regulator-min-microvolt = <2800000>;
968 regulator-max-microvolt = <2800000>;
969 regulator-always-on;
970 };
971
972 ldo1 {
973 regulator-name = "avdd-cam1";
974 regulator-min-microvolt = <2800000>;
975 regulator-max-microvolt = <2800000>;
976 };
977
978 ldo2 {
979 regulator-name = "avdd-cam2";
980 regulator-min-microvolt = <2800000>;
981 regulator-max-microvolt = <2800000>;
982 };
983
984 ldo3 {
985 regulator-name = "avdd-dsi-csi";
986 regulator-min-microvolt = <1200000>;
987 regulator-max-microvolt = <1200000>;
988 regulator-always-on;
989 regulator-boot-on;
990 };
991
992 ldo4 {
993 regulator-name = "vpp-fuse";
994 regulator-min-microvolt = <1800000>;
995 regulator-max-microvolt = <1800000>;
996 };
997
99bda7b9 998 palmas_ldo6_reg: ldo6 {
c321d968
LD		 999 regulator-name = "vdd-sensor-2v85";
1000 regulator-min-microvolt = <2850000>;
1001 regulator-max-microvolt = <2850000>;
1002 };
1003
1004 ldo7 {
1005 regulator-name = "vdd-af-cam1";
1006 regulator-min-microvolt = <2800000>;
1007 regulator-max-microvolt = <2800000>;
1008 };
1009
1010 ldo8 {
1011 regulator-name = "vdd-rtc";
1012 regulator-min-microvolt = <900000>;
1013 regulator-max-microvolt = <900000>;
1014 regulator-always-on;
1015 regulator-boot-on;
1016 ti,enable-ldo8-tracking;
1017 };
1018
1019 ldo9 {
1020 regulator-name = "vddio-sdmmc-2";
1021 regulator-min-microvolt = <1800000>;
1022 regulator-max-microvolt = <3300000>;
1023 regulator-always-on;
1024 regulator-boot-on;
1025 };
1026
1027 ldoln {
1028 regulator-name = "hvdd-usb";
1029 regulator-min-microvolt = <3300000>;
1030 regulator-max-microvolt = <3300000>;
1031 };
1032
1033 ldousb {
1034 regulator-name = "avdd-usb";
1035 regulator-min-microvolt = <3300000>;
1036 regulator-max-microvolt = <3300000>;
1037 regulator-always-on;
1038 regulator-boot-on;
1039 };
1040
1041 regen1 {
1042 regulator-name = "rail-3v3";
1043 regulator-max-microvolt = <3300000>;
1044 regulator-always-on;
1045 regulator-boot-on;
1046 };
1047
1048 regen2 {
1049 regulator-name = "rail-5v0";
1050 regulator-max-microvolt = <5000000>;
1051 regulator-always-on;
1052 regulator-boot-on;
1053 };
1054 };
1055 };
1056
1057 rtc {
1058 compatible = "ti,palmas-rtc";
1059 interrupt-parent = <&palmas>;
1060 interrupts = <8 0>;
1061 };
6be3cf72
LD		 1062
1063 pinmux {
1064 compatible = "ti,tps65913-pinctrl";
1065 pinctrl-names = "default";
1066 pinctrl-0 = <&palmas_default>;
1067
1068 palmas_default: pinmux {
1069 pin_gpio6 {
1070 pins = "gpio6";
1071 function = "gpio";
1072 };
1073 };
1074 };
c321d968 1075 };
da204ee2
LD		 1076 };
1077
5cc75fca
LD		 1078 spi@7000da00 {
1079 status = "okay";
1080 spi-max-frequency = <25000000>;
1081 spi-flash@0 {
1082 compatible = "winbond,w25q32dw";
1083 reg = <0>;
1084 spi-max-frequency = <20000000>;
1085 };
1086 };
1087
58ecb23f 1088 pmc@7000e400 {
a71c03e7 1089 nvidia,invert-interrupt;
47d2d63b 1090 nvidia,suspend-mode = <1>;
4a7658fe
JL		 1091 nvidia,cpu-pwr-good-time = <500>;
1092 nvidia,cpu-pwr-off-time = <300>;
1093 nvidia,core-pwr-good-time = <641 3845>;
1094 nvidia,core-pwr-off-time = <61036>;
1095 nvidia,core-power-req-active-high;
1096 nvidia,sys-clock-req-active-high;
a71c03e7 1097 };
7021d122 1098
58ecb23f 1099 ahub@70080000 {
aa5ae424
SW		 1100 i2s@70080400 {
1101 status = "okay";
1102 };
1103 };
1104
8d3207ca 1105 sdhci@78000400 {
3325f1bc 1106 cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
8d3207ca
RK		 1107 bus-width = <4>;
1108 status = "okay";
1109 };
1110
1111 sdhci@78000600 {
1112 bus-width = <8>;
1113 status = "okay";
7a2617a6 1114 non-removable;
8d3207ca
RK		 1115 };
1116
328dc0ec
MP		 1117 usb@7d008000 {
1118 status = "okay";
1119 };
1120
1121 usb-phy@7d008000 {
1122 status = "okay";
1123 vbus-supply = <&usb3_vbus_reg>;
1124 };
1125
48b90117
TR		 1126 backlight: backlight {
1127 compatible = "pwm-backlight";
1128
1129 enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
1130 power-supply = <&vdd_bl_reg>;
1131 pwms = <&pwm 1 1000000>;
1132
1133 brightness-levels = <0 4 8 16 32 64 128 255>;
1134 default-brightness-level = <6>;
1135 };
1136
7021d122
JL		 1137 clocks {
1138 compatible = "simple-bus";
1139 #address-cells = <1>;
1140 #size-cells = <0>;
1141
58ecb23f 1142 clk32k_in: clock@0 {
7021d122
JL		 1143 compatible = "fixed-clock";
1144 reg=<0>;
1145 #clock-cells = <0>;
1146 clock-frequency = <32768>;
1147 };
1148 };
81c6c56c 1149
21b341ca
LD		 1150 gpio-keys {
1151 compatible = "gpio-keys";
1152
1153 home {
1154 label = "Home";
1155 gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
e6e646e6 1156 linux,code = <KEY_HOME>;
21b341ca
LD		 1157 };
1158
1159 power {
1160 label = "Power";
1161 gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
e6e646e6 1162 linux,code = <KEY_POWER>;
21b341ca
LD		 1163 gpio-key,wakeup;
1164 };
1165
1166 volume_down {
1167 label = "Volume Down";
1168 gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;
e6e646e6 1169 linux,code = <KEY_VOLUMEDOWN>;
21b341ca
LD		 1170 };
1171
1172 volume_up {
1173 label = "Volume Up";
1174 gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>;
e6e646e6 1175 linux,code = <KEY_VOLUMEUP>;
21b341ca
LD		 1176 };
1177 };
1178
81c6c56c
LD		 1179 regulators {
1180 compatible = "simple-bus";
1181 #address-cells = <1>;
1182 #size-cells = <0>;
1183
1184 vdd_ac_bat_reg: regulator@0 {
1185 compatible = "regulator-fixed";
1186 reg = <0>;
1187 regulator-name = "vdd_ac_bat";
1188 regulator-min-microvolt = <5000000>;
1189 regulator-max-microvolt = <5000000>;
1190 regulator-always-on;
1191 };
fcf0b3a6
LD		 1192
1193 dvdd_ts_reg: regulator@1 {
1194 compatible = "regulator-fixed";
1195 reg = <1>;
1196 regulator-name = "dvdd_ts";
1197 regulator-min-microvolt = <1800000>;
1198 regulator-max-microvolt = <1800000>;
1199 enable-active-high;
3325f1bc 1200 gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>;
fcf0b3a6
LD		 1201 };
1202
fcf0b3a6
LD		 1203 usb1_vbus_reg: regulator@3 {
1204 compatible = "regulator-fixed";
1205 reg = <3>;
1206 regulator-name = "usb1_vbus";
1207 regulator-min-microvolt = <5000000>;
1208 regulator-max-microvolt = <5000000>;
1209 enable-active-high;
3325f1bc 1210 gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
fcf0b3a6
LD		 1211 gpio-open-drain;
1212 vin-supply = <&tps65090_dcdc1_reg>;
1213 };
1214
1215 usb3_vbus_reg: regulator@4 {
1216 compatible = "regulator-fixed";
1217 reg = <4>;
1218 regulator-name = "usb2_vbus";
1219 regulator-min-microvolt = <5000000>;
1220 regulator-max-microvolt = <5000000>;
1221 enable-active-high;
3325f1bc 1222 gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
fcf0b3a6
LD		 1223 gpio-open-drain;
1224 vin-supply = <&tps65090_dcdc1_reg>;
1225 };
1226
1227 vdd_hdmi_reg: regulator@5 {
1228 compatible = "regulator-fixed";
1229 reg = <5>;
1230 regulator-name = "vdd_hdmi_5v0";
1231 regulator-min-microvolt = <5000000>;
1232 regulator-max-microvolt = <5000000>;
1233 enable-active-high;
3325f1bc 1234 gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
fcf0b3a6
LD		 1235 vin-supply = <&tps65090_dcdc1_reg>;
1236 };
c321d968
LD		 1237
1238 vdd_cam_1v8_reg: regulator@6 {
1239 compatible = "regulator-fixed";
1240 reg = <6>;
1241 regulator-name = "vdd_cam_1v8_reg";
1242 regulator-min-microvolt = <1800000>;
1243 regulator-max-microvolt = <1800000>;
1244 enable-active-high;
1245 gpio = <&palmas_gpio 6 0>;
1246 };
81c6c56c 1247 };
aa5ae424
SW		 1248
1249 sound {
1250 compatible = "nvidia,tegra-audio-rt5640-dalmore",
1251 "nvidia,tegra-audio-rt5640";
1252 nvidia,model = "NVIDIA Tegra Dalmore";
1253
1254 nvidia,audio-routing =
1255 "Headphones", "HPOR",
1256 "Headphones", "HPOL",
1257 "Speakers", "SPORP",
1258 "Speakers", "SPORN",
1259 "Speakers", "SPOLP",
8af3bbec
SW		 1260 "Speakers", "SPOLN",
1261 "Mic Jack", "MICBIAS1",
1262 "IN2P", "Mic Jack";
aa5ae424
SW		 1263
1264 nvidia,i2s-controller = <&tegra_i2s1>;
1265 nvidia,audio-codec = <&rt5640>;
1266
1267 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
1268
1269 clocks = <&tegra_car TEGRA114_CLK_PLL_A>,
1270 <&tegra_car TEGRA114_CLK_PLL_A_OUT0>,
1271 <&tegra_car TEGRA114_CLK_EXTERN1>;
1272 clock-names = "pll_a", "pll_a_out0", "mclk";
1273 };
a71c03e7 1274};
Linux kernel - Deliverables
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