Commit | Line | Data |
---|---|---|
a71c03e7 HD |
1 | /dts-v1/; |
2 | ||
1bd0bd49 | 3 | #include "tegra114.dtsi" |
a71c03e7 HD |
4 | |
5 | / { | |
6 | model = "NVIDIA Tegra114 Dalmore evaluation board"; | |
7 | compatible = "nvidia,dalmore", "nvidia,tegra114"; | |
8 | ||
9 | memory { | |
10 | reg = <0x80000000 0x40000000>; | |
11 | }; | |
12 | ||
2c314d5c PR |
13 | pinmux { |
14 | pinctrl-names = "default"; | |
15 | pinctrl-0 = <&state_default>; | |
16 | ||
17 | state_default: pinmux { | |
18 | clk1_out_pw4 { | |
19 | nvidia,pins = "clk1_out_pw4"; | |
20 | nvidia,function = "extperiph1"; | |
21 | nvidia,pull = <0>; | |
22 | nvidia,tristate = <0>; | |
23 | nvidia,enable-input = <0>; | |
24 | }; | |
25 | dap1_din_pn1 { | |
26 | nvidia,pins = "dap1_din_pn1"; | |
27 | nvidia,function = "i2s0"; | |
28 | nvidia,pull = <0>; | |
29 | nvidia,tristate = <1>; | |
30 | nvidia,enable-input = <1>; | |
31 | }; | |
32 | dap1_dout_pn2 { | |
33 | nvidia,pins = "dap1_dout_pn2", | |
34 | "dap1_fs_pn0", | |
35 | "dap1_sclk_pn3"; | |
36 | nvidia,function = "i2s0"; | |
37 | nvidia,pull = <0>; | |
38 | nvidia,tristate = <0>; | |
39 | nvidia,enable-input = <1>; | |
40 | }; | |
41 | dap2_din_pa4 { | |
42 | nvidia,pins = "dap2_din_pa4"; | |
43 | nvidia,function = "i2s1"; | |
44 | nvidia,pull = <0>; | |
45 | nvidia,tristate = <1>; | |
46 | nvidia,enable-input = <1>; | |
47 | }; | |
48 | dap2_dout_pa5 { | |
49 | nvidia,pins = "dap2_dout_pa5", | |
50 | "dap2_fs_pa2", | |
51 | "dap2_sclk_pa3"; | |
52 | nvidia,function = "i2s1"; | |
53 | nvidia,pull = <0>; | |
54 | nvidia,tristate = <0>; | |
55 | nvidia,enable-input = <1>; | |
56 | }; | |
57 | dap4_din_pp5 { | |
58 | nvidia,pins = "dap4_din_pp5", | |
59 | "dap4_dout_pp6", | |
60 | "dap4_fs_pp4", | |
61 | "dap4_sclk_pp7"; | |
62 | nvidia,function = "i2s3"; | |
63 | nvidia,pull = <0>; | |
64 | nvidia,tristate = <0>; | |
65 | nvidia,enable-input = <1>; | |
66 | }; | |
67 | dvfs_pwm_px0 { | |
68 | nvidia,pins = "dvfs_pwm_px0", | |
69 | "dvfs_clk_px2"; | |
70 | nvidia,function = "cldvfs"; | |
71 | nvidia,pull = <0>; | |
72 | nvidia,tristate = <0>; | |
73 | nvidia,enable-input = <0>; | |
74 | }; | |
75 | ulpi_clk_py0 { | |
76 | nvidia,pins = "ulpi_clk_py0", | |
77 | "ulpi_data0_po1", | |
78 | "ulpi_data1_po2", | |
79 | "ulpi_data2_po3", | |
80 | "ulpi_data3_po4", | |
81 | "ulpi_data4_po5", | |
82 | "ulpi_data5_po6", | |
83 | "ulpi_data6_po7", | |
84 | "ulpi_data7_po0"; | |
85 | nvidia,function = "ulpi"; | |
86 | nvidia,pull = <0>; | |
87 | nvidia,tristate = <0>; | |
88 | nvidia,enable-input = <1>; | |
89 | }; | |
90 | ulpi_dir_py1 { | |
91 | nvidia,pins = "ulpi_dir_py1", | |
92 | "ulpi_nxt_py2"; | |
93 | nvidia,function = "ulpi"; | |
94 | nvidia,pull = <0>; | |
95 | nvidia,tristate = <1>; | |
96 | nvidia,enable-input = <1>; | |
97 | }; | |
98 | ulpi_stp_py3 { | |
99 | nvidia,pins = "ulpi_stp_py3"; | |
100 | nvidia,function = "ulpi"; | |
101 | nvidia,pull = <0>; | |
102 | nvidia,tristate = <0>; | |
103 | nvidia,enable-input = <0>; | |
104 | }; | |
105 | cam_i2c_scl_pbb1 { | |
106 | nvidia,pins = "cam_i2c_scl_pbb1", | |
107 | "cam_i2c_sda_pbb2"; | |
108 | nvidia,function = "i2c3"; | |
109 | nvidia,pull = <0>; | |
110 | nvidia,tristate = <0>; | |
111 | nvidia,enable-input = <1>; | |
112 | nvidia,lock = <0>; | |
113 | nvidia,open-drain = <0>; | |
114 | }; | |
115 | cam_mclk_pcc0 { | |
116 | nvidia,pins = "cam_mclk_pcc0", | |
117 | "pbb0"; | |
118 | nvidia,function = "vi_alt3"; | |
119 | nvidia,pull = <0>; | |
120 | nvidia,tristate = <0>; | |
121 | nvidia,enable-input = <0>; | |
122 | nvidia,lock = <0>; | |
123 | }; | |
124 | gen2_i2c_scl_pt5 { | |
125 | nvidia,pins = "gen2_i2c_scl_pt5", | |
126 | "gen2_i2c_sda_pt6"; | |
127 | nvidia,function = "i2c2"; | |
128 | nvidia,pull = <0>; | |
129 | nvidia,tristate = <0>; | |
130 | nvidia,enable-input = <1>; | |
131 | nvidia,lock = <0>; | |
132 | nvidia,open-drain = <0>; | |
133 | }; | |
134 | gmi_a16_pj7 { | |
135 | nvidia,pins = "gmi_a16_pj7"; | |
136 | nvidia,function = "uartd"; | |
137 | nvidia,pull = <0>; | |
138 | nvidia,tristate = <0>; | |
139 | nvidia,enable-input = <0>; | |
140 | }; | |
141 | gmi_a17_pb0 { | |
142 | nvidia,pins = "gmi_a17_pb0", | |
143 | "gmi_a18_pb1"; | |
144 | nvidia,function = "uartd"; | |
145 | nvidia,pull = <0>; | |
146 | nvidia,tristate = <1>; | |
147 | nvidia,enable-input = <1>; | |
148 | }; | |
149 | gmi_a19_pk7 { | |
150 | nvidia,pins = "gmi_a19_pk7"; | |
151 | nvidia,function = "uartd"; | |
152 | nvidia,pull = <0>; | |
153 | nvidia,tristate = <0>; | |
154 | nvidia,enable-input = <0>; | |
155 | }; | |
156 | gmi_ad5_pg5 { | |
157 | nvidia,pins = "gmi_ad5_pg5", | |
158 | "gmi_cs6_n_pi3", | |
159 | "gmi_wr_n_pi0"; | |
160 | nvidia,function = "spi4"; | |
161 | nvidia,pull = <0>; | |
162 | nvidia,tristate = <0>; | |
163 | nvidia,enable-input = <1>; | |
164 | }; | |
165 | gmi_ad6_pg6 { | |
166 | nvidia,pins = "gmi_ad6_pg6", | |
167 | "gmi_ad7_pg7"; | |
168 | nvidia,function = "spi4"; | |
169 | nvidia,pull = <2>; | |
170 | nvidia,tristate = <0>; | |
171 | nvidia,enable-input = <1>; | |
172 | }; | |
173 | gmi_ad12_ph4 { | |
174 | nvidia,pins = "gmi_ad12_ph4"; | |
175 | nvidia,function = "rsvd4"; | |
176 | nvidia,pull = <0>; | |
177 | nvidia,tristate = <0>; | |
178 | nvidia,enable-input = <0>; | |
179 | }; | |
180 | gmi_ad9_ph1 { | |
181 | nvidia,pins = "gmi_ad9_ph1"; | |
182 | nvidia,function = "pwm1"; | |
183 | nvidia,pull = <0>; | |
184 | nvidia,tristate = <0>; | |
185 | nvidia,enable-input = <0>; | |
186 | }; | |
187 | gmi_cs1_n_pj2 { | |
188 | nvidia,pins = "gmi_cs1_n_pj2", | |
189 | "gmi_oe_n_pi1"; | |
190 | nvidia,function = "soc"; | |
191 | nvidia,pull = <0>; | |
192 | nvidia,tristate = <1>; | |
193 | nvidia,enable-input = <1>; | |
194 | }; | |
195 | clk2_out_pw5 { | |
196 | nvidia,pins = "clk2_out_pw5"; | |
197 | nvidia,function = "extperiph2"; | |
198 | nvidia,pull = <0>; | |
199 | nvidia,tristate = <0>; | |
200 | nvidia,enable-input = <0>; | |
201 | }; | |
202 | sdmmc1_clk_pz0 { | |
203 | nvidia,pins = "sdmmc1_clk_pz0"; | |
204 | nvidia,function = "sdmmc1"; | |
205 | nvidia,pull = <0>; | |
206 | nvidia,tristate = <0>; | |
207 | nvidia,enable-input = <1>; | |
208 | }; | |
209 | sdmmc1_cmd_pz1 { | |
210 | nvidia,pins = "sdmmc1_cmd_pz1", | |
211 | "sdmmc1_dat0_py7", | |
212 | "sdmmc1_dat1_py6", | |
213 | "sdmmc1_dat2_py5", | |
214 | "sdmmc1_dat3_py4"; | |
215 | nvidia,function = "sdmmc1"; | |
216 | nvidia,pull = <2>; | |
217 | nvidia,tristate = <0>; | |
218 | nvidia,enable-input = <1>; | |
219 | }; | |
220 | sdmmc1_wp_n_pv3 { | |
221 | nvidia,pins = "sdmmc1_wp_n_pv3"; | |
222 | nvidia,function = "spi4"; | |
223 | nvidia,pull = <2>; | |
224 | nvidia,tristate = <0>; | |
225 | nvidia,enable-input = <0>; | |
226 | }; | |
227 | sdmmc3_clk_pa6 { | |
228 | nvidia,pins = "sdmmc3_clk_pa6"; | |
229 | nvidia,function = "sdmmc3"; | |
230 | nvidia,pull = <0>; | |
231 | nvidia,tristate = <0>; | |
232 | nvidia,enable-input = <1>; | |
233 | }; | |
234 | sdmmc3_cmd_pa7 { | |
235 | nvidia,pins = "sdmmc3_cmd_pa7", | |
236 | "sdmmc3_dat0_pb7", | |
237 | "sdmmc3_dat1_pb6", | |
238 | "sdmmc3_dat2_pb5", | |
239 | "sdmmc3_dat3_pb4", | |
240 | "kb_col4_pq4", | |
241 | "sdmmc3_clk_lb_out_pee4", | |
242 | "sdmmc3_clk_lb_in_pee5"; | |
243 | nvidia,function = "sdmmc3"; | |
244 | nvidia,pull = <2>; | |
245 | nvidia,tristate = <0>; | |
246 | nvidia,enable-input = <1>; | |
247 | }; | |
248 | sdmmc4_clk_pcc4 { | |
249 | nvidia,pins = "sdmmc4_clk_pcc4"; | |
250 | nvidia,function = "sdmmc4"; | |
251 | nvidia,pull = <0>; | |
252 | nvidia,tristate = <0>; | |
253 | nvidia,enable-input = <1>; | |
254 | }; | |
255 | sdmmc4_cmd_pt7 { | |
256 | nvidia,pins = "sdmmc4_cmd_pt7", | |
257 | "sdmmc4_dat0_paa0", | |
258 | "sdmmc4_dat1_paa1", | |
259 | "sdmmc4_dat2_paa2", | |
260 | "sdmmc4_dat3_paa3", | |
261 | "sdmmc4_dat4_paa4", | |
262 | "sdmmc4_dat5_paa5", | |
263 | "sdmmc4_dat6_paa6", | |
264 | "sdmmc4_dat7_paa7"; | |
265 | nvidia,function = "sdmmc4"; | |
266 | nvidia,pull = <2>; | |
267 | nvidia,tristate = <0>; | |
268 | nvidia,enable-input = <1>; | |
269 | }; | |
270 | clk_32k_out_pa0 { | |
271 | nvidia,pins = "clk_32k_out_pa0"; | |
272 | nvidia,function = "blink"; | |
273 | nvidia,pull = <0>; | |
274 | nvidia,tristate = <0>; | |
275 | nvidia,enable-input = <0>; | |
276 | }; | |
277 | kb_col0_pq0 { | |
278 | nvidia,pins = "kb_col0_pq0", | |
279 | "kb_col1_pq1", | |
280 | "kb_col2_pq2", | |
281 | "kb_row0_pr0", | |
282 | "kb_row1_pr1", | |
283 | "kb_row2_pr2"; | |
284 | nvidia,function = "kbc"; | |
285 | nvidia,pull = <2>; | |
286 | nvidia,tristate = <0>; | |
287 | nvidia,enable-input = <1>; | |
288 | }; | |
289 | dap3_din_pp1 { | |
290 | nvidia,pins = "dap3_din_pp1", | |
291 | "dap3_sclk_pp3"; | |
292 | nvidia,function = "displayb"; | |
293 | nvidia,pull = <0>; | |
294 | nvidia,tristate = <1>; | |
295 | nvidia,enable-input = <0>; | |
296 | }; | |
297 | pv0 { | |
298 | nvidia,pins = "pv0"; | |
299 | nvidia,function = "rsvd4"; | |
300 | nvidia,pull = <0>; | |
301 | nvidia,tristate = <1>; | |
302 | nvidia,enable-input = <0>; | |
303 | }; | |
304 | kb_row7_pr7 { | |
305 | nvidia,pins = "kb_row7_pr7"; | |
306 | nvidia,function = "rsvd2"; | |
307 | nvidia,pull = <2>; | |
308 | nvidia,tristate = <0>; | |
309 | nvidia,enable-input = <1>; | |
310 | }; | |
311 | kb_row10_ps2 { | |
312 | nvidia,pins = "kb_row10_ps2"; | |
313 | nvidia,function = "uarta"; | |
314 | nvidia,pull = <0>; | |
315 | nvidia,tristate = <1>; | |
316 | nvidia,enable-input = <1>; | |
317 | }; | |
318 | kb_row9_ps1 { | |
319 | nvidia,pins = "kb_row9_ps1"; | |
320 | nvidia,function = "uarta"; | |
321 | nvidia,pull = <0>; | |
322 | nvidia,tristate = <0>; | |
323 | nvidia,enable-input = <0>; | |
324 | }; | |
325 | pwr_i2c_scl_pz6 { | |
326 | nvidia,pins = "pwr_i2c_scl_pz6", | |
327 | "pwr_i2c_sda_pz7"; | |
328 | nvidia,function = "i2cpwr"; | |
329 | nvidia,pull = <0>; | |
330 | nvidia,tristate = <0>; | |
331 | nvidia,enable-input = <1>; | |
332 | nvidia,lock = <0>; | |
333 | nvidia,open-drain = <0>; | |
334 | }; | |
335 | sys_clk_req_pz5 { | |
336 | nvidia,pins = "sys_clk_req_pz5"; | |
337 | nvidia,function = "sysclk"; | |
338 | nvidia,pull = <0>; | |
339 | nvidia,tristate = <0>; | |
340 | nvidia,enable-input = <0>; | |
341 | }; | |
342 | core_pwr_req { | |
343 | nvidia,pins = "core_pwr_req"; | |
344 | nvidia,function = "pwron"; | |
345 | nvidia,pull = <0>; | |
346 | nvidia,tristate = <0>; | |
347 | nvidia,enable-input = <0>; | |
348 | }; | |
349 | cpu_pwr_req { | |
350 | nvidia,pins = "cpu_pwr_req"; | |
351 | nvidia,function = "cpu"; | |
352 | nvidia,pull = <0>; | |
353 | nvidia,tristate = <0>; | |
354 | nvidia,enable-input = <0>; | |
355 | }; | |
356 | pwr_int_n { | |
357 | nvidia,pins = "pwr_int_n"; | |
358 | nvidia,function = "pmi"; | |
359 | nvidia,pull = <0>; | |
360 | nvidia,tristate = <1>; | |
361 | nvidia,enable-input = <1>; | |
362 | }; | |
363 | reset_out_n { | |
364 | nvidia,pins = "reset_out_n"; | |
365 | nvidia,function = "reset_out_n"; | |
366 | nvidia,pull = <0>; | |
367 | nvidia,tristate = <0>; | |
368 | nvidia,enable-input = <0>; | |
369 | }; | |
370 | clk3_out_pee0 { | |
371 | nvidia,pins = "clk3_out_pee0"; | |
372 | nvidia,function = "extperiph3"; | |
373 | nvidia,pull = <0>; | |
374 | nvidia,tristate = <0>; | |
375 | nvidia,enable-input = <0>; | |
376 | }; | |
377 | gen1_i2c_scl_pc4 { | |
378 | nvidia,pins = "gen1_i2c_scl_pc4", | |
379 | "gen1_i2c_sda_pc5"; | |
380 | nvidia,function = "i2c1"; | |
381 | nvidia,pull = <0>; | |
382 | nvidia,tristate = <0>; | |
383 | nvidia,enable-input = <1>; | |
384 | nvidia,lock = <0>; | |
385 | nvidia,open-drain = <0>; | |
386 | }; | |
387 | uart2_cts_n_pj5 { | |
388 | nvidia,pins = "uart2_cts_n_pj5"; | |
389 | nvidia,function = "uartb"; | |
390 | nvidia,pull = <0>; | |
391 | nvidia,tristate = <1>; | |
392 | nvidia,enable-input = <1>; | |
393 | }; | |
394 | uart2_rts_n_pj6 { | |
395 | nvidia,pins = "uart2_rts_n_pj6"; | |
396 | nvidia,function = "uartb"; | |
397 | nvidia,pull = <0>; | |
398 | nvidia,tristate = <0>; | |
399 | nvidia,enable-input = <0>; | |
400 | }; | |
401 | uart2_rxd_pc3 { | |
402 | nvidia,pins = "uart2_rxd_pc3"; | |
403 | nvidia,function = "irda"; | |
404 | nvidia,pull = <0>; | |
405 | nvidia,tristate = <1>; | |
406 | nvidia,enable-input = <1>; | |
407 | }; | |
408 | uart2_txd_pc2 { | |
409 | nvidia,pins = "uart2_txd_pc2"; | |
410 | nvidia,function = "irda"; | |
411 | nvidia,pull = <0>; | |
412 | nvidia,tristate = <0>; | |
413 | nvidia,enable-input = <0>; | |
414 | }; | |
415 | uart3_cts_n_pa1 { | |
416 | nvidia,pins = "uart3_cts_n_pa1", | |
417 | "uart3_rxd_pw7"; | |
418 | nvidia,function = "uartc"; | |
419 | nvidia,pull = <0>; | |
420 | nvidia,tristate = <1>; | |
421 | nvidia,enable-input = <1>; | |
422 | }; | |
423 | uart3_rts_n_pc0 { | |
424 | nvidia,pins = "uart3_rts_n_pc0", | |
425 | "uart3_txd_pw6"; | |
426 | nvidia,function = "uartc"; | |
427 | nvidia,pull = <0>; | |
428 | nvidia,tristate = <0>; | |
429 | nvidia,enable-input = <0>; | |
430 | }; | |
431 | owr { | |
432 | nvidia,pins = "owr"; | |
433 | nvidia,function = "owr"; | |
434 | nvidia,pull = <0>; | |
435 | nvidia,tristate = <0>; | |
436 | nvidia,enable-input = <1>; | |
437 | }; | |
438 | hdmi_cec_pee3 { | |
439 | nvidia,pins = "hdmi_cec_pee3"; | |
440 | nvidia,function = "cec"; | |
441 | nvidia,pull = <0>; | |
442 | nvidia,tristate = <0>; | |
443 | nvidia,enable-input = <1>; | |
444 | nvidia,lock = <0>; | |
445 | nvidia,open-drain = <0>; | |
446 | }; | |
447 | ddc_scl_pv4 { | |
448 | nvidia,pins = "ddc_scl_pv4", | |
449 | "ddc_sda_pv5"; | |
450 | nvidia,function = "i2c4"; | |
451 | nvidia,pull = <0>; | |
452 | nvidia,tristate = <0>; | |
453 | nvidia,enable-input = <1>; | |
454 | nvidia,lock = <0>; | |
455 | nvidia,rcv-sel = <1>; | |
456 | }; | |
457 | spdif_in_pk6 { | |
458 | nvidia,pins = "spdif_in_pk6"; | |
459 | nvidia,function = "usb"; | |
460 | nvidia,pull = <2>; | |
461 | nvidia,tristate = <0>; | |
462 | nvidia,enable-input = <1>; | |
463 | nvidia,lock = <0>; | |
464 | }; | |
465 | usb_vbus_en0_pn4 { | |
466 | nvidia,pins = "usb_vbus_en0_pn4"; | |
467 | nvidia,function = "usb"; | |
468 | nvidia,pull = <2>; | |
469 | nvidia,tristate = <0>; | |
470 | nvidia,enable-input = <1>; | |
471 | nvidia,lock = <0>; | |
472 | nvidia,open-drain = <1>; | |
473 | }; | |
474 | gpio_x6_aud_px6 { | |
475 | nvidia,pins = "gpio_x6_aud_px6"; | |
476 | nvidia,function = "spi6"; | |
477 | nvidia,pull = <2>; | |
478 | nvidia,tristate = <1>; | |
479 | nvidia,enable-input = <1>; | |
480 | }; | |
481 | gpio_x4_aud_px4 { | |
482 | nvidia,pins = "gpio_x4_aud_px4", | |
483 | "gpio_x7_aud_px7"; | |
484 | nvidia,function = "rsvd1"; | |
485 | nvidia,pull = <1>; | |
486 | nvidia,tristate = <0>; | |
487 | nvidia,enable-input = <0>; | |
488 | }; | |
489 | gpio_x5_aud_px5 { | |
490 | nvidia,pins = "gpio_x5_aud_px5"; | |
491 | nvidia,function = "rsvd1"; | |
492 | nvidia,pull = <2>; | |
493 | nvidia,tristate = <0>; | |
494 | nvidia,enable-input = <1>; | |
495 | }; | |
496 | gpio_w2_aud_pw2 { | |
497 | nvidia,pins = "gpio_w2_aud_pw2"; | |
498 | nvidia,function = "rsvd2"; | |
499 | nvidia,pull = <2>; | |
500 | nvidia,tristate = <0>; | |
501 | nvidia,enable-input = <1>; | |
502 | }; | |
503 | gpio_w3_aud_pw3 { | |
504 | nvidia,pins = "gpio_w3_aud_pw3"; | |
505 | nvidia,function = "spi6"; | |
506 | nvidia,pull = <2>; | |
507 | nvidia,tristate = <0>; | |
508 | nvidia,enable-input = <1>; | |
509 | }; | |
510 | gpio_x1_aud_px1 { | |
511 | nvidia,pins = "gpio_x1_aud_px1"; | |
512 | nvidia,function = "rsvd4"; | |
513 | nvidia,pull = <1>; | |
514 | nvidia,tristate = <0>; | |
515 | nvidia,enable-input = <1>; | |
516 | }; | |
517 | gpio_x3_aud_px3 { | |
518 | nvidia,pins = "gpio_x3_aud_px3"; | |
519 | nvidia,function = "rsvd4"; | |
520 | nvidia,pull = <2>; | |
521 | nvidia,tristate = <0>; | |
522 | nvidia,enable-input = <1>; | |
523 | }; | |
524 | dap3_fs_pp0 { | |
525 | nvidia,pins = "dap3_fs_pp0"; | |
526 | nvidia,function = "i2s2"; | |
527 | nvidia,pull = <1>; | |
528 | nvidia,tristate = <0>; | |
529 | nvidia,enable-input = <0>; | |
530 | }; | |
531 | dap3_dout_pp2 { | |
532 | nvidia,pins = "dap3_dout_pp2"; | |
533 | nvidia,function = "i2s2"; | |
534 | nvidia,pull = <1>; | |
535 | nvidia,tristate = <0>; | |
536 | nvidia,enable-input = <0>; | |
537 | }; | |
538 | pv1 { | |
539 | nvidia,pins = "pv1"; | |
540 | nvidia,function = "rsvd1"; | |
541 | nvidia,pull = <0>; | |
542 | nvidia,tristate = <0>; | |
543 | nvidia,enable-input = <1>; | |
544 | }; | |
545 | pbb3 { | |
546 | nvidia,pins = "pbb3", | |
547 | "pbb5", | |
548 | "pbb6", | |
549 | "pbb7"; | |
550 | nvidia,function = "rsvd4"; | |
551 | nvidia,pull = <1>; | |
552 | nvidia,tristate = <0>; | |
553 | nvidia,enable-input = <0>; | |
554 | }; | |
555 | pcc1 { | |
556 | nvidia,pins = "pcc1", | |
557 | "pcc2"; | |
558 | nvidia,function = "rsvd4"; | |
559 | nvidia,pull = <1>; | |
560 | nvidia,tristate = <0>; | |
561 | nvidia,enable-input = <1>; | |
562 | }; | |
563 | gmi_ad0_pg0 { | |
564 | nvidia,pins = "gmi_ad0_pg0", | |
565 | "gmi_ad1_pg1"; | |
566 | nvidia,function = "gmi"; | |
567 | nvidia,pull = <0>; | |
568 | nvidia,tristate = <0>; | |
569 | nvidia,enable-input = <0>; | |
570 | }; | |
571 | gmi_ad10_ph2 { | |
572 | nvidia,pins = "gmi_ad10_ph2", | |
573 | "gmi_ad11_ph3", | |
574 | "gmi_ad13_ph5", | |
575 | "gmi_ad8_ph0", | |
576 | "gmi_clk_pk1"; | |
577 | nvidia,function = "gmi"; | |
578 | nvidia,pull = <1>; | |
579 | nvidia,tristate = <0>; | |
580 | nvidia,enable-input = <0>; | |
581 | }; | |
582 | gmi_ad2_pg2 { | |
583 | nvidia,pins = "gmi_ad2_pg2", | |
584 | "gmi_ad3_pg3"; | |
585 | nvidia,function = "gmi"; | |
586 | nvidia,pull = <0>; | |
587 | nvidia,tristate = <0>; | |
588 | nvidia,enable-input = <1>; | |
589 | }; | |
590 | gmi_adv_n_pk0 { | |
591 | nvidia,pins = "gmi_adv_n_pk0", | |
592 | "gmi_cs0_n_pj0", | |
593 | "gmi_cs2_n_pk3", | |
594 | "gmi_cs4_n_pk2", | |
595 | "gmi_cs7_n_pi6", | |
596 | "gmi_dqs_p_pj3", | |
597 | "gmi_iordy_pi5", | |
598 | "gmi_wp_n_pc7"; | |
599 | nvidia,function = "gmi"; | |
600 | nvidia,pull = <2>; | |
601 | nvidia,tristate = <0>; | |
602 | nvidia,enable-input = <1>; | |
603 | }; | |
604 | gmi_cs3_n_pk4 { | |
605 | nvidia,pins = "gmi_cs3_n_pk4"; | |
606 | nvidia,function = "gmi"; | |
607 | nvidia,pull = <2>; | |
608 | nvidia,tristate = <0>; | |
609 | nvidia,enable-input = <0>; | |
610 | }; | |
611 | clk2_req_pcc5 { | |
612 | nvidia,pins = "clk2_req_pcc5"; | |
613 | nvidia,function = "rsvd4"; | |
614 | nvidia,pull = <0>; | |
615 | nvidia,tristate = <0>; | |
616 | nvidia,enable-input = <0>; | |
617 | }; | |
618 | kb_col3_pq3 { | |
619 | nvidia,pins = "kb_col3_pq3", | |
620 | "kb_col6_pq6", | |
621 | "kb_col7_pq7"; | |
622 | nvidia,function = "kbc"; | |
623 | nvidia,pull = <2>; | |
624 | nvidia,tristate = <0>; | |
625 | nvidia,enable-input = <0>; | |
626 | }; | |
627 | kb_col5_pq5 { | |
628 | nvidia,pins = "kb_col5_pq5"; | |
629 | nvidia,function = "kbc"; | |
630 | nvidia,pull = <2>; | |
631 | nvidia,tristate = <0>; | |
632 | nvidia,enable-input = <1>; | |
633 | }; | |
634 | kb_row3_pr3 { | |
635 | nvidia,pins = "kb_row3_pr3", | |
636 | "kb_row4_pr4", | |
637 | "kb_row6_pr6", | |
638 | "kb_row8_ps0"; | |
639 | nvidia,function = "kbc"; | |
640 | nvidia,pull = <1>; | |
641 | nvidia,tristate = <0>; | |
642 | nvidia,enable-input = <1>; | |
643 | }; | |
644 | clk3_req_pee1 { | |
645 | nvidia,pins = "clk3_req_pee1"; | |
646 | nvidia,function = "rsvd4"; | |
647 | nvidia,pull = <0>; | |
648 | nvidia,tristate = <0>; | |
649 | nvidia,enable-input = <0>; | |
650 | }; | |
651 | pu4 { | |
652 | nvidia,pins = "pu4"; | |
653 | nvidia,function = "displayb"; | |
654 | nvidia,pull = <0>; | |
655 | nvidia,tristate = <0>; | |
656 | nvidia,enable-input = <0>; | |
657 | }; | |
658 | pu5 { | |
659 | nvidia,pins = "pu5", | |
660 | "pu6"; | |
661 | nvidia,function = "displayb"; | |
662 | nvidia,pull = <0>; | |
663 | nvidia,tristate = <0>; | |
664 | nvidia,enable-input = <1>; | |
665 | }; | |
666 | hdmi_int_pn7 { | |
667 | nvidia,pins = "hdmi_int_pn7"; | |
668 | nvidia,function = "rsvd1"; | |
669 | nvidia,pull = <1>; | |
670 | nvidia,tristate = <0>; | |
671 | nvidia,enable-input = <1>; | |
672 | }; | |
673 | clk1_req_pee2 { | |
674 | nvidia,pins = "clk1_req_pee2", | |
675 | "usb_vbus_en1_pn5"; | |
676 | nvidia,function = "rsvd4"; | |
677 | nvidia,pull = <1>; | |
678 | nvidia,tristate = <1>; | |
679 | nvidia,enable-input = <0>; | |
680 | }; | |
681 | ||
682 | drive_sdio1 { | |
683 | nvidia,pins = "drive_sdio1"; | |
684 | nvidia,high-speed-mode = <1>; | |
685 | nvidia,schmitt = <0>; | |
686 | nvidia,low-power-mode = <3>; | |
687 | nvidia,pull-down-strength = <36>; | |
688 | nvidia,pull-up-strength = <20>; | |
689 | nvidia,slew-rate-rising = <2>; | |
690 | nvidia,slew-rate-falling = <2>; | |
691 | }; | |
692 | drive_sdio3 { | |
693 | nvidia,pins = "drive_sdio3"; | |
694 | nvidia,high-speed-mode = <1>; | |
695 | nvidia,schmitt = <0>; | |
696 | nvidia,low-power-mode = <3>; | |
697 | nvidia,pull-down-strength = <22>; | |
698 | nvidia,pull-up-strength = <36>; | |
699 | nvidia,slew-rate-rising = <0>; | |
700 | nvidia,slew-rate-falling = <0>; | |
701 | }; | |
702 | drive_gma { | |
703 | nvidia,pins = "drive_gma"; | |
704 | nvidia,high-speed-mode = <1>; | |
705 | nvidia,schmitt = <0>; | |
706 | nvidia,low-power-mode = <3>; | |
707 | nvidia,pull-down-strength = <2>; | |
708 | nvidia,pull-up-strength = <1>; | |
709 | nvidia,slew-rate-rising = <0>; | |
710 | nvidia,slew-rate-falling = <0>; | |
711 | nvidia,drive-type = <1>; | |
712 | }; | |
713 | }; | |
714 | }; | |
715 | ||
a71c03e7 HD |
716 | serial@70006300 { |
717 | status = "okay"; | |
a71c03e7 HD |
718 | }; |
719 | ||
33eb271e RK |
720 | i2c@7000c000 { |
721 | status = "okay"; | |
722 | clock-frequency = <100000>; | |
723 | ||
724 | battery: smart-battery { | |
725 | compatible = "ti,bq20z45", "sbs,sbs-battery"; | |
726 | reg = <0xb>; | |
727 | battery-name = "battery"; | |
728 | sbs,i2c-retry-count = <2>; | |
729 | sbs,poll-retry-count = <100>; | |
d5284a67 | 730 | power-supplies = <&charger>; |
33eb271e | 731 | }; |
aa5ae424 SW |
732 | |
733 | rt5640: rt5640 { | |
734 | compatible = "realtek,rt5640"; | |
735 | reg = <0x1c>; | |
736 | interrupt-parent = <&gpio>; | |
737 | interrupts = <TEGRA_GPIO(W, 3) GPIO_ACTIVE_HIGH>; | |
738 | realtek,ldo1-en-gpios = | |
739 | <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; | |
740 | }; | |
33eb271e RK |
741 | }; |
742 | ||
da204ee2 LD |
743 | i2c@7000d000 { |
744 | status = "okay"; | |
745 | clock-frequency = <400000>; | |
746 | ||
747 | tps51632 { | |
748 | compatible = "ti,tps51632"; | |
749 | reg = <0x43>; | |
750 | regulator-name = "vdd-cpu"; | |
751 | regulator-min-microvolt = <500000>; | |
752 | regulator-max-microvolt = <1520000>; | |
753 | regulator-boot-on; | |
754 | regulator-always-on; | |
755 | }; | |
81c6c56c LD |
756 | |
757 | tps65090 { | |
758 | compatible = "ti,tps65090"; | |
759 | reg = <0x48>; | |
760 | interrupt-parent = <&gpio>; | |
6cecf916 | 761 | interrupts = <TEGRA_GPIO(J, 0) IRQ_TYPE_LEVEL_HIGH>; |
81c6c56c LD |
762 | |
763 | vsys1-supply = <&vdd_ac_bat_reg>; | |
764 | vsys2-supply = <&vdd_ac_bat_reg>; | |
765 | vsys3-supply = <&vdd_ac_bat_reg>; | |
766 | infet1-supply = <&vdd_ac_bat_reg>; | |
767 | infet2-supply = <&vdd_ac_bat_reg>; | |
768 | infet3-supply = <&tps65090_dcdc2_reg>; | |
769 | infet4-supply = <&tps65090_dcdc2_reg>; | |
770 | infet5-supply = <&tps65090_dcdc2_reg>; | |
771 | infet6-supply = <&tps65090_dcdc2_reg>; | |
772 | infet7-supply = <&tps65090_dcdc2_reg>; | |
773 | vsys-l1-supply = <&vdd_ac_bat_reg>; | |
774 | vsys-l2-supply = <&vdd_ac_bat_reg>; | |
775 | ||
d5284a67 | 776 | charger: charger { |
1a99ece9 RK |
777 | compatible = "ti,tps65090-charger"; |
778 | ti,enable-low-current-chrg; | |
779 | }; | |
780 | ||
81c6c56c | 781 | regulators { |
fcf0b3a6 | 782 | tps65090_dcdc1_reg: dcdc1 { |
81c6c56c LD |
783 | regulator-name = "vdd-sys-5v0"; |
784 | regulator-always-on; | |
785 | regulator-boot-on; | |
786 | }; | |
787 | ||
788 | tps65090_dcdc2_reg: dcdc2 { | |
789 | regulator-name = "vdd-sys-3v3"; | |
790 | regulator-always-on; | |
791 | regulator-boot-on; | |
792 | }; | |
793 | ||
794 | dcdc3 { | |
795 | regulator-name = "vdd-ao"; | |
796 | regulator-always-on; | |
797 | regulator-boot-on; | |
798 | }; | |
799 | ||
800 | fet1 { | |
801 | regulator-name = "vdd-lcd-bl"; | |
802 | }; | |
803 | ||
804 | fet3 { | |
805 | regulator-name = "vdd-modem-3v3"; | |
806 | }; | |
807 | ||
808 | fet4 { | |
809 | regulator-name = "avdd-lcd"; | |
810 | }; | |
811 | ||
812 | fet5 { | |
813 | regulator-name = "vdd-lvds"; | |
814 | }; | |
815 | ||
816 | fet6 { | |
817 | regulator-name = "vdd-sd-slot"; | |
15d5ef4d | 818 | regulator-always-on; |
81c6c56c LD |
819 | regulator-boot-on; |
820 | }; | |
821 | ||
822 | fet7 { | |
823 | regulator-name = "vdd-com-3v3"; | |
824 | }; | |
825 | ||
826 | ldo1 { | |
827 | regulator-name = "vdd-sby-5v0"; | |
828 | regulator-always-on; | |
829 | regulator-boot-on; | |
830 | }; | |
831 | ||
832 | ldo2 { | |
833 | regulator-name = "vdd-sby-3v3"; | |
834 | regulator-always-on; | |
835 | regulator-boot-on; | |
836 | }; | |
837 | }; | |
838 | }; | |
da204ee2 LD |
839 | }; |
840 | ||
5cc75fca LD |
841 | spi@7000da00 { |
842 | status = "okay"; | |
843 | spi-max-frequency = <25000000>; | |
844 | spi-flash@0 { | |
845 | compatible = "winbond,w25q32dw"; | |
846 | reg = <0>; | |
847 | spi-max-frequency = <20000000>; | |
848 | }; | |
849 | }; | |
850 | ||
a71c03e7 HD |
851 | pmc { |
852 | nvidia,invert-interrupt; | |
853 | }; | |
7021d122 | 854 | |
aa5ae424 SW |
855 | ahub { |
856 | i2s@70080400 { | |
857 | status = "okay"; | |
858 | }; | |
859 | }; | |
860 | ||
8d3207ca | 861 | sdhci@78000400 { |
3325f1bc | 862 | cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; |
8d3207ca RK |
863 | bus-width = <4>; |
864 | status = "okay"; | |
865 | }; | |
866 | ||
867 | sdhci@78000600 { | |
868 | bus-width = <8>; | |
869 | status = "okay"; | |
7a2617a6 | 870 | non-removable; |
8d3207ca RK |
871 | }; |
872 | ||
7021d122 JL |
873 | clocks { |
874 | compatible = "simple-bus"; | |
875 | #address-cells = <1>; | |
876 | #size-cells = <0>; | |
877 | ||
878 | clk32k_in: clock { | |
879 | compatible = "fixed-clock"; | |
880 | reg=<0>; | |
881 | #clock-cells = <0>; | |
882 | clock-frequency = <32768>; | |
883 | }; | |
884 | }; | |
81c6c56c LD |
885 | |
886 | regulators { | |
887 | compatible = "simple-bus"; | |
888 | #address-cells = <1>; | |
889 | #size-cells = <0>; | |
890 | ||
891 | vdd_ac_bat_reg: regulator@0 { | |
892 | compatible = "regulator-fixed"; | |
893 | reg = <0>; | |
894 | regulator-name = "vdd_ac_bat"; | |
895 | regulator-min-microvolt = <5000000>; | |
896 | regulator-max-microvolt = <5000000>; | |
897 | regulator-always-on; | |
898 | }; | |
fcf0b3a6 LD |
899 | |
900 | dvdd_ts_reg: regulator@1 { | |
901 | compatible = "regulator-fixed"; | |
902 | reg = <1>; | |
903 | regulator-name = "dvdd_ts"; | |
904 | regulator-min-microvolt = <1800000>; | |
905 | regulator-max-microvolt = <1800000>; | |
906 | enable-active-high; | |
3325f1bc | 907 | gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>; |
fcf0b3a6 LD |
908 | }; |
909 | ||
910 | lcd_bl_en_reg: regulator@2 { | |
911 | compatible = "regulator-fixed"; | |
912 | reg = <2>; | |
913 | regulator-name = "lcd_bl_en"; | |
914 | regulator-min-microvolt = <5000000>; | |
915 | regulator-max-microvolt = <5000000>; | |
916 | enable-active-high; | |
3325f1bc | 917 | gpio = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; |
fcf0b3a6 LD |
918 | }; |
919 | ||
920 | usb1_vbus_reg: regulator@3 { | |
921 | compatible = "regulator-fixed"; | |
922 | reg = <3>; | |
923 | regulator-name = "usb1_vbus"; | |
924 | regulator-min-microvolt = <5000000>; | |
925 | regulator-max-microvolt = <5000000>; | |
926 | enable-active-high; | |
3325f1bc | 927 | gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; |
fcf0b3a6 LD |
928 | gpio-open-drain; |
929 | vin-supply = <&tps65090_dcdc1_reg>; | |
930 | }; | |
931 | ||
932 | usb3_vbus_reg: regulator@4 { | |
933 | compatible = "regulator-fixed"; | |
934 | reg = <4>; | |
935 | regulator-name = "usb2_vbus"; | |
936 | regulator-min-microvolt = <5000000>; | |
937 | regulator-max-microvolt = <5000000>; | |
938 | enable-active-high; | |
3325f1bc | 939 | gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; |
fcf0b3a6 LD |
940 | gpio-open-drain; |
941 | vin-supply = <&tps65090_dcdc1_reg>; | |
942 | }; | |
943 | ||
944 | vdd_hdmi_reg: regulator@5 { | |
945 | compatible = "regulator-fixed"; | |
946 | reg = <5>; | |
947 | regulator-name = "vdd_hdmi_5v0"; | |
948 | regulator-min-microvolt = <5000000>; | |
949 | regulator-max-microvolt = <5000000>; | |
950 | enable-active-high; | |
3325f1bc | 951 | gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; |
fcf0b3a6 LD |
952 | vin-supply = <&tps65090_dcdc1_reg>; |
953 | }; | |
81c6c56c | 954 | }; |
aa5ae424 SW |
955 | |
956 | sound { | |
957 | compatible = "nvidia,tegra-audio-rt5640-dalmore", | |
958 | "nvidia,tegra-audio-rt5640"; | |
959 | nvidia,model = "NVIDIA Tegra Dalmore"; | |
960 | ||
961 | nvidia,audio-routing = | |
962 | "Headphones", "HPOR", | |
963 | "Headphones", "HPOL", | |
964 | "Speakers", "SPORP", | |
965 | "Speakers", "SPORN", | |
966 | "Speakers", "SPOLP", | |
967 | "Speakers", "SPOLN"; | |
968 | ||
969 | nvidia,i2s-controller = <&tegra_i2s1>; | |
970 | nvidia,audio-codec = <&rt5640>; | |
971 | ||
972 | nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>; | |
973 | ||
974 | clocks = <&tegra_car TEGRA114_CLK_PLL_A>, | |
975 | <&tegra_car TEGRA114_CLK_PLL_A_OUT0>, | |
976 | <&tegra_car TEGRA114_CLK_EXTERN1>; | |
977 | clock-names = "pll_a", "pll_a_out0", "mclk"; | |
978 | }; | |
a71c03e7 | 979 | }; |