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ARM: tegra: Add Tegra114 gr3d support
[deliverable/linux.git] / arch / arm / boot / dts / tegra114-dalmore.dts
CommitLineData
a71c03e7
HD		 1/dts-v1/;
2
e6e646e6 3#include <dt-bindings/input/input.h>
1bd0bd49 4#include "tegra114.dtsi"
a71c03e7
HD		 5
6/ {
7 model = "NVIDIA Tegra114 Dalmore evaluation board";
8 compatible = "nvidia,dalmore", "nvidia,tegra114";
9
553c0a20
SW		 10 aliases {
11 rtc0 = "/i2c@7000d000/tps65913@58";
12 rtc1 = "/rtc@7000e000";
13 };
14
a71c03e7
HD		 15 memory {
16 reg = <0x80000000 0x40000000>;
17 };
18
58ecb23f 19 pinmux@70000868 {
2c314d5c
PR		 20 pinctrl-names = "default";
21 pinctrl-0 = <&state_default>;
22
23 state_default: pinmux {
24 clk1_out_pw4 {
25 nvidia,pins = "clk1_out_pw4";
26 nvidia,function = "extperiph1";
5fc6b0dd
LD		 27 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
28 nvidia,tristate = <TEGRA_PIN_DISABLE>;
29 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 30 };
31 dap1_din_pn1 {
32 nvidia,pins = "dap1_din_pn1";
33 nvidia,function = "i2s0";
5fc6b0dd
LD		 34 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
35 nvidia,tristate = <TEGRA_PIN_ENABLE>;
36 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 37 };
38 dap1_dout_pn2 {
39 nvidia,pins = "dap1_dout_pn2",
40 "dap1_fs_pn0",
41 "dap1_sclk_pn3";
42 nvidia,function = "i2s0";
5fc6b0dd
LD		 43 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
44 nvidia,tristate = <TEGRA_PIN_DISABLE>;
45 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 46 };
47 dap2_din_pa4 {
48 nvidia,pins = "dap2_din_pa4";
49 nvidia,function = "i2s1";
5fc6b0dd
LD		 50 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
51 nvidia,tristate = <TEGRA_PIN_ENABLE>;
52 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 53 };
54 dap2_dout_pa5 {
55 nvidia,pins = "dap2_dout_pa5",
56 "dap2_fs_pa2",
57 "dap2_sclk_pa3";
58 nvidia,function = "i2s1";
5fc6b0dd
LD		 59 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
60 nvidia,tristate = <TEGRA_PIN_DISABLE>;
61 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 62 };
63 dap4_din_pp5 {
64 nvidia,pins = "dap4_din_pp5",
65 "dap4_dout_pp6",
66 "dap4_fs_pp4",
67 "dap4_sclk_pp7";
68 nvidia,function = "i2s3";
5fc6b0dd
LD		 69 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
70 nvidia,tristate = <TEGRA_PIN_DISABLE>;
71 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 72 };
73 dvfs_pwm_px0 {
74 nvidia,pins = "dvfs_pwm_px0",
75 "dvfs_clk_px2";
76 nvidia,function = "cldvfs";
5fc6b0dd
LD		 77 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
78 nvidia,tristate = <TEGRA_PIN_DISABLE>;
79 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 80 };
81 ulpi_clk_py0 {
82 nvidia,pins = "ulpi_clk_py0",
83 "ulpi_data0_po1",
84 "ulpi_data1_po2",
85 "ulpi_data2_po3",
86 "ulpi_data3_po4",
87 "ulpi_data4_po5",
88 "ulpi_data5_po6",
89 "ulpi_data6_po7",
90 "ulpi_data7_po0";
91 nvidia,function = "ulpi";
5fc6b0dd
LD		 92 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
93 nvidia,tristate = <TEGRA_PIN_DISABLE>;
94 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 95 };
96 ulpi_dir_py1 {
97 nvidia,pins = "ulpi_dir_py1",
98 "ulpi_nxt_py2";
99 nvidia,function = "ulpi";
5fc6b0dd
LD		 100 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
101 nvidia,tristate = <TEGRA_PIN_ENABLE>;
102 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 103 };
104 ulpi_stp_py3 {
105 nvidia,pins = "ulpi_stp_py3";
106 nvidia,function = "ulpi";
5fc6b0dd
LD		 107 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
108 nvidia,tristate = <TEGRA_PIN_DISABLE>;
109 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 110 };
111 cam_i2c_scl_pbb1 {
112 nvidia,pins = "cam_i2c_scl_pbb1",
113 "cam_i2c_sda_pbb2";
114 nvidia,function = "i2c3";
5fc6b0dd
LD		 115 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
116 nvidia,tristate = <TEGRA_PIN_DISABLE>;
117 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
118 nvidia,lock = <TEGRA_PIN_DISABLE>;
119 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 120 };
121 cam_mclk_pcc0 {
122 nvidia,pins = "cam_mclk_pcc0",
123 "pbb0";
124 nvidia,function = "vi_alt3";
5fc6b0dd
LD		 125 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
126 nvidia,tristate = <TEGRA_PIN_DISABLE>;
127 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
128 nvidia,lock = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 129 };
130 gen2_i2c_scl_pt5 {
131 nvidia,pins = "gen2_i2c_scl_pt5",
132 "gen2_i2c_sda_pt6";
133 nvidia,function = "i2c2";
5fc6b0dd
LD		 134 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
135 nvidia,tristate = <TEGRA_PIN_DISABLE>;
136 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
137 nvidia,lock = <TEGRA_PIN_DISABLE>;
138 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 139 };
140 gmi_a16_pj7 {
141 nvidia,pins = "gmi_a16_pj7";
142 nvidia,function = "uartd";
5fc6b0dd
LD		 143 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
144 nvidia,tristate = <TEGRA_PIN_DISABLE>;
145 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 146 };
147 gmi_a17_pb0 {
148 nvidia,pins = "gmi_a17_pb0",
149 "gmi_a18_pb1";
150 nvidia,function = "uartd";
5fc6b0dd
LD		 151 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
152 nvidia,tristate = <TEGRA_PIN_ENABLE>;
153 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 154 };
155 gmi_a19_pk7 {
156 nvidia,pins = "gmi_a19_pk7";
157 nvidia,function = "uartd";
5fc6b0dd
LD		 158 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
159 nvidia,tristate = <TEGRA_PIN_DISABLE>;
160 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 161 };
162 gmi_ad5_pg5 {
163 nvidia,pins = "gmi_ad5_pg5",
164 "gmi_cs6_n_pi3",
165 "gmi_wr_n_pi0";
166 nvidia,function = "spi4";
5fc6b0dd
LD		 167 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
168 nvidia,tristate = <TEGRA_PIN_DISABLE>;
169 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 170 };
171 gmi_ad6_pg6 {
172 nvidia,pins = "gmi_ad6_pg6",
173 "gmi_ad7_pg7";
174 nvidia,function = "spi4";
5fc6b0dd
LD		 175 nvidia,pull = <TEGRA_PIN_PULL_UP>;
176 nvidia,tristate = <TEGRA_PIN_DISABLE>;
177 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 178 };
179 gmi_ad12_ph4 {
180 nvidia,pins = "gmi_ad12_ph4";
181 nvidia,function = "rsvd4";
5fc6b0dd
LD		 182 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
183 nvidia,tristate = <TEGRA_PIN_DISABLE>;
184 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 185 };
186 gmi_ad9_ph1 {
187 nvidia,pins = "gmi_ad9_ph1";
188 nvidia,function = "pwm1";
5fc6b0dd
LD		 189 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
190 nvidia,tristate = <TEGRA_PIN_DISABLE>;
191 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 192 };
193 gmi_cs1_n_pj2 {
194 nvidia,pins = "gmi_cs1_n_pj2",
195 "gmi_oe_n_pi1";
196 nvidia,function = "soc";
5fc6b0dd
LD		 197 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
198 nvidia,tristate = <TEGRA_PIN_ENABLE>;
199 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 200 };
201 clk2_out_pw5 {
202 nvidia,pins = "clk2_out_pw5";
203 nvidia,function = "extperiph2";
5fc6b0dd
LD		 204 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
205 nvidia,tristate = <TEGRA_PIN_DISABLE>;
206 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 207 };
208 sdmmc1_clk_pz0 {
209 nvidia,pins = "sdmmc1_clk_pz0";
210 nvidia,function = "sdmmc1";
5fc6b0dd
LD		 211 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
212 nvidia,tristate = <TEGRA_PIN_DISABLE>;
213 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 214 };
215 sdmmc1_cmd_pz1 {
216 nvidia,pins = "sdmmc1_cmd_pz1",
217 "sdmmc1_dat0_py7",
218 "sdmmc1_dat1_py6",
219 "sdmmc1_dat2_py5",
220 "sdmmc1_dat3_py4";
221 nvidia,function = "sdmmc1";
5fc6b0dd
LD		 222 nvidia,pull = <TEGRA_PIN_PULL_UP>;
223 nvidia,tristate = <TEGRA_PIN_DISABLE>;
224 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 225 };
226 sdmmc1_wp_n_pv3 {
227 nvidia,pins = "sdmmc1_wp_n_pv3";
228 nvidia,function = "spi4";
5fc6b0dd
LD		 229 nvidia,pull = <TEGRA_PIN_PULL_UP>;
230 nvidia,tristate = <TEGRA_PIN_DISABLE>;
231 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 232 };
233 sdmmc3_clk_pa6 {
234 nvidia,pins = "sdmmc3_clk_pa6";
235 nvidia,function = "sdmmc3";
5fc6b0dd
LD		 236 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
237 nvidia,tristate = <TEGRA_PIN_DISABLE>;
238 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 239 };
240 sdmmc3_cmd_pa7 {
241 nvidia,pins = "sdmmc3_cmd_pa7",
242 "sdmmc3_dat0_pb7",
243 "sdmmc3_dat1_pb6",
244 "sdmmc3_dat2_pb5",
245 "sdmmc3_dat3_pb4",
246 "kb_col4_pq4",
247 "sdmmc3_clk_lb_out_pee4",
248 "sdmmc3_clk_lb_in_pee5";
249 nvidia,function = "sdmmc3";
5fc6b0dd
LD		 250 nvidia,pull = <TEGRA_PIN_PULL_UP>;
251 nvidia,tristate = <TEGRA_PIN_DISABLE>;
252 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 253 };
254 sdmmc4_clk_pcc4 {
255 nvidia,pins = "sdmmc4_clk_pcc4";
256 nvidia,function = "sdmmc4";
5fc6b0dd
LD		 257 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
258 nvidia,tristate = <TEGRA_PIN_DISABLE>;
259 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 260 };
261 sdmmc4_cmd_pt7 {
262 nvidia,pins = "sdmmc4_cmd_pt7",
263 "sdmmc4_dat0_paa0",
264 "sdmmc4_dat1_paa1",
265 "sdmmc4_dat2_paa2",
266 "sdmmc4_dat3_paa3",
267 "sdmmc4_dat4_paa4",
268 "sdmmc4_dat5_paa5",
269 "sdmmc4_dat6_paa6",
270 "sdmmc4_dat7_paa7";
271 nvidia,function = "sdmmc4";
5fc6b0dd
LD		 272 nvidia,pull = <TEGRA_PIN_PULL_UP>;
273 nvidia,tristate = <TEGRA_PIN_DISABLE>;
274 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 275 };
276 clk_32k_out_pa0 {
277 nvidia,pins = "clk_32k_out_pa0";
278 nvidia,function = "blink";
5fc6b0dd
LD		 279 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
280 nvidia,tristate = <TEGRA_PIN_DISABLE>;
281 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 282 };
283 kb_col0_pq0 {
284 nvidia,pins = "kb_col0_pq0",
285 "kb_col1_pq1",
286 "kb_col2_pq2",
287 "kb_row0_pr0",
288 "kb_row1_pr1",
289 "kb_row2_pr2";
290 nvidia,function = "kbc";
5fc6b0dd
LD		 291 nvidia,pull = <TEGRA_PIN_PULL_UP>;
292 nvidia,tristate = <TEGRA_PIN_DISABLE>;
293 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 294 };
295 dap3_din_pp1 {
296 nvidia,pins = "dap3_din_pp1",
297 "dap3_sclk_pp3";
298 nvidia,function = "displayb";
5fc6b0dd
LD		 299 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
300 nvidia,tristate = <TEGRA_PIN_ENABLE>;
301 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 302 };
303 pv0 {
304 nvidia,pins = "pv0";
305 nvidia,function = "rsvd4";
5fc6b0dd
LD		 306 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
307 nvidia,tristate = <TEGRA_PIN_ENABLE>;
308 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 309 };
310 kb_row7_pr7 {
311 nvidia,pins = "kb_row7_pr7";
312 nvidia,function = "rsvd2";
5fc6b0dd
LD		 313 nvidia,pull = <TEGRA_PIN_PULL_UP>;
314 nvidia,tristate = <TEGRA_PIN_DISABLE>;
315 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 316 };
317 kb_row10_ps2 {
318 nvidia,pins = "kb_row10_ps2";
319 nvidia,function = "uarta";
5fc6b0dd
LD		 320 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
321 nvidia,tristate = <TEGRA_PIN_ENABLE>;
322 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 323 };
324 kb_row9_ps1 {
325 nvidia,pins = "kb_row9_ps1";
326 nvidia,function = "uarta";
5fc6b0dd
LD		 327 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
328 nvidia,tristate = <TEGRA_PIN_DISABLE>;
329 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 330 };
331 pwr_i2c_scl_pz6 {
332 nvidia,pins = "pwr_i2c_scl_pz6",
333 "pwr_i2c_sda_pz7";
334 nvidia,function = "i2cpwr";
5fc6b0dd
LD		 335 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
336 nvidia,tristate = <TEGRA_PIN_DISABLE>;
337 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
338 nvidia,lock = <TEGRA_PIN_DISABLE>;
339 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 340 };
341 sys_clk_req_pz5 {
342 nvidia,pins = "sys_clk_req_pz5";
343 nvidia,function = "sysclk";
5fc6b0dd
LD		 344 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
345 nvidia,tristate = <TEGRA_PIN_DISABLE>;
346 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 347 };
348 core_pwr_req {
349 nvidia,pins = "core_pwr_req";
350 nvidia,function = "pwron";
5fc6b0dd
LD		 351 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
352 nvidia,tristate = <TEGRA_PIN_DISABLE>;
353 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 354 };
355 cpu_pwr_req {
356 nvidia,pins = "cpu_pwr_req";
357 nvidia,function = "cpu";
5fc6b0dd
LD		 358 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
359 nvidia,tristate = <TEGRA_PIN_DISABLE>;
360 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 361 };
362 pwr_int_n {
363 nvidia,pins = "pwr_int_n";
364 nvidia,function = "pmi";
5fc6b0dd
LD		 365 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
366 nvidia,tristate = <TEGRA_PIN_ENABLE>;
367 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 368 };
369 reset_out_n {
370 nvidia,pins = "reset_out_n";
371 nvidia,function = "reset_out_n";
5fc6b0dd
LD		 372 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
373 nvidia,tristate = <TEGRA_PIN_DISABLE>;
374 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 375 };
376 clk3_out_pee0 {
377 nvidia,pins = "clk3_out_pee0";
378 nvidia,function = "extperiph3";
5fc6b0dd
LD		 379 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
380 nvidia,tristate = <TEGRA_PIN_DISABLE>;
381 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 382 };
383 gen1_i2c_scl_pc4 {
384 nvidia,pins = "gen1_i2c_scl_pc4",
385 "gen1_i2c_sda_pc5";
386 nvidia,function = "i2c1";
5fc6b0dd
LD		 387 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
388 nvidia,tristate = <TEGRA_PIN_DISABLE>;
389 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
390 nvidia,lock = <TEGRA_PIN_DISABLE>;
391 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 392 };
393 uart2_cts_n_pj5 {
394 nvidia,pins = "uart2_cts_n_pj5";
395 nvidia,function = "uartb";
5fc6b0dd
LD		 396 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
397 nvidia,tristate = <TEGRA_PIN_ENABLE>;
398 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 399 };
400 uart2_rts_n_pj6 {
401 nvidia,pins = "uart2_rts_n_pj6";
402 nvidia,function = "uartb";
5fc6b0dd
LD		 403 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
404 nvidia,tristate = <TEGRA_PIN_DISABLE>;
405 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 406 };
407 uart2_rxd_pc3 {
408 nvidia,pins = "uart2_rxd_pc3";
409 nvidia,function = "irda";
5fc6b0dd
LD		 410 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
411 nvidia,tristate = <TEGRA_PIN_ENABLE>;
412 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 413 };
414 uart2_txd_pc2 {
415 nvidia,pins = "uart2_txd_pc2";
416 nvidia,function = "irda";
5fc6b0dd
LD		 417 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
418 nvidia,tristate = <TEGRA_PIN_DISABLE>;
419 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 420 };
421 uart3_cts_n_pa1 {
422 nvidia,pins = "uart3_cts_n_pa1",
423 "uart3_rxd_pw7";
424 nvidia,function = "uartc";
5fc6b0dd
LD		 425 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
426 nvidia,tristate = <TEGRA_PIN_ENABLE>;
427 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 428 };
429 uart3_rts_n_pc0 {
430 nvidia,pins = "uart3_rts_n_pc0",
431 "uart3_txd_pw6";
432 nvidia,function = "uartc";
5fc6b0dd
LD		 433 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
434 nvidia,tristate = <TEGRA_PIN_DISABLE>;
435 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 436 };
437 owr {
438 nvidia,pins = "owr";
439 nvidia,function = "owr";
5fc6b0dd
LD		 440 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
441 nvidia,tristate = <TEGRA_PIN_DISABLE>;
442 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 443 };
444 hdmi_cec_pee3 {
445 nvidia,pins = "hdmi_cec_pee3";
446 nvidia,function = "cec";
5fc6b0dd
LD		 447 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
448 nvidia,tristate = <TEGRA_PIN_DISABLE>;
449 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
450 nvidia,lock = <TEGRA_PIN_DISABLE>;
451 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 452 };
453 ddc_scl_pv4 {
454 nvidia,pins = "ddc_scl_pv4",
455 "ddc_sda_pv5";
456 nvidia,function = "i2c4";
5fc6b0dd
LD		 457 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
458 nvidia,tristate = <TEGRA_PIN_DISABLE>;
459 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
460 nvidia,lock = <TEGRA_PIN_DISABLE>;
461 nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 462 };
463 spdif_in_pk6 {
464 nvidia,pins = "spdif_in_pk6";
465 nvidia,function = "usb";
5fc6b0dd
LD		 466 nvidia,pull = <TEGRA_PIN_PULL_UP>;
467 nvidia,tristate = <TEGRA_PIN_DISABLE>;
468 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
469 nvidia,lock = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 470 };
471 usb_vbus_en0_pn4 {
472 nvidia,pins = "usb_vbus_en0_pn4";
473 nvidia,function = "usb";
5fc6b0dd
LD		 474 nvidia,pull = <TEGRA_PIN_PULL_UP>;
475 nvidia,tristate = <TEGRA_PIN_DISABLE>;
476 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
477 nvidia,lock = <TEGRA_PIN_DISABLE>;
478 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 479 };
480 gpio_x6_aud_px6 {
481 nvidia,pins = "gpio_x6_aud_px6";
482 nvidia,function = "spi6";
5fc6b0dd
LD		 483 nvidia,pull = <TEGRA_PIN_PULL_UP>;
484 nvidia,tristate = <TEGRA_PIN_ENABLE>;
485 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 486 };
487 gpio_x4_aud_px4 {
488 nvidia,pins = "gpio_x4_aud_px4",
489 "gpio_x7_aud_px7";
490 nvidia,function = "rsvd1";
5fc6b0dd
LD		 491 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
492 nvidia,tristate = <TEGRA_PIN_DISABLE>;
493 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 494 };
495 gpio_x5_aud_px5 {
496 nvidia,pins = "gpio_x5_aud_px5";
497 nvidia,function = "rsvd1";
5fc6b0dd
LD		 498 nvidia,pull = <TEGRA_PIN_PULL_UP>;
499 nvidia,tristate = <TEGRA_PIN_DISABLE>;
500 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 501 };
502 gpio_w2_aud_pw2 {
503 nvidia,pins = "gpio_w2_aud_pw2";
504 nvidia,function = "rsvd2";
5fc6b0dd
LD		 505 nvidia,pull = <TEGRA_PIN_PULL_UP>;
506 nvidia,tristate = <TEGRA_PIN_DISABLE>;
507 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 508 };
509 gpio_w3_aud_pw3 {
510 nvidia,pins = "gpio_w3_aud_pw3";
511 nvidia,function = "spi6";
5fc6b0dd
LD		 512 nvidia,pull = <TEGRA_PIN_PULL_UP>;
513 nvidia,tristate = <TEGRA_PIN_DISABLE>;
514 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 515 };
516 gpio_x1_aud_px1 {
517 nvidia,pins = "gpio_x1_aud_px1";
518 nvidia,function = "rsvd4";
5fc6b0dd
LD		 519 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
520 nvidia,tristate = <TEGRA_PIN_DISABLE>;
521 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 522 };
523 gpio_x3_aud_px3 {
524 nvidia,pins = "gpio_x3_aud_px3";
525 nvidia,function = "rsvd4";
5fc6b0dd
LD		 526 nvidia,pull = <TEGRA_PIN_PULL_UP>;
527 nvidia,tristate = <TEGRA_PIN_DISABLE>;
528 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 529 };
530 dap3_fs_pp0 {
531 nvidia,pins = "dap3_fs_pp0";
532 nvidia,function = "i2s2";
5fc6b0dd
LD		 533 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
534 nvidia,tristate = <TEGRA_PIN_DISABLE>;
535 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 536 };
537 dap3_dout_pp2 {
538 nvidia,pins = "dap3_dout_pp2";
539 nvidia,function = "i2s2";
5fc6b0dd
LD		 540 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
541 nvidia,tristate = <TEGRA_PIN_DISABLE>;
542 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 543 };
544 pv1 {
545 nvidia,pins = "pv1";
546 nvidia,function = "rsvd1";
5fc6b0dd
LD		 547 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
548 nvidia,tristate = <TEGRA_PIN_DISABLE>;
549 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 550 };
551 pbb3 {
552 nvidia,pins = "pbb3",
553 "pbb5",
554 "pbb6",
555 "pbb7";
556 nvidia,function = "rsvd4";
5fc6b0dd
LD		 557 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
558 nvidia,tristate = <TEGRA_PIN_DISABLE>;
559 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 560 };
561 pcc1 {
562 nvidia,pins = "pcc1",
563 "pcc2";
564 nvidia,function = "rsvd4";
5fc6b0dd
LD		 565 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
566 nvidia,tristate = <TEGRA_PIN_DISABLE>;
567 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 568 };
569 gmi_ad0_pg0 {
570 nvidia,pins = "gmi_ad0_pg0",
571 "gmi_ad1_pg1";
572 nvidia,function = "gmi";
5fc6b0dd
LD		 573 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
574 nvidia,tristate = <TEGRA_PIN_DISABLE>;
575 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 576 };
577 gmi_ad10_ph2 {
578 nvidia,pins = "gmi_ad10_ph2",
579 "gmi_ad11_ph3",
580 "gmi_ad13_ph5",
581 "gmi_ad8_ph0",
582 "gmi_clk_pk1";
583 nvidia,function = "gmi";
5fc6b0dd
LD		 584 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
585 nvidia,tristate = <TEGRA_PIN_DISABLE>;
586 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 587 };
588 gmi_ad2_pg2 {
589 nvidia,pins = "gmi_ad2_pg2",
590 "gmi_ad3_pg3";
591 nvidia,function = "gmi";
5fc6b0dd
LD		 592 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
593 nvidia,tristate = <TEGRA_PIN_DISABLE>;
594 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 595 };
596 gmi_adv_n_pk0 {
597 nvidia,pins = "gmi_adv_n_pk0",
598 "gmi_cs0_n_pj0",
599 "gmi_cs2_n_pk3",
600 "gmi_cs4_n_pk2",
601 "gmi_cs7_n_pi6",
602 "gmi_dqs_p_pj3",
603 "gmi_iordy_pi5",
604 "gmi_wp_n_pc7";
605 nvidia,function = "gmi";
5fc6b0dd
LD		 606 nvidia,pull = <TEGRA_PIN_PULL_UP>;
607 nvidia,tristate = <TEGRA_PIN_DISABLE>;
608 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 609 };
610 gmi_cs3_n_pk4 {
611 nvidia,pins = "gmi_cs3_n_pk4";
612 nvidia,function = "gmi";
5fc6b0dd
LD		 613 nvidia,pull = <TEGRA_PIN_PULL_UP>;
614 nvidia,tristate = <TEGRA_PIN_DISABLE>;
615 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 616 };
617 clk2_req_pcc5 {
618 nvidia,pins = "clk2_req_pcc5";
619 nvidia,function = "rsvd4";
5fc6b0dd
LD		 620 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
621 nvidia,tristate = <TEGRA_PIN_DISABLE>;
622 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 623 };
624 kb_col3_pq3 {
625 nvidia,pins = "kb_col3_pq3",
626 "kb_col6_pq6",
627 "kb_col7_pq7";
628 nvidia,function = "kbc";
5fc6b0dd
LD		 629 nvidia,pull = <TEGRA_PIN_PULL_UP>;
630 nvidia,tristate = <TEGRA_PIN_DISABLE>;
631 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 632 };
633 kb_col5_pq5 {
634 nvidia,pins = "kb_col5_pq5";
635 nvidia,function = "kbc";
5fc6b0dd
LD		 636 nvidia,pull = <TEGRA_PIN_PULL_UP>;
637 nvidia,tristate = <TEGRA_PIN_DISABLE>;
638 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 639 };
640 kb_row3_pr3 {
641 nvidia,pins = "kb_row3_pr3",
642 "kb_row4_pr4",
643 "kb_row6_pr6",
644 "kb_row8_ps0";
645 nvidia,function = "kbc";
5fc6b0dd
LD		 646 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
647 nvidia,tristate = <TEGRA_PIN_DISABLE>;
648 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 649 };
650 clk3_req_pee1 {
651 nvidia,pins = "clk3_req_pee1";
652 nvidia,function = "rsvd4";
5fc6b0dd
LD		 653 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
654 nvidia,tristate = <TEGRA_PIN_DISABLE>;
655 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 656 };
657 pu4 {
658 nvidia,pins = "pu4";
659 nvidia,function = "displayb";
5fc6b0dd
LD		 660 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
661 nvidia,tristate = <TEGRA_PIN_DISABLE>;
662 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 663 };
664 pu5 {
665 nvidia,pins = "pu5",
666 "pu6";
667 nvidia,function = "displayb";
5fc6b0dd
LD		 668 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
669 nvidia,tristate = <TEGRA_PIN_DISABLE>;
670 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 671 };
672 hdmi_int_pn7 {
673 nvidia,pins = "hdmi_int_pn7";
674 nvidia,function = "rsvd1";
5fc6b0dd
LD		 675 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
676 nvidia,tristate = <TEGRA_PIN_DISABLE>;
677 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2c314d5c
PR		 678 };
679 clk1_req_pee2 {
680 nvidia,pins = "clk1_req_pee2",
681 "usb_vbus_en1_pn5";
682 nvidia,function = "rsvd4";
5fc6b0dd
LD		 683 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
684 nvidia,tristate = <TEGRA_PIN_ENABLE>;
685 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2c314d5c
PR		 686 };
687
688 drive_sdio1 {
689 nvidia,pins = "drive_sdio1";
5fc6b0dd
LD		 690 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
691 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
692 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
2c314d5c
PR		 693 nvidia,pull-down-strength = <36>;
694 nvidia,pull-up-strength = <20>;
5fc6b0dd
LD		 695 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>;
696 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>;
2c314d5c
PR		 697 };
698 drive_sdio3 {
699 nvidia,pins = "drive_sdio3";
5fc6b0dd
LD		 700 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
701 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
702 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
2c314d5c
PR		 703 nvidia,pull-down-strength = <22>;
704 nvidia,pull-up-strength = <36>;
5fc6b0dd
LD		 705 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
706 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
2c314d5c
PR		 707 };
708 drive_gma {
709 nvidia,pins = "drive_gma";
5fc6b0dd
LD		 710 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
711 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
712 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
2c314d5c
PR		 713 nvidia,pull-down-strength = <2>;
714 nvidia,pull-up-strength = <1>;
5fc6b0dd
LD		 715 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
716 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
2c314d5c
PR		 717 nvidia,drive-type = <1>;
718 };
719 };
720 };
721
a71c03e7
HD		 722 serial@70006300 {
723 status = "okay";
a71c03e7
HD		 724 };
725
33eb271e
RK		 726 i2c@7000c000 {
727 status = "okay";
728 clock-frequency = <100000>;
729
58ecb23f 730 battery: smart-battery@b {
33eb271e
RK		 731 compatible = "ti,bq20z45", "sbs,sbs-battery";
732 reg = <0xb>;
733 battery-name = "battery";
734 sbs,i2c-retry-count = <2>;
735 sbs,poll-retry-count = <100>;
d5284a67 736 power-supplies = <&charger>;
33eb271e 737 };
aa5ae424 738
58ecb23f 739 rt5640: rt5640@1c {
aa5ae424
SW		 740 compatible = "realtek,rt5640";
741 reg = <0x1c>;
742 interrupt-parent = <&gpio>;
743 interrupts = <TEGRA_GPIO(W, 3) GPIO_ACTIVE_HIGH>;
744 realtek,ldo1-en-gpios =
745 <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
746 };
99bda7b9
WN		 747
748 temperature-sensor@4c {
749 compatible = "onnn,nct1008";
750 reg = <0x4c>;
751 vcc-supply = <&palmas_ldo6_reg>;
752 interrupt-parent = <&gpio>;
753 interrupts = <TEGRA_GPIO(O, 4) IRQ_TYPE_LEVEL_LOW>;
754 };
33eb271e
RK		 755 };
756
da204ee2
LD		 757 i2c@7000d000 {
758 status = "okay";
759 clock-frequency = <400000>;
760
58ecb23f 761 tps51632@43 {
da204ee2
LD		 762 compatible = "ti,tps51632";
763 reg = <0x43>;
764 regulator-name = "vdd-cpu";
765 regulator-min-microvolt = <500000>;
766 regulator-max-microvolt = <1520000>;
767 regulator-boot-on;
768 regulator-always-on;
769 };
81c6c56c 770
58ecb23f 771 tps65090@48 {
81c6c56c
LD		 772 compatible = "ti,tps65090";
773 reg = <0x48>;
774 interrupt-parent = <&gpio>;
6cecf916 775 interrupts = <TEGRA_GPIO(J, 0) IRQ_TYPE_LEVEL_HIGH>;
81c6c56c
LD		 776
777 vsys1-supply = <&vdd_ac_bat_reg>;
778 vsys2-supply = <&vdd_ac_bat_reg>;
779 vsys3-supply = <&vdd_ac_bat_reg>;
780 infet1-supply = <&vdd_ac_bat_reg>;
781 infet2-supply = <&vdd_ac_bat_reg>;
782 infet3-supply = <&tps65090_dcdc2_reg>;
783 infet4-supply = <&tps65090_dcdc2_reg>;
784 infet5-supply = <&tps65090_dcdc2_reg>;
785 infet6-supply = <&tps65090_dcdc2_reg>;
786 infet7-supply = <&tps65090_dcdc2_reg>;
787 vsys-l1-supply = <&vdd_ac_bat_reg>;
788 vsys-l2-supply = <&vdd_ac_bat_reg>;
789
d5284a67 790 charger: charger {
1a99ece9
RK		 791 compatible = "ti,tps65090-charger";
792 ti,enable-low-current-chrg;
793 };
794
81c6c56c 795 regulators {
fcf0b3a6 796 tps65090_dcdc1_reg: dcdc1 {
81c6c56c
LD		 797 regulator-name = "vdd-sys-5v0";
798 regulator-always-on;
799 regulator-boot-on;
800 };
801
802 tps65090_dcdc2_reg: dcdc2 {
803 regulator-name = "vdd-sys-3v3";
804 regulator-always-on;
805 regulator-boot-on;
806 };
807
c321d968 808 tps65090_dcdc3_reg: dcdc3 {
81c6c56c
LD		 809 regulator-name = "vdd-ao";
810 regulator-always-on;
811 regulator-boot-on;
812 };
813
814 fet1 {
815 regulator-name = "vdd-lcd-bl";
816 };
817
818 fet3 {
819 regulator-name = "vdd-modem-3v3";
820 };
821
822 fet4 {
823 regulator-name = "avdd-lcd";
824 };
825
826 fet5 {
827 regulator-name = "vdd-lvds";
828 };
829
830 fet6 {
831 regulator-name = "vdd-sd-slot";
15d5ef4d 832 regulator-always-on;
81c6c56c
LD		 833 regulator-boot-on;
834 };
835
836 fet7 {
837 regulator-name = "vdd-com-3v3";
838 };
839
840 ldo1 {
841 regulator-name = "vdd-sby-5v0";
842 regulator-always-on;
843 regulator-boot-on;
844 };
845
846 ldo2 {
847 regulator-name = "vdd-sby-3v3";
848 regulator-always-on;
849 regulator-boot-on;
850 };
851 };
852 };
c321d968 853
58ecb23f 854 palmas: tps65913@58 {
c321d968
LD		 855 compatible = "ti,palmas";
856 reg = <0x58>;
eca8f98e 857 interrupts = <0 86 IRQ_TYPE_LEVEL_LOW>;
c321d968
LD		 858
859 #interrupt-cells = <2>;
860 interrupt-controller;
861
27cf5d14
BH		 862 ti,system-power-controller;
863
c321d968
LD		 864 palmas_gpio: gpio {
865 compatible = "ti,palmas-gpio";
866 gpio-controller;
867 #gpio-cells = <2>;
868 };
869
870 pmic {
871 compatible = "ti,tps65913-pmic", "ti,palmas-pmic";
872 smps1-in-supply = <&tps65090_dcdc3_reg>;
873 smps3-in-supply = <&tps65090_dcdc3_reg>;
874 smps4-in-supply = <&tps65090_dcdc2_reg>;
875 smps7-in-supply = <&tps65090_dcdc2_reg>;
876 smps8-in-supply = <&tps65090_dcdc2_reg>;
877 smps9-in-supply = <&tps65090_dcdc2_reg>;
878 ldo1-in-supply = <&tps65090_dcdc2_reg>;
879 ldo2-in-supply = <&tps65090_dcdc2_reg>;
880 ldo3-in-supply = <&palmas_smps3_reg>;
881 ldo4-in-supply = <&tps65090_dcdc2_reg>;
882 ldo5-in-supply = <&vdd_ac_bat_reg>;
883 ldo6-in-supply = <&tps65090_dcdc2_reg>;
884 ldo7-in-supply = <&tps65090_dcdc2_reg>;
885 ldo8-in-supply = <&tps65090_dcdc3_reg>;
886 ldo9-in-supply = <&palmas_smps9_reg>;
887 ldoln-in-supply = <&tps65090_dcdc1_reg>;
888 ldousb-in-supply = <&tps65090_dcdc1_reg>;
889
890 regulators {
891 smps12 {
892 regulator-name = "vddio-ddr";
893 regulator-min-microvolt = <1350000>;
894 regulator-max-microvolt = <1350000>;
895 regulator-always-on;
896 regulator-boot-on;
897 };
898
899 palmas_smps3_reg: smps3 {
900 regulator-name = "vddio-1v8";
901 regulator-min-microvolt = <1800000>;
902 regulator-max-microvolt = <1800000>;
903 regulator-always-on;
904 regulator-boot-on;
905 };
906
907 smps45 {
908 regulator-name = "vdd-core";
909 regulator-min-microvolt = <900000>;
910 regulator-max-microvolt = <1400000>;
911 regulator-always-on;
912 regulator-boot-on;
913 };
914
915 smps457 {
916 regulator-name = "vdd-core";
917 regulator-min-microvolt = <900000>;
918 regulator-max-microvolt = <1400000>;
919 regulator-always-on;
920 regulator-boot-on;
921 };
922
923 smps8 {
924 regulator-name = "avdd-pll";
925 regulator-min-microvolt = <1050000>;
926 regulator-max-microvolt = <1050000>;
927 regulator-always-on;
928 regulator-boot-on;
929 };
930
931 palmas_smps9_reg: smps9 {
932 regulator-name = "sdhci-vdd-sd-slot";
933 regulator-min-microvolt = <2800000>;
934 regulator-max-microvolt = <2800000>;
935 regulator-always-on;
936 };
937
938 ldo1 {
939 regulator-name = "avdd-cam1";
940 regulator-min-microvolt = <2800000>;
941 regulator-max-microvolt = <2800000>;
942 };
943
944 ldo2 {
945 regulator-name = "avdd-cam2";
946 regulator-min-microvolt = <2800000>;
947 regulator-max-microvolt = <2800000>;
948 };
949
950 ldo3 {
951 regulator-name = "avdd-dsi-csi";
952 regulator-min-microvolt = <1200000>;
953 regulator-max-microvolt = <1200000>;
954 regulator-always-on;
955 regulator-boot-on;
956 };
957
958 ldo4 {
959 regulator-name = "vpp-fuse";
960 regulator-min-microvolt = <1800000>;
961 regulator-max-microvolt = <1800000>;
962 };
963
99bda7b9 964 palmas_ldo6_reg: ldo6 {
c321d968
LD		 965 regulator-name = "vdd-sensor-2v85";
966 regulator-min-microvolt = <2850000>;
967 regulator-max-microvolt = <2850000>;
968 };
969
970 ldo7 {
971 regulator-name = "vdd-af-cam1";
972 regulator-min-microvolt = <2800000>;
973 regulator-max-microvolt = <2800000>;
974 };
975
976 ldo8 {
977 regulator-name = "vdd-rtc";
978 regulator-min-microvolt = <900000>;
979 regulator-max-microvolt = <900000>;
980 regulator-always-on;
981 regulator-boot-on;
982 ti,enable-ldo8-tracking;
983 };
984
985 ldo9 {
986 regulator-name = "vddio-sdmmc-2";
987 regulator-min-microvolt = <1800000>;
988 regulator-max-microvolt = <3300000>;
989 regulator-always-on;
990 regulator-boot-on;
991 };
992
993 ldoln {
994 regulator-name = "hvdd-usb";
995 regulator-min-microvolt = <3300000>;
996 regulator-max-microvolt = <3300000>;
997 };
998
999 ldousb {
1000 regulator-name = "avdd-usb";
1001 regulator-min-microvolt = <3300000>;
1002 regulator-max-microvolt = <3300000>;
1003 regulator-always-on;
1004 regulator-boot-on;
1005 };
1006
1007 regen1 {
1008 regulator-name = "rail-3v3";
1009 regulator-max-microvolt = <3300000>;
1010 regulator-always-on;
1011 regulator-boot-on;
1012 };
1013
1014 regen2 {
1015 regulator-name = "rail-5v0";
1016 regulator-max-microvolt = <5000000>;
1017 regulator-always-on;
1018 regulator-boot-on;
1019 };
1020 };
1021 };
1022
1023 rtc {
1024 compatible = "ti,palmas-rtc";
1025 interrupt-parent = <&palmas>;
1026 interrupts = <8 0>;
1027 };
6be3cf72
LD		 1028
1029 pinmux {
1030 compatible = "ti,tps65913-pinctrl";
1031 pinctrl-names = "default";
1032 pinctrl-0 = <&palmas_default>;
1033
1034 palmas_default: pinmux {
1035 pin_gpio6 {
1036 pins = "gpio6";
1037 function = "gpio";
1038 };
1039 };
1040 };
c321d968 1041 };
da204ee2
LD		 1042 };
1043
5cc75fca
LD		 1044 spi@7000da00 {
1045 status = "okay";
1046 spi-max-frequency = <25000000>;
1047 spi-flash@0 {
1048 compatible = "winbond,w25q32dw";
1049 reg = <0>;
1050 spi-max-frequency = <20000000>;
1051 };
1052 };
1053
58ecb23f 1054 pmc@7000e400 {
a71c03e7 1055 nvidia,invert-interrupt;
47d2d63b 1056 nvidia,suspend-mode = <1>;
4a7658fe
JL		 1057 nvidia,cpu-pwr-good-time = <500>;
1058 nvidia,cpu-pwr-off-time = <300>;
1059 nvidia,core-pwr-good-time = <641 3845>;
1060 nvidia,core-pwr-off-time = <61036>;
1061 nvidia,core-power-req-active-high;
1062 nvidia,sys-clock-req-active-high;
a71c03e7 1063 };
7021d122 1064
58ecb23f 1065 ahub@70080000 {
aa5ae424
SW		 1066 i2s@70080400 {
1067 status = "okay";
1068 };
1069 };
1070
8d3207ca 1071 sdhci@78000400 {
3325f1bc 1072 cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
8d3207ca
RK		 1073 bus-width = <4>;
1074 status = "okay";
1075 };
1076
1077 sdhci@78000600 {
1078 bus-width = <8>;
1079 status = "okay";
7a2617a6 1080 non-removable;
8d3207ca
RK		 1081 };
1082
328dc0ec
MP		 1083 usb@7d008000 {
1084 status = "okay";
1085 };
1086
1087 usb-phy@7d008000 {
1088 status = "okay";
1089 vbus-supply = <&usb3_vbus_reg>;
1090 };
1091
7021d122
JL		 1092 clocks {
1093 compatible = "simple-bus";
1094 #address-cells = <1>;
1095 #size-cells = <0>;
1096
58ecb23f 1097 clk32k_in: clock@0 {
7021d122
JL		 1098 compatible = "fixed-clock";
1099 reg=<0>;
1100 #clock-cells = <0>;
1101 clock-frequency = <32768>;
1102 };
1103 };
81c6c56c 1104
21b341ca
LD		 1105 gpio-keys {
1106 compatible = "gpio-keys";
1107
1108 home {
1109 label = "Home";
1110 gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
e6e646e6 1111 linux,code = <KEY_HOME>;
21b341ca
LD		 1112 };
1113
1114 power {
1115 label = "Power";
1116 gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
e6e646e6 1117 linux,code = <KEY_POWER>;
21b341ca
LD		 1118 gpio-key,wakeup;
1119 };
1120
1121 volume_down {
1122 label = "Volume Down";
1123 gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;
e6e646e6 1124 linux,code = <KEY_VOLUMEDOWN>;
21b341ca
LD		 1125 };
1126
1127 volume_up {
1128 label = "Volume Up";
1129 gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>;
e6e646e6 1130 linux,code = <KEY_VOLUMEUP>;
21b341ca
LD		 1131 };
1132 };
1133
81c6c56c
LD		 1134 regulators {
1135 compatible = "simple-bus";
1136 #address-cells = <1>;
1137 #size-cells = <0>;
1138
1139 vdd_ac_bat_reg: regulator@0 {
1140 compatible = "regulator-fixed";
1141 reg = <0>;
1142 regulator-name = "vdd_ac_bat";
1143 regulator-min-microvolt = <5000000>;
1144 regulator-max-microvolt = <5000000>;
1145 regulator-always-on;
1146 };
fcf0b3a6
LD		 1147
1148 dvdd_ts_reg: regulator@1 {
1149 compatible = "regulator-fixed";
1150 reg = <1>;
1151 regulator-name = "dvdd_ts";
1152 regulator-min-microvolt = <1800000>;
1153 regulator-max-microvolt = <1800000>;
1154 enable-active-high;
3325f1bc 1155 gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>;
fcf0b3a6
LD		 1156 };
1157
1158 lcd_bl_en_reg: regulator@2 {
1159 compatible = "regulator-fixed";
1160 reg = <2>;
1161 regulator-name = "lcd_bl_en";
1162 regulator-min-microvolt = <5000000>;
1163 regulator-max-microvolt = <5000000>;
1164 enable-active-high;
3325f1bc 1165 gpio = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
fcf0b3a6
LD		 1166 };
1167
1168 usb1_vbus_reg: regulator@3 {
1169 compatible = "regulator-fixed";
1170 reg = <3>;
1171 regulator-name = "usb1_vbus";
1172 regulator-min-microvolt = <5000000>;
1173 regulator-max-microvolt = <5000000>;
1174 enable-active-high;
3325f1bc 1175 gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
fcf0b3a6
LD		 1176 gpio-open-drain;
1177 vin-supply = <&tps65090_dcdc1_reg>;
1178 };
1179
1180 usb3_vbus_reg: regulator@4 {
1181 compatible = "regulator-fixed";
1182 reg = <4>;
1183 regulator-name = "usb2_vbus";
1184 regulator-min-microvolt = <5000000>;
1185 regulator-max-microvolt = <5000000>;
1186 enable-active-high;
3325f1bc 1187 gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
fcf0b3a6
LD		 1188 gpio-open-drain;
1189 vin-supply = <&tps65090_dcdc1_reg>;
1190 };
1191
1192 vdd_hdmi_reg: regulator@5 {
1193 compatible = "regulator-fixed";
1194 reg = <5>;
1195 regulator-name = "vdd_hdmi_5v0";
1196 regulator-min-microvolt = <5000000>;
1197 regulator-max-microvolt = <5000000>;
1198 enable-active-high;
3325f1bc 1199 gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
fcf0b3a6
LD		 1200 vin-supply = <&tps65090_dcdc1_reg>;
1201 };
c321d968
LD		 1202
1203 vdd_cam_1v8_reg: regulator@6 {
1204 compatible = "regulator-fixed";
1205 reg = <6>;
1206 regulator-name = "vdd_cam_1v8_reg";
1207 regulator-min-microvolt = <1800000>;
1208 regulator-max-microvolt = <1800000>;
1209 enable-active-high;
1210 gpio = <&palmas_gpio 6 0>;
1211 };
81c6c56c 1212 };
aa5ae424
SW		 1213
1214 sound {
1215 compatible = "nvidia,tegra-audio-rt5640-dalmore",
1216 "nvidia,tegra-audio-rt5640";
1217 nvidia,model = "NVIDIA Tegra Dalmore";
1218
1219 nvidia,audio-routing =
1220 "Headphones", "HPOR",
1221 "Headphones", "HPOL",
1222 "Speakers", "SPORP",
1223 "Speakers", "SPORN",
1224 "Speakers", "SPOLP",
8af3bbec
SW		 1225 "Speakers", "SPOLN",
1226 "Mic Jack", "MICBIAS1",
1227 "IN2P", "Mic Jack";
aa5ae424
SW		 1228
1229 nvidia,i2s-controller = <&tegra_i2s1>;
1230 nvidia,audio-codec = <&rt5640>;
1231
1232 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
1233
1234 clocks = <&tegra_car TEGRA114_CLK_PLL_A>,
1235 <&tegra_car TEGRA114_CLK_PLL_A_OUT0>,
1236 <&tegra_car TEGRA114_CLK_EXTERN1>;
1237 clock-names = "pll_a", "pll_a_out0", "mclk";
1238 };
a71c03e7 1239};
Linux kernel - Deliverables
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