Commit | Line | Data |
---|---|---|
a1c85860 | 1 | #include <dt-bindings/clock/tegra114-car.h> |
3325f1bc | 2 | #include <dt-bindings/gpio/tegra-gpio.h> |
6cecf916 | 3 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
3325f1bc | 4 | |
1bd0bd49 | 5 | #include "skeleton.dtsi" |
18a4df70 HD |
6 | |
7 | / { | |
8 | compatible = "nvidia,tegra114"; | |
9 | interrupt-parent = <&gic>; | |
10 | ||
0fb22096 LD |
11 | aliases { |
12 | serial0 = &uarta; | |
13 | serial1 = &uartb; | |
14 | serial2 = &uartc; | |
15 | serial3 = &uartd; | |
16 | }; | |
17 | ||
18a4df70 HD |
18 | gic: interrupt-controller { |
19 | compatible = "arm,cortex-a15-gic"; | |
20 | #interrupt-cells = <3>; | |
21 | interrupt-controller; | |
22 | reg = <0x50041000 0x1000>, | |
23 | <0x50042000 0x1000>, | |
24 | <0x50044000 0x2000>, | |
25 | <0x50046000 0x2000>; | |
6cecf916 SW |
26 | interrupts = <GIC_PPI 9 |
27 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; | |
18a4df70 HD |
28 | }; |
29 | ||
30 | timer@60005000 { | |
31 | compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer"; | |
32 | reg = <0x60005000 0x400>; | |
6cecf916 SW |
33 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
34 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, | |
35 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, | |
36 | <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, | |
37 | <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, | |
38 | <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; | |
a1c85860 | 39 | clocks = <&tegra_car TEGRA114_CLK_TIMER>; |
18a4df70 HD |
40 | }; |
41 | ||
42 | tegra_car: clock { | |
672d889c | 43 | compatible = "nvidia,tegra114-car"; |
18a4df70 HD |
44 | reg = <0x60006000 0x1000>; |
45 | #clock-cells = <1>; | |
46 | }; | |
47 | ||
c5d9da4a LD |
48 | apbdma: dma { |
49 | compatible = "nvidia,tegra114-apbdma"; | |
50 | reg = <0x6000a000 0x1400>; | |
6cecf916 SW |
51 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, |
52 | <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, | |
53 | <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, | |
54 | <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, | |
55 | <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, | |
56 | <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, | |
57 | <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, | |
58 | <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, | |
59 | <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, | |
60 | <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, | |
61 | <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, | |
62 | <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, | |
63 | <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, | |
64 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, | |
65 | <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, | |
66 | <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, | |
67 | <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, | |
68 | <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, | |
69 | <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, | |
70 | <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, | |
71 | <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, | |
72 | <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, | |
73 | <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, | |
74 | <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, | |
75 | <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, | |
76 | <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, | |
77 | <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, | |
78 | <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, | |
79 | <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, | |
80 | <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, | |
81 | <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, | |
82 | <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; | |
a1c85860 | 83 | clocks = <&tegra_car TEGRA114_CLK_APBDMA>; |
c5d9da4a LD |
84 | }; |
85 | ||
0dfe42ed HD |
86 | ahb: ahb { |
87 | compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb"; | |
88 | reg = <0x6000c004 0x14c>; | |
89 | }; | |
90 | ||
b16f9183 LD |
91 | gpio: gpio { |
92 | compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio"; | |
93 | reg = <0x6000d000 0x1000>; | |
6cecf916 SW |
94 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, |
95 | <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, | |
96 | <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, | |
97 | <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, | |
98 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, | |
99 | <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, | |
100 | <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, | |
101 | <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; | |
b16f9183 LD |
102 | #gpio-cells = <2>; |
103 | gpio-controller; | |
104 | #interrupt-cells = <2>; | |
105 | interrupt-controller; | |
106 | }; | |
107 | ||
031b77af LD |
108 | pinmux: pinmux { |
109 | compatible = "nvidia,tegra114-pinmux"; | |
110 | reg = <0x70000868 0x148 /* Pad control registers */ | |
111 | 0x70003000 0x40c>; /* Mux registers */ | |
112 | }; | |
113 | ||
0fb22096 LD |
114 | /* |
115 | * There are two serial driver i.e. 8250 based simple serial | |
116 | * driver and APB DMA based serial driver for higher baudrate | |
117 | * and performace. To enable the 8250 based driver, the compatible | |
118 | * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable | |
119 | * the APB DMA based serial driver, the comptible is | |
120 | * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart". | |
121 | */ | |
122 | uarta: serial@70006000 { | |
18a4df70 HD |
123 | compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; |
124 | reg = <0x70006000 0x40>; | |
125 | reg-shift = <2>; | |
6cecf916 | 126 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
0fb22096 | 127 | nvidia,dma-request-selector = <&apbdma 8>; |
18a4df70 | 128 | status = "disabled"; |
a1c85860 | 129 | clocks = <&tegra_car TEGRA114_CLK_UARTA>; |
18a4df70 HD |
130 | }; |
131 | ||
0fb22096 | 132 | uartb: serial@70006040 { |
18a4df70 HD |
133 | compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; |
134 | reg = <0x70006040 0x40>; | |
135 | reg-shift = <2>; | |
6cecf916 | 136 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
0fb22096 | 137 | nvidia,dma-request-selector = <&apbdma 9>; |
18a4df70 | 138 | status = "disabled"; |
a1c85860 | 139 | clocks = <&tegra_car TEGRA114_CLK_UARTB>; |
18a4df70 HD |
140 | }; |
141 | ||
0fb22096 | 142 | uartc: serial@70006200 { |
18a4df70 HD |
143 | compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; |
144 | reg = <0x70006200 0x100>; | |
145 | reg-shift = <2>; | |
6cecf916 | 146 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
0fb22096 | 147 | nvidia,dma-request-selector = <&apbdma 10>; |
18a4df70 | 148 | status = "disabled"; |
a1c85860 | 149 | clocks = <&tegra_car TEGRA114_CLK_UARTC>; |
18a4df70 HD |
150 | }; |
151 | ||
0fb22096 | 152 | uartd: serial@70006300 { |
18a4df70 HD |
153 | compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; |
154 | reg = <0x70006300 0x100>; | |
155 | reg-shift = <2>; | |
6cecf916 | 156 | interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; |
0fb22096 | 157 | nvidia,dma-request-selector = <&apbdma 19>; |
18a4df70 | 158 | status = "disabled"; |
a1c85860 | 159 | clocks = <&tegra_car TEGRA114_CLK_UARTD>; |
18a4df70 HD |
160 | }; |
161 | ||
6c716db5 AC |
162 | pwm: pwm { |
163 | compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm"; | |
164 | reg = <0x7000a000 0x100>; | |
165 | #pwm-cells = <2>; | |
a1c85860 | 166 | clocks = <&tegra_car TEGRA114_CLK_PWM>; |
6c716db5 AC |
167 | status = "disabled"; |
168 | }; | |
169 | ||
3fc2f94e LD |
170 | i2c@7000c000 { |
171 | compatible = "nvidia,tegra114-i2c"; | |
172 | reg = <0x7000c000 0x100>; | |
6cecf916 | 173 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
3fc2f94e LD |
174 | #address-cells = <1>; |
175 | #size-cells = <0>; | |
a1c85860 | 176 | clocks = <&tegra_car TEGRA114_CLK_I2C1>; |
3fc2f94e LD |
177 | clock-names = "div-clk"; |
178 | status = "disabled"; | |
179 | }; | |
180 | ||
181 | i2c@7000c400 { | |
182 | compatible = "nvidia,tegra114-i2c"; | |
183 | reg = <0x7000c400 0x100>; | |
6cecf916 | 184 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
3fc2f94e LD |
185 | #address-cells = <1>; |
186 | #size-cells = <0>; | |
a1c85860 | 187 | clocks = <&tegra_car TEGRA114_CLK_I2C2>; |
3fc2f94e LD |
188 | clock-names = "div-clk"; |
189 | status = "disabled"; | |
190 | }; | |
191 | ||
192 | i2c@7000c500 { | |
193 | compatible = "nvidia,tegra114-i2c"; | |
194 | reg = <0x7000c500 0x100>; | |
6cecf916 | 195 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
3fc2f94e LD |
196 | #address-cells = <1>; |
197 | #size-cells = <0>; | |
a1c85860 | 198 | clocks = <&tegra_car TEGRA114_CLK_I2C3>; |
3fc2f94e LD |
199 | clock-names = "div-clk"; |
200 | status = "disabled"; | |
201 | }; | |
202 | ||
203 | i2c@7000c700 { | |
204 | compatible = "nvidia,tegra114-i2c"; | |
205 | reg = <0x7000c700 0x100>; | |
6cecf916 | 206 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; |
3fc2f94e LD |
207 | #address-cells = <1>; |
208 | #size-cells = <0>; | |
a1c85860 | 209 | clocks = <&tegra_car TEGRA114_CLK_I2C4>; |
3fc2f94e LD |
210 | clock-names = "div-clk"; |
211 | status = "disabled"; | |
212 | }; | |
213 | ||
214 | i2c@7000d000 { | |
215 | compatible = "nvidia,tegra114-i2c"; | |
216 | reg = <0x7000d000 0x100>; | |
6cecf916 | 217 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; |
3fc2f94e LD |
218 | #address-cells = <1>; |
219 | #size-cells = <0>; | |
a1c85860 | 220 | clocks = <&tegra_car TEGRA114_CLK_I2C5>; |
3fc2f94e LD |
221 | clock-names = "div-clk"; |
222 | status = "disabled"; | |
223 | }; | |
224 | ||
6ea0297e LD |
225 | spi@7000d400 { |
226 | compatible = "nvidia,tegra114-spi"; | |
227 | reg = <0x7000d400 0x200>; | |
6cecf916 | 228 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
6ea0297e LD |
229 | nvidia,dma-request-selector = <&apbdma 15>; |
230 | #address-cells = <1>; | |
231 | #size-cells = <0>; | |
a1c85860 | 232 | clocks = <&tegra_car TEGRA114_CLK_SBC1>; |
6ea0297e LD |
233 | clock-names = "spi"; |
234 | status = "disabled"; | |
235 | }; | |
236 | ||
237 | spi@7000d600 { | |
238 | compatible = "nvidia,tegra114-spi"; | |
239 | reg = <0x7000d600 0x200>; | |
6cecf916 | 240 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
6ea0297e LD |
241 | nvidia,dma-request-selector = <&apbdma 16>; |
242 | #address-cells = <1>; | |
243 | #size-cells = <0>; | |
a1c85860 | 244 | clocks = <&tegra_car TEGRA114_CLK_SBC2>; |
6ea0297e LD |
245 | clock-names = "spi"; |
246 | status = "disabled"; | |
247 | }; | |
248 | ||
249 | spi@7000d800 { | |
250 | compatible = "nvidia,tegra114-spi"; | |
251 | reg = <0x7000d800 0x200>; | |
6cecf916 | 252 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
6ea0297e LD |
253 | nvidia,dma-request-selector = <&apbdma 17>; |
254 | #address-cells = <1>; | |
255 | #size-cells = <0>; | |
a1c85860 | 256 | clocks = <&tegra_car TEGRA114_CLK_SBC3>; |
6ea0297e LD |
257 | clock-names = "spi"; |
258 | status = "disabled"; | |
259 | }; | |
260 | ||
261 | spi@7000da00 { | |
262 | compatible = "nvidia,tegra114-spi"; | |
263 | reg = <0x7000da00 0x200>; | |
6cecf916 | 264 | interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
6ea0297e LD |
265 | nvidia,dma-request-selector = <&apbdma 18>; |
266 | #address-cells = <1>; | |
267 | #size-cells = <0>; | |
a1c85860 | 268 | clocks = <&tegra_car TEGRA114_CLK_SBC4>; |
6ea0297e LD |
269 | clock-names = "spi"; |
270 | status = "disabled"; | |
271 | }; | |
272 | ||
273 | spi@7000dc00 { | |
274 | compatible = "nvidia,tegra114-spi"; | |
275 | reg = <0x7000dc00 0x200>; | |
6cecf916 | 276 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
6ea0297e LD |
277 | nvidia,dma-request-selector = <&apbdma 27>; |
278 | #address-cells = <1>; | |
279 | #size-cells = <0>; | |
a1c85860 | 280 | clocks = <&tegra_car TEGRA114_CLK_SBC5>; |
6ea0297e LD |
281 | clock-names = "spi"; |
282 | status = "disabled"; | |
283 | }; | |
284 | ||
285 | spi@7000de00 { | |
286 | compatible = "nvidia,tegra114-spi"; | |
287 | reg = <0x7000de00 0x200>; | |
6cecf916 | 288 | interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; |
6ea0297e LD |
289 | nvidia,dma-request-selector = <&apbdma 28>; |
290 | #address-cells = <1>; | |
291 | #size-cells = <0>; | |
a1c85860 | 292 | clocks = <&tegra_car TEGRA114_CLK_SBC6>; |
6ea0297e LD |
293 | clock-names = "spi"; |
294 | status = "disabled"; | |
295 | }; | |
296 | ||
18a4df70 HD |
297 | rtc { |
298 | compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; | |
299 | reg = <0x7000e000 0x100>; | |
6cecf916 | 300 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
a1c85860 | 301 | clocks = <&tegra_car TEGRA114_CLK_RTC>; |
18a4df70 HD |
302 | }; |
303 | ||
cd467b7d LD |
304 | kbc { |
305 | compatible = "nvidia,tegra114-kbc"; | |
306 | reg = <0x7000e200 0x100>; | |
6cecf916 | 307 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
a1c85860 | 308 | clocks = <&tegra_car TEGRA114_CLK_KBC>; |
cd467b7d LD |
309 | status = "disabled"; |
310 | }; | |
311 | ||
18a4df70 | 312 | pmc { |
2b84e53b | 313 | compatible = "nvidia,tegra114-pmc"; |
18a4df70 | 314 | reg = <0x7000e400 0x400>; |
a1c85860 | 315 | clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>; |
7021d122 | 316 | clock-names = "pclk", "clk32k_in"; |
18a4df70 HD |
317 | }; |
318 | ||
2da13965 HD |
319 | iommu { |
320 | compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu"; | |
321 | reg = <0x7000f010 0x02c | |
322 | 0x7000f1f0 0x010 | |
323 | 0x7000f228 0x074>; | |
324 | nvidia,#asids = <4>; | |
325 | dma-window = <0 0x40000000>; | |
326 | nvidia,swgroups = <0x18659fe>; | |
327 | nvidia,ahb = <&ahb>; | |
328 | }; | |
329 | ||
15e5c647 SW |
330 | ahub { |
331 | compatible = "nvidia,tegra114-ahub"; | |
332 | reg = <0x70080000 0x200>, | |
333 | <0x70080200 0x100>, | |
334 | <0x70081000 0x200>; | |
335 | interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; | |
336 | nvidia,dma-request-selector = <&apbdma 1>, <&apbdma 2>, | |
337 | <&apbdma 3>, <&apbdma 4>, <&apbdma 6>, <&apbdma 7>, | |
338 | <&apbdma 12>, <&apbdma 13>, <&apbdma 14>, | |
339 | <&apbdma 29>; | |
340 | clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>, | |
341 | <&tegra_car TEGRA114_CLK_APBIF>, | |
342 | <&tegra_car TEGRA114_CLK_I2S0>, | |
343 | <&tegra_car TEGRA114_CLK_I2S1>, | |
344 | <&tegra_car TEGRA114_CLK_I2S2>, | |
345 | <&tegra_car TEGRA114_CLK_I2S3>, | |
346 | <&tegra_car TEGRA114_CLK_I2S4>, | |
347 | <&tegra_car TEGRA114_CLK_DAM0>, | |
348 | <&tegra_car TEGRA114_CLK_DAM1>, | |
349 | <&tegra_car TEGRA114_CLK_DAM2>, | |
350 | <&tegra_car TEGRA114_CLK_SPDIF_IN>, | |
351 | <&tegra_car TEGRA114_CLK_AMX>, | |
352 | <&tegra_car TEGRA114_CLK_ADX>; | |
353 | clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", | |
354 | "i2s3", "i2s4", "dam0", "dam1", "dam2", | |
355 | "spdif_in", "amx", "adx"; | |
356 | ranges; | |
357 | #address-cells = <1>; | |
358 | #size-cells = <1>; | |
359 | ||
360 | tegra_i2s0: i2s@70080300 { | |
361 | compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; | |
362 | reg = <0x70080300 0x100>; | |
363 | nvidia,ahub-cif-ids = <4 4>; | |
364 | clocks = <&tegra_car TEGRA114_CLK_I2S0>; | |
365 | status = "disabled"; | |
366 | }; | |
367 | ||
368 | tegra_i2s1: i2s@70080400 { | |
369 | compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; | |
370 | reg = <0x70080400 0x100>; | |
371 | nvidia,ahub-cif-ids = <5 5>; | |
372 | clocks = <&tegra_car TEGRA114_CLK_I2S1>; | |
373 | status = "disabled"; | |
374 | }; | |
375 | ||
376 | tegra_i2s2: i2s@70080500 { | |
377 | compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; | |
378 | reg = <0x70080500 0x100>; | |
379 | nvidia,ahub-cif-ids = <6 6>; | |
380 | clocks = <&tegra_car TEGRA114_CLK_I2S2>; | |
381 | status = "disabled"; | |
382 | }; | |
383 | ||
384 | tegra_i2s3: i2s@70080600 { | |
385 | compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; | |
386 | reg = <0x70080600 0x100>; | |
387 | nvidia,ahub-cif-ids = <7 7>; | |
388 | clocks = <&tegra_car TEGRA114_CLK_I2S3>; | |
389 | status = "disabled"; | |
390 | }; | |
391 | ||
392 | tegra_i2s4: i2s@70080700 { | |
393 | compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; | |
394 | reg = <0x70080700 0x100>; | |
395 | nvidia,ahub-cif-ids = <8 8>; | |
396 | clocks = <&tegra_car TEGRA114_CLK_I2S4>; | |
397 | status = "disabled"; | |
398 | }; | |
399 | }; | |
400 | ||
933d87a5 PR |
401 | sdhci@78000000 { |
402 | compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; | |
403 | reg = <0x78000000 0x200>; | |
6cecf916 | 404 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
a1c85860 | 405 | clocks = <&tegra_car TEGRA114_CLK_SDMMC1>; |
933d87a5 PR |
406 | status = "disable"; |
407 | }; | |
408 | ||
409 | sdhci@78000200 { | |
410 | compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; | |
411 | reg = <0x78000200 0x200>; | |
6cecf916 | 412 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
a1c85860 | 413 | clocks = <&tegra_car TEGRA114_CLK_SDMMC2>; |
933d87a5 PR |
414 | status = "disable"; |
415 | }; | |
416 | ||
417 | sdhci@78000400 { | |
418 | compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; | |
419 | reg = <0x78000400 0x200>; | |
6cecf916 | 420 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
a1c85860 | 421 | clocks = <&tegra_car TEGRA114_CLK_SDMMC3>; |
933d87a5 PR |
422 | status = "disable"; |
423 | }; | |
424 | ||
425 | sdhci@78000600 { | |
426 | compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; | |
427 | reg = <0x78000600 0x200>; | |
6cecf916 | 428 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
a1c85860 | 429 | clocks = <&tegra_car TEGRA114_CLK_SDMMC4>; |
933d87a5 PR |
430 | status = "disable"; |
431 | }; | |
432 | ||
18a4df70 HD |
433 | cpus { |
434 | #address-cells = <1>; | |
435 | #size-cells = <0>; | |
436 | ||
437 | cpu@0 { | |
438 | device_type = "cpu"; | |
439 | compatible = "arm,cortex-a15"; | |
440 | reg = <0>; | |
441 | }; | |
442 | ||
443 | cpu@1 { | |
444 | device_type = "cpu"; | |
445 | compatible = "arm,cortex-a15"; | |
446 | reg = <1>; | |
447 | }; | |
448 | ||
449 | cpu@2 { | |
450 | device_type = "cpu"; | |
451 | compatible = "arm,cortex-a15"; | |
452 | reg = <2>; | |
453 | }; | |
454 | ||
455 | cpu@3 { | |
456 | device_type = "cpu"; | |
457 | compatible = "arm,cortex-a15"; | |
458 | reg = <3>; | |
459 | }; | |
460 | }; | |
461 | ||
462 | timer { | |
463 | compatible = "arm,armv7-timer"; | |
6cecf916 SW |
464 | interrupts = |
465 | <GIC_PPI 13 | |
466 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
467 | <GIC_PPI 14 | |
468 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
469 | <GIC_PPI 11 | |
470 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
471 | <GIC_PPI 10 | |
472 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; | |
18a4df70 HD |
473 | }; |
474 | }; |