Commit | Line | Data |
---|---|---|
a1c85860 | 1 | #include <dt-bindings/clock/tegra114-car.h> |
3325f1bc | 2 | #include <dt-bindings/gpio/tegra-gpio.h> |
32215e71 | 3 | #include <dt-bindings/memory/tegra114-mc.h> |
5fc6b0dd | 4 | #include <dt-bindings/pinctrl/pinctrl-tegra.h> |
6cecf916 | 5 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
3325f1bc | 6 | |
1bd0bd49 | 7 | #include "skeleton.dtsi" |
18a4df70 HD |
8 | |
9 | / { | |
10 | compatible = "nvidia,tegra114"; | |
870c81a4 | 11 | interrupt-parent = <&lic>; |
18a4df70 | 12 | |
65344b93 MP |
13 | host1x@50000000 { |
14 | compatible = "nvidia,tegra114-host1x", "simple-bus"; | |
15 | reg = <0x50000000 0x00028000>; | |
16 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ | |
17 | <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ | |
18 | clocks = <&tegra_car TEGRA114_CLK_HOST1X>; | |
19 | resets = <&tegra_car 28>; | |
20 | reset-names = "host1x"; | |
21 | ||
22 | #address-cells = <1>; | |
23 | #size-cells = <1>; | |
24 | ||
25 | ranges = <0x54000000 0x54000000 0x01000000>; | |
26 | ||
5648b260 TR |
27 | gr2d@54140000 { |
28 | compatible = "nvidia,tegra114-gr2d", "nvidia,tegra20-gr2d"; | |
29 | reg = <0x54140000 0x00040000>; | |
30 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; | |
31 | clocks = <&tegra_car TEGRA114_CLK_GR2D>; | |
32 | resets = <&tegra_car 21>; | |
33 | reset-names = "2d"; | |
34 | }; | |
35 | ||
032f11f3 TR |
36 | gr3d@54180000 { |
37 | compatible = "nvidia,tegra114-gr3d", "nvidia,tegra20-gr3d"; | |
38 | reg = <0x54180000 0x00040000>; | |
39 | clocks = <&tegra_car TEGRA114_CLK_GR3D>; | |
40 | resets = <&tegra_car 24>; | |
41 | reset-names = "3d"; | |
42 | }; | |
43 | ||
65344b93 MP |
44 | dc@54200000 { |
45 | compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc"; | |
46 | reg = <0x54200000 0x00040000>; | |
47 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; | |
48 | clocks = <&tegra_car TEGRA114_CLK_DISP1>, | |
49 | <&tegra_car TEGRA114_CLK_PLL_P>; | |
50 | clock-names = "dc", "parent"; | |
51 | resets = <&tegra_car 27>; | |
52 | reset-names = "dc"; | |
53 | ||
32215e71 TR |
54 | iommus = <&mc TEGRA_SWGROUP_DC>; |
55 | ||
688b56b4 TR |
56 | nvidia,head = <0>; |
57 | ||
65344b93 MP |
58 | rgb { |
59 | status = "disabled"; | |
60 | }; | |
61 | }; | |
62 | ||
63 | dc@54240000 { | |
64 | compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc"; | |
65 | reg = <0x54240000 0x00040000>; | |
66 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; | |
67 | clocks = <&tegra_car TEGRA114_CLK_DISP2>, | |
68 | <&tegra_car TEGRA114_CLK_PLL_P>; | |
69 | clock-names = "dc", "parent"; | |
70 | resets = <&tegra_car 26>; | |
71 | reset-names = "dc"; | |
72 | ||
32215e71 TR |
73 | iommus = <&mc TEGRA_SWGROUP_DCB>; |
74 | ||
688b56b4 TR |
75 | nvidia,head = <1>; |
76 | ||
65344b93 MP |
77 | rgb { |
78 | status = "disabled"; | |
79 | }; | |
80 | }; | |
81 | ||
82 | hdmi@54280000 { | |
83 | compatible = "nvidia,tegra114-hdmi"; | |
84 | reg = <0x54280000 0x00040000>; | |
85 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; | |
86 | clocks = <&tegra_car TEGRA114_CLK_HDMI>, | |
87 | <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>; | |
88 | clock-names = "hdmi", "parent"; | |
89 | resets = <&tegra_car 51>; | |
90 | reset-names = "hdmi"; | |
91 | status = "disabled"; | |
92 | }; | |
7e4ba90f TR |
93 | |
94 | dsi@54300000 { | |
95 | compatible = "nvidia,tegra114-dsi"; | |
96 | reg = <0x54300000 0x00040000>; | |
97 | clocks = <&tegra_car TEGRA114_CLK_DSIA>, | |
98 | <&tegra_car TEGRA114_CLK_DSIALP>, | |
99 | <&tegra_car TEGRA114_CLK_PLL_D_OUT0>; | |
100 | clock-names = "dsi", "lp", "parent"; | |
101 | resets = <&tegra_car 48>; | |
102 | reset-names = "dsi"; | |
103 | nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */ | |
104 | status = "disabled"; | |
105 | ||
106 | #address-cells = <1>; | |
107 | #size-cells = <0>; | |
108 | }; | |
109 | ||
110 | dsi@54400000 { | |
111 | compatible = "nvidia,tegra114-dsi"; | |
112 | reg = <0x54400000 0x00040000>; | |
113 | clocks = <&tegra_car TEGRA114_CLK_DSIB>, | |
114 | <&tegra_car TEGRA114_CLK_DSIBLP>, | |
115 | <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>; | |
116 | clock-names = "dsi", "lp", "parent"; | |
117 | resets = <&tegra_car 82>; | |
118 | reset-names = "dsi"; | |
119 | nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */ | |
120 | status = "disabled"; | |
121 | ||
122 | #address-cells = <1>; | |
123 | #size-cells = <0>; | |
124 | }; | |
65344b93 MP |
125 | }; |
126 | ||
58ecb23f | 127 | gic: interrupt-controller@50041000 { |
18a4df70 HD |
128 | compatible = "arm,cortex-a15-gic"; |
129 | #interrupt-cells = <3>; | |
130 | interrupt-controller; | |
131 | reg = <0x50041000 0x1000>, | |
132 | <0x50042000 0x1000>, | |
133 | <0x50044000 0x2000>, | |
134 | <0x50046000 0x2000>; | |
6cecf916 SW |
135 | interrupts = <GIC_PPI 9 |
136 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; | |
870c81a4 MZ |
137 | interrupt-parent = <&gic>; |
138 | }; | |
139 | ||
140 | lic: interrupt-controller@60004000 { | |
141 | compatible = "nvidia,tegra114-ictlr", "nvidia,tegra30-ictlr"; | |
142 | reg = <0x60004000 0x100>, | |
143 | <0x60004100 0x50>, | |
144 | <0x60004200 0x50>, | |
145 | <0x60004300 0x50>, | |
146 | <0x60004400 0x50>; | |
147 | interrupt-controller; | |
148 | #interrupt-cells = <3>; | |
149 | interrupt-parent = <&gic>; | |
18a4df70 HD |
150 | }; |
151 | ||
152 | timer@60005000 { | |
b6641294 | 153 | compatible = "nvidia,tegra114-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer"; |
18a4df70 | 154 | reg = <0x60005000 0x400>; |
6cecf916 SW |
155 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
156 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, | |
157 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, | |
158 | <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, | |
159 | <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, | |
160 | <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; | |
a1c85860 | 161 | clocks = <&tegra_car TEGRA114_CLK_TIMER>; |
18a4df70 HD |
162 | }; |
163 | ||
58ecb23f | 164 | tegra_car: clock@60006000 { |
672d889c | 165 | compatible = "nvidia,tegra114-car"; |
18a4df70 HD |
166 | reg = <0x60006000 0x1000>; |
167 | #clock-cells = <1>; | |
3393d422 | 168 | #reset-cells = <1>; |
18a4df70 HD |
169 | }; |
170 | ||
b1023134 TR |
171 | flow-controller@60007000 { |
172 | compatible = "nvidia,tegra114-flowctrl"; | |
173 | reg = <0x60007000 0x1000>; | |
174 | }; | |
175 | ||
58ecb23f | 176 | apbdma: dma@6000a000 { |
c5d9da4a LD |
177 | compatible = "nvidia,tegra114-apbdma"; |
178 | reg = <0x6000a000 0x1400>; | |
6cecf916 SW |
179 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, |
180 | <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, | |
181 | <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, | |
182 | <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, | |
183 | <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, | |
184 | <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, | |
185 | <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, | |
186 | <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, | |
187 | <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, | |
188 | <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, | |
189 | <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, | |
190 | <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, | |
191 | <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, | |
192 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, | |
193 | <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, | |
194 | <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, | |
195 | <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, | |
196 | <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, | |
197 | <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, | |
198 | <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, | |
199 | <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, | |
200 | <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, | |
201 | <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, | |
202 | <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, | |
203 | <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, | |
204 | <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, | |
205 | <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, | |
206 | <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, | |
207 | <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, | |
208 | <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, | |
209 | <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, | |
210 | <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; | |
a1c85860 | 211 | clocks = <&tegra_car TEGRA114_CLK_APBDMA>; |
3393d422 SW |
212 | resets = <&tegra_car 34>; |
213 | reset-names = "dma"; | |
034d023f | 214 | #dma-cells = <1>; |
c5d9da4a LD |
215 | }; |
216 | ||
0d5ccb38 | 217 | ahb: ahb@6000c000 { |
0dfe42ed | 218 | compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb"; |
0d5ccb38 | 219 | reg = <0x6000c000 0x150>; |
0dfe42ed HD |
220 | }; |
221 | ||
58ecb23f | 222 | gpio: gpio@6000d000 { |
b16f9183 LD |
223 | compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio"; |
224 | reg = <0x6000d000 0x1000>; | |
6cecf916 SW |
225 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, |
226 | <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, | |
227 | <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, | |
228 | <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, | |
229 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, | |
230 | <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, | |
231 | <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, | |
232 | <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; | |
b16f9183 LD |
233 | #gpio-cells = <2>; |
234 | gpio-controller; | |
235 | #interrupt-cells = <2>; | |
236 | interrupt-controller; | |
4f1d8414 | 237 | /* |
17cdddf0 | 238 | gpio-ranges = <&pinmux 0 0 246>; |
4f1d8414 | 239 | */ |
b16f9183 LD |
240 | }; |
241 | ||
155dfc7b PDS |
242 | apbmisc@70000800 { |
243 | compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc"; | |
244 | reg = <0x70000800 0x64 /* Chip revision */ | |
245 | 0x70000008 0x04>; /* Strapping options */ | |
246 | }; | |
247 | ||
58ecb23f | 248 | pinmux: pinmux@70000868 { |
031b77af LD |
249 | compatible = "nvidia,tegra114-pinmux"; |
250 | reg = <0x70000868 0x148 /* Pad control registers */ | |
251 | 0x70003000 0x40c>; /* Mux registers */ | |
252 | }; | |
253 | ||
0fb22096 LD |
254 | /* |
255 | * There are two serial driver i.e. 8250 based simple serial | |
256 | * driver and APB DMA based serial driver for higher baudrate | |
257 | * and performace. To enable the 8250 based driver, the compatible | |
258 | * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable | |
e1098248 | 259 | * the APB DMA based serial driver, the compatible is |
0fb22096 LD |
260 | * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart". |
261 | */ | |
262 | uarta: serial@70006000 { | |
18a4df70 HD |
263 | compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; |
264 | reg = <0x70006000 0x40>; | |
265 | reg-shift = <2>; | |
6cecf916 | 266 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
a1c85860 | 267 | clocks = <&tegra_car TEGRA114_CLK_UARTA>; |
3393d422 SW |
268 | resets = <&tegra_car 6>; |
269 | reset-names = "serial"; | |
034d023f SW |
270 | dmas = <&apbdma 8>, <&apbdma 8>; |
271 | dma-names = "rx", "tx"; | |
3393d422 | 272 | status = "disabled"; |
18a4df70 HD |
273 | }; |
274 | ||
0fb22096 | 275 | uartb: serial@70006040 { |
18a4df70 HD |
276 | compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; |
277 | reg = <0x70006040 0x40>; | |
278 | reg-shift = <2>; | |
6cecf916 | 279 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
a1c85860 | 280 | clocks = <&tegra_car TEGRA114_CLK_UARTB>; |
3393d422 SW |
281 | resets = <&tegra_car 7>; |
282 | reset-names = "serial"; | |
034d023f SW |
283 | dmas = <&apbdma 9>, <&apbdma 9>; |
284 | dma-names = "rx", "tx"; | |
3393d422 | 285 | status = "disabled"; |
18a4df70 HD |
286 | }; |
287 | ||
0fb22096 | 288 | uartc: serial@70006200 { |
18a4df70 HD |
289 | compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; |
290 | reg = <0x70006200 0x100>; | |
291 | reg-shift = <2>; | |
6cecf916 | 292 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
a1c85860 | 293 | clocks = <&tegra_car TEGRA114_CLK_UARTC>; |
3393d422 SW |
294 | resets = <&tegra_car 55>; |
295 | reset-names = "serial"; | |
034d023f SW |
296 | dmas = <&apbdma 10>, <&apbdma 10>; |
297 | dma-names = "rx", "tx"; | |
3393d422 | 298 | status = "disabled"; |
18a4df70 HD |
299 | }; |
300 | ||
0fb22096 | 301 | uartd: serial@70006300 { |
18a4df70 HD |
302 | compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; |
303 | reg = <0x70006300 0x100>; | |
304 | reg-shift = <2>; | |
6cecf916 | 305 | interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; |
a1c85860 | 306 | clocks = <&tegra_car TEGRA114_CLK_UARTD>; |
3393d422 SW |
307 | resets = <&tegra_car 65>; |
308 | reset-names = "serial"; | |
034d023f SW |
309 | dmas = <&apbdma 19>, <&apbdma 19>; |
310 | dma-names = "rx", "tx"; | |
3393d422 | 311 | status = "disabled"; |
18a4df70 HD |
312 | }; |
313 | ||
58ecb23f | 314 | pwm: pwm@7000a000 { |
6c716db5 AC |
315 | compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm"; |
316 | reg = <0x7000a000 0x100>; | |
317 | #pwm-cells = <2>; | |
a1c85860 | 318 | clocks = <&tegra_car TEGRA114_CLK_PWM>; |
3393d422 SW |
319 | resets = <&tegra_car 17>; |
320 | reset-names = "pwm"; | |
6c716db5 AC |
321 | status = "disabled"; |
322 | }; | |
323 | ||
3fc2f94e LD |
324 | i2c@7000c000 { |
325 | compatible = "nvidia,tegra114-i2c"; | |
326 | reg = <0x7000c000 0x100>; | |
6cecf916 | 327 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
3fc2f94e LD |
328 | #address-cells = <1>; |
329 | #size-cells = <0>; | |
a1c85860 | 330 | clocks = <&tegra_car TEGRA114_CLK_I2C1>; |
3fc2f94e | 331 | clock-names = "div-clk"; |
3393d422 SW |
332 | resets = <&tegra_car 12>; |
333 | reset-names = "i2c"; | |
034d023f SW |
334 | dmas = <&apbdma 21>, <&apbdma 21>; |
335 | dma-names = "rx", "tx"; | |
3fc2f94e LD |
336 | status = "disabled"; |
337 | }; | |
338 | ||
339 | i2c@7000c400 { | |
340 | compatible = "nvidia,tegra114-i2c"; | |
341 | reg = <0x7000c400 0x100>; | |
6cecf916 | 342 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
3fc2f94e LD |
343 | #address-cells = <1>; |
344 | #size-cells = <0>; | |
a1c85860 | 345 | clocks = <&tegra_car TEGRA114_CLK_I2C2>; |
3fc2f94e | 346 | clock-names = "div-clk"; |
3393d422 SW |
347 | resets = <&tegra_car 54>; |
348 | reset-names = "i2c"; | |
034d023f SW |
349 | dmas = <&apbdma 22>, <&apbdma 22>; |
350 | dma-names = "rx", "tx"; | |
3fc2f94e LD |
351 | status = "disabled"; |
352 | }; | |
353 | ||
354 | i2c@7000c500 { | |
355 | compatible = "nvidia,tegra114-i2c"; | |
356 | reg = <0x7000c500 0x100>; | |
6cecf916 | 357 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
3fc2f94e LD |
358 | #address-cells = <1>; |
359 | #size-cells = <0>; | |
a1c85860 | 360 | clocks = <&tegra_car TEGRA114_CLK_I2C3>; |
3fc2f94e | 361 | clock-names = "div-clk"; |
3393d422 SW |
362 | resets = <&tegra_car 67>; |
363 | reset-names = "i2c"; | |
034d023f SW |
364 | dmas = <&apbdma 23>, <&apbdma 23>; |
365 | dma-names = "rx", "tx"; | |
3fc2f94e LD |
366 | status = "disabled"; |
367 | }; | |
368 | ||
369 | i2c@7000c700 { | |
370 | compatible = "nvidia,tegra114-i2c"; | |
371 | reg = <0x7000c700 0x100>; | |
6cecf916 | 372 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; |
3fc2f94e LD |
373 | #address-cells = <1>; |
374 | #size-cells = <0>; | |
a1c85860 | 375 | clocks = <&tegra_car TEGRA114_CLK_I2C4>; |
3fc2f94e | 376 | clock-names = "div-clk"; |
3393d422 SW |
377 | resets = <&tegra_car 103>; |
378 | reset-names = "i2c"; | |
034d023f SW |
379 | dmas = <&apbdma 26>, <&apbdma 26>; |
380 | dma-names = "rx", "tx"; | |
3fc2f94e LD |
381 | status = "disabled"; |
382 | }; | |
383 | ||
384 | i2c@7000d000 { | |
385 | compatible = "nvidia,tegra114-i2c"; | |
386 | reg = <0x7000d000 0x100>; | |
6cecf916 | 387 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; |
3fc2f94e LD |
388 | #address-cells = <1>; |
389 | #size-cells = <0>; | |
a1c85860 | 390 | clocks = <&tegra_car TEGRA114_CLK_I2C5>; |
3fc2f94e | 391 | clock-names = "div-clk"; |
3393d422 SW |
392 | resets = <&tegra_car 47>; |
393 | reset-names = "i2c"; | |
034d023f SW |
394 | dmas = <&apbdma 24>, <&apbdma 24>; |
395 | dma-names = "rx", "tx"; | |
3fc2f94e LD |
396 | status = "disabled"; |
397 | }; | |
398 | ||
6ea0297e LD |
399 | spi@7000d400 { |
400 | compatible = "nvidia,tegra114-spi"; | |
401 | reg = <0x7000d400 0x200>; | |
6cecf916 | 402 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
6ea0297e LD |
403 | #address-cells = <1>; |
404 | #size-cells = <0>; | |
a1c85860 | 405 | clocks = <&tegra_car TEGRA114_CLK_SBC1>; |
6ea0297e | 406 | clock-names = "spi"; |
3393d422 SW |
407 | resets = <&tegra_car 41>; |
408 | reset-names = "spi"; | |
034d023f SW |
409 | dmas = <&apbdma 15>, <&apbdma 15>; |
410 | dma-names = "rx", "tx"; | |
6ea0297e LD |
411 | status = "disabled"; |
412 | }; | |
413 | ||
414 | spi@7000d600 { | |
415 | compatible = "nvidia,tegra114-spi"; | |
416 | reg = <0x7000d600 0x200>; | |
6cecf916 | 417 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
6ea0297e LD |
418 | #address-cells = <1>; |
419 | #size-cells = <0>; | |
a1c85860 | 420 | clocks = <&tegra_car TEGRA114_CLK_SBC2>; |
6ea0297e | 421 | clock-names = "spi"; |
3393d422 SW |
422 | resets = <&tegra_car 44>; |
423 | reset-names = "spi"; | |
034d023f SW |
424 | dmas = <&apbdma 16>, <&apbdma 16>; |
425 | dma-names = "rx", "tx"; | |
6ea0297e LD |
426 | status = "disabled"; |
427 | }; | |
428 | ||
429 | spi@7000d800 { | |
430 | compatible = "nvidia,tegra114-spi"; | |
431 | reg = <0x7000d800 0x200>; | |
6cecf916 | 432 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
6ea0297e LD |
433 | #address-cells = <1>; |
434 | #size-cells = <0>; | |
a1c85860 | 435 | clocks = <&tegra_car TEGRA114_CLK_SBC3>; |
6ea0297e | 436 | clock-names = "spi"; |
3393d422 SW |
437 | resets = <&tegra_car 46>; |
438 | reset-names = "spi"; | |
034d023f SW |
439 | dmas = <&apbdma 17>, <&apbdma 17>; |
440 | dma-names = "rx", "tx"; | |
6ea0297e LD |
441 | status = "disabled"; |
442 | }; | |
443 | ||
444 | spi@7000da00 { | |
445 | compatible = "nvidia,tegra114-spi"; | |
446 | reg = <0x7000da00 0x200>; | |
6cecf916 | 447 | interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
6ea0297e LD |
448 | #address-cells = <1>; |
449 | #size-cells = <0>; | |
a1c85860 | 450 | clocks = <&tegra_car TEGRA114_CLK_SBC4>; |
6ea0297e | 451 | clock-names = "spi"; |
3393d422 SW |
452 | resets = <&tegra_car 68>; |
453 | reset-names = "spi"; | |
034d023f SW |
454 | dmas = <&apbdma 18>, <&apbdma 18>; |
455 | dma-names = "rx", "tx"; | |
6ea0297e LD |
456 | status = "disabled"; |
457 | }; | |
458 | ||
459 | spi@7000dc00 { | |
460 | compatible = "nvidia,tegra114-spi"; | |
461 | reg = <0x7000dc00 0x200>; | |
6cecf916 | 462 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
6ea0297e LD |
463 | #address-cells = <1>; |
464 | #size-cells = <0>; | |
a1c85860 | 465 | clocks = <&tegra_car TEGRA114_CLK_SBC5>; |
6ea0297e | 466 | clock-names = "spi"; |
3393d422 SW |
467 | resets = <&tegra_car 104>; |
468 | reset-names = "spi"; | |
034d023f SW |
469 | dmas = <&apbdma 27>, <&apbdma 27>; |
470 | dma-names = "rx", "tx"; | |
6ea0297e LD |
471 | status = "disabled"; |
472 | }; | |
473 | ||
474 | spi@7000de00 { | |
475 | compatible = "nvidia,tegra114-spi"; | |
476 | reg = <0x7000de00 0x200>; | |
6cecf916 | 477 | interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; |
6ea0297e LD |
478 | #address-cells = <1>; |
479 | #size-cells = <0>; | |
a1c85860 | 480 | clocks = <&tegra_car TEGRA114_CLK_SBC6>; |
6ea0297e | 481 | clock-names = "spi"; |
3393d422 SW |
482 | resets = <&tegra_car 105>; |
483 | reset-names = "spi"; | |
034d023f SW |
484 | dmas = <&apbdma 28>, <&apbdma 28>; |
485 | dma-names = "rx", "tx"; | |
6ea0297e LD |
486 | status = "disabled"; |
487 | }; | |
488 | ||
58ecb23f | 489 | rtc@7000e000 { |
18a4df70 HD |
490 | compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; |
491 | reg = <0x7000e000 0x100>; | |
6cecf916 | 492 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
a1c85860 | 493 | clocks = <&tegra_car TEGRA114_CLK_RTC>; |
18a4df70 HD |
494 | }; |
495 | ||
58ecb23f | 496 | kbc@7000e200 { |
cd467b7d LD |
497 | compatible = "nvidia,tegra114-kbc"; |
498 | reg = <0x7000e200 0x100>; | |
6cecf916 | 499 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
a1c85860 | 500 | clocks = <&tegra_car TEGRA114_CLK_KBC>; |
3393d422 SW |
501 | resets = <&tegra_car 36>; |
502 | reset-names = "kbc"; | |
cd467b7d LD |
503 | status = "disabled"; |
504 | }; | |
505 | ||
58ecb23f | 506 | pmc@7000e400 { |
2b84e53b | 507 | compatible = "nvidia,tegra114-pmc"; |
18a4df70 | 508 | reg = <0x7000e400 0x400>; |
a1c85860 | 509 | clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>; |
7021d122 | 510 | clock-names = "pclk", "clk32k_in"; |
18a4df70 HD |
511 | }; |
512 | ||
155dfc7b PDS |
513 | fuse@7000f800 { |
514 | compatible = "nvidia,tegra114-efuse"; | |
515 | reg = <0x7000f800 0x400>; | |
516 | clocks = <&tegra_car TEGRA114_CLK_FUSE>; | |
517 | clock-names = "fuse"; | |
518 | resets = <&tegra_car 39>; | |
519 | reset-names = "fuse"; | |
520 | }; | |
521 | ||
c6f70a4d TR |
522 | mc: memory-controller@70019000 { |
523 | compatible = "nvidia,tegra114-mc"; | |
524 | reg = <0x70019000 0x1000>; | |
525 | clocks = <&tegra_car TEGRA114_CLK_MC>; | |
526 | clock-names = "mc"; | |
527 | ||
528 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; | |
529 | ||
530 | #iommu-cells = <1>; | |
2da13965 HD |
531 | }; |
532 | ||
58ecb23f | 533 | ahub@70080000 { |
15e5c647 SW |
534 | compatible = "nvidia,tegra114-ahub"; |
535 | reg = <0x70080000 0x200>, | |
536 | <0x70080200 0x100>, | |
537 | <0x70081000 0x200>; | |
538 | interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; | |
15e5c647 | 539 | clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>, |
2bd541ff SW |
540 | <&tegra_car TEGRA114_CLK_APBIF>; |
541 | clock-names = "d_audio", "apbif"; | |
3393d422 SW |
542 | resets = <&tegra_car 106>, /* d_audio */ |
543 | <&tegra_car 107>, /* apbif */ | |
544 | <&tegra_car 30>, /* i2s0 */ | |
545 | <&tegra_car 11>, /* i2s1 */ | |
546 | <&tegra_car 18>, /* i2s2 */ | |
547 | <&tegra_car 101>, /* i2s3 */ | |
548 | <&tegra_car 102>, /* i2s4 */ | |
549 | <&tegra_car 108>, /* dam0 */ | |
550 | <&tegra_car 109>, /* dam1 */ | |
551 | <&tegra_car 110>, /* dam2 */ | |
552 | <&tegra_car 10>, /* spdif */ | |
553 | <&tegra_car 153>, /* amx */ | |
554 | <&tegra_car 154>; /* adx */ | |
555 | reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", | |
556 | "i2s3", "i2s4", "dam0", "dam1", "dam2", | |
557 | "spdif", "amx", "adx"; | |
034d023f SW |
558 | dmas = <&apbdma 1>, <&apbdma 1>, |
559 | <&apbdma 2>, <&apbdma 2>, | |
560 | <&apbdma 3>, <&apbdma 3>, | |
561 | <&apbdma 4>, <&apbdma 4>, | |
562 | <&apbdma 6>, <&apbdma 6>, | |
563 | <&apbdma 7>, <&apbdma 7>, | |
564 | <&apbdma 12>, <&apbdma 12>, | |
565 | <&apbdma 13>, <&apbdma 13>, | |
566 | <&apbdma 14>, <&apbdma 14>, | |
567 | <&apbdma 29>, <&apbdma 29>; | |
568 | dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", | |
569 | "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", | |
570 | "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", | |
571 | "rx9", "tx9"; | |
15e5c647 SW |
572 | ranges; |
573 | #address-cells = <1>; | |
574 | #size-cells = <1>; | |
575 | ||
576 | tegra_i2s0: i2s@70080300 { | |
577 | compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; | |
578 | reg = <0x70080300 0x100>; | |
579 | nvidia,ahub-cif-ids = <4 4>; | |
580 | clocks = <&tegra_car TEGRA114_CLK_I2S0>; | |
3393d422 SW |
581 | resets = <&tegra_car 30>; |
582 | reset-names = "i2s"; | |
15e5c647 SW |
583 | status = "disabled"; |
584 | }; | |
585 | ||
586 | tegra_i2s1: i2s@70080400 { | |
587 | compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; | |
588 | reg = <0x70080400 0x100>; | |
589 | nvidia,ahub-cif-ids = <5 5>; | |
590 | clocks = <&tegra_car TEGRA114_CLK_I2S1>; | |
3393d422 SW |
591 | resets = <&tegra_car 11>; |
592 | reset-names = "i2s"; | |
15e5c647 SW |
593 | status = "disabled"; |
594 | }; | |
595 | ||
596 | tegra_i2s2: i2s@70080500 { | |
597 | compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; | |
598 | reg = <0x70080500 0x100>; | |
599 | nvidia,ahub-cif-ids = <6 6>; | |
600 | clocks = <&tegra_car TEGRA114_CLK_I2S2>; | |
3393d422 SW |
601 | resets = <&tegra_car 18>; |
602 | reset-names = "i2s"; | |
15e5c647 SW |
603 | status = "disabled"; |
604 | }; | |
605 | ||
606 | tegra_i2s3: i2s@70080600 { | |
607 | compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; | |
608 | reg = <0x70080600 0x100>; | |
609 | nvidia,ahub-cif-ids = <7 7>; | |
610 | clocks = <&tegra_car TEGRA114_CLK_I2S3>; | |
3393d422 SW |
611 | resets = <&tegra_car 101>; |
612 | reset-names = "i2s"; | |
15e5c647 SW |
613 | status = "disabled"; |
614 | }; | |
615 | ||
616 | tegra_i2s4: i2s@70080700 { | |
617 | compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; | |
618 | reg = <0x70080700 0x100>; | |
619 | nvidia,ahub-cif-ids = <8 8>; | |
620 | clocks = <&tegra_car TEGRA114_CLK_I2S4>; | |
3393d422 SW |
621 | resets = <&tegra_car 102>; |
622 | reset-names = "i2s"; | |
15e5c647 SW |
623 | status = "disabled"; |
624 | }; | |
625 | }; | |
626 | ||
e3d04d17 TR |
627 | mipi: mipi@700e3000 { |
628 | compatible = "nvidia,tegra114-mipi"; | |
629 | reg = <0x700e3000 0x100>; | |
630 | clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>; | |
631 | #nvidia,mipi-calibrate-cells = <1>; | |
632 | }; | |
633 | ||
933d87a5 PR |
634 | sdhci@78000000 { |
635 | compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; | |
636 | reg = <0x78000000 0x200>; | |
6cecf916 | 637 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
a1c85860 | 638 | clocks = <&tegra_car TEGRA114_CLK_SDMMC1>; |
3393d422 SW |
639 | resets = <&tegra_car 14>; |
640 | reset-names = "sdhci"; | |
e2b6d77e | 641 | status = "disabled"; |
933d87a5 PR |
642 | }; |
643 | ||
644 | sdhci@78000200 { | |
645 | compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; | |
646 | reg = <0x78000200 0x200>; | |
6cecf916 | 647 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
a1c85860 | 648 | clocks = <&tegra_car TEGRA114_CLK_SDMMC2>; |
3393d422 SW |
649 | resets = <&tegra_car 9>; |
650 | reset-names = "sdhci"; | |
e2b6d77e | 651 | status = "disabled"; |
933d87a5 PR |
652 | }; |
653 | ||
654 | sdhci@78000400 { | |
655 | compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; | |
656 | reg = <0x78000400 0x200>; | |
6cecf916 | 657 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
a1c85860 | 658 | clocks = <&tegra_car TEGRA114_CLK_SDMMC3>; |
3393d422 SW |
659 | resets = <&tegra_car 69>; |
660 | reset-names = "sdhci"; | |
e2b6d77e | 661 | status = "disabled"; |
933d87a5 PR |
662 | }; |
663 | ||
664 | sdhci@78000600 { | |
665 | compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; | |
666 | reg = <0x78000600 0x200>; | |
6cecf916 | 667 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
a1c85860 | 668 | clocks = <&tegra_car TEGRA114_CLK_SDMMC4>; |
3393d422 SW |
669 | resets = <&tegra_car 15>; |
670 | reset-names = "sdhci"; | |
e2b6d77e | 671 | status = "disabled"; |
933d87a5 PR |
672 | }; |
673 | ||
328dc0ec MP |
674 | usb@7d000000 { |
675 | compatible = "nvidia,tegra30-ehci", "usb-ehci"; | |
676 | reg = <0x7d000000 0x4000>; | |
677 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; | |
678 | phy_type = "utmi"; | |
679 | clocks = <&tegra_car TEGRA114_CLK_USBD>; | |
3393d422 SW |
680 | resets = <&tegra_car 22>; |
681 | reset-names = "usb"; | |
328dc0ec MP |
682 | nvidia,phy = <&phy1>; |
683 | status = "disabled"; | |
684 | }; | |
685 | ||
686 | phy1: usb-phy@7d000000 { | |
687 | compatible = "nvidia,tegra30-usb-phy"; | |
688 | reg = <0x7d000000 0x4000 0x7d000000 0x4000>; | |
689 | phy_type = "utmi"; | |
690 | clocks = <&tegra_car TEGRA114_CLK_USBD>, | |
691 | <&tegra_car TEGRA114_CLK_PLL_U>, | |
692 | <&tegra_car TEGRA114_CLK_USBD>; | |
693 | clock-names = "reg", "pll_u", "utmi-pads"; | |
308efde2 TT |
694 | resets = <&tegra_car 22>, <&tegra_car 22>; |
695 | reset-names = "usb", "utmi-pads"; | |
328dc0ec MP |
696 | nvidia,hssync-start-delay = <0>; |
697 | nvidia,idle-wait-delay = <17>; | |
698 | nvidia,elastic-limit = <16>; | |
699 | nvidia,term-range-adj = <6>; | |
700 | nvidia,xcvr-setup = <9>; | |
701 | nvidia,xcvr-lsfslew = <0>; | |
702 | nvidia,xcvr-lsrslew = <3>; | |
703 | nvidia,hssquelch-level = <2>; | |
704 | nvidia,hsdiscon-level = <5>; | |
705 | nvidia,xcvr-hsslew = <12>; | |
308efde2 | 706 | nvidia,has-utmi-pad-registers; |
328dc0ec MP |
707 | status = "disabled"; |
708 | }; | |
709 | ||
710 | usb@7d008000 { | |
711 | compatible = "nvidia,tegra30-ehci", "usb-ehci"; | |
712 | reg = <0x7d008000 0x4000>; | |
713 | interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; | |
714 | phy_type = "utmi"; | |
715 | clocks = <&tegra_car TEGRA114_CLK_USB3>; | |
3393d422 SW |
716 | resets = <&tegra_car 59>; |
717 | reset-names = "usb"; | |
328dc0ec MP |
718 | nvidia,phy = <&phy3>; |
719 | status = "disabled"; | |
720 | }; | |
721 | ||
722 | phy3: usb-phy@7d008000 { | |
723 | compatible = "nvidia,tegra30-usb-phy"; | |
724 | reg = <0x7d008000 0x4000 0x7d000000 0x4000>; | |
725 | phy_type = "utmi"; | |
726 | clocks = <&tegra_car TEGRA114_CLK_USB3>, | |
727 | <&tegra_car TEGRA114_CLK_PLL_U>, | |
728 | <&tegra_car TEGRA114_CLK_USBD>; | |
729 | clock-names = "reg", "pll_u", "utmi-pads"; | |
308efde2 TT |
730 | resets = <&tegra_car 59>, <&tegra_car 22>; |
731 | reset-names = "usb", "utmi-pads"; | |
328dc0ec MP |
732 | nvidia,hssync-start-delay = <0>; |
733 | nvidia,idle-wait-delay = <17>; | |
734 | nvidia,elastic-limit = <16>; | |
735 | nvidia,term-range-adj = <6>; | |
736 | nvidia,xcvr-setup = <9>; | |
737 | nvidia,xcvr-lsfslew = <0>; | |
738 | nvidia,xcvr-lsrslew = <3>; | |
739 | nvidia,hssquelch-level = <2>; | |
740 | nvidia,hsdiscon-level = <5>; | |
741 | nvidia,xcvr-hsslew = <12>; | |
742 | status = "disabled"; | |
743 | }; | |
744 | ||
18a4df70 HD |
745 | cpus { |
746 | #address-cells = <1>; | |
747 | #size-cells = <0>; | |
748 | ||
749 | cpu@0 { | |
750 | device_type = "cpu"; | |
751 | compatible = "arm,cortex-a15"; | |
752 | reg = <0>; | |
753 | }; | |
754 | ||
755 | cpu@1 { | |
756 | device_type = "cpu"; | |
757 | compatible = "arm,cortex-a15"; | |
758 | reg = <1>; | |
759 | }; | |
760 | ||
761 | cpu@2 { | |
762 | device_type = "cpu"; | |
763 | compatible = "arm,cortex-a15"; | |
764 | reg = <2>; | |
765 | }; | |
766 | ||
767 | cpu@3 { | |
768 | device_type = "cpu"; | |
769 | compatible = "arm,cortex-a15"; | |
770 | reg = <3>; | |
771 | }; | |
772 | }; | |
773 | ||
774 | timer { | |
775 | compatible = "arm,armv7-timer"; | |
6cecf916 SW |
776 | interrupts = |
777 | <GIC_PPI 13 | |
778 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
779 | <GIC_PPI 14 | |
780 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
781 | <GIC_PPI 11 | |
782 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
783 | <GIC_PPI 10 | |
784 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; | |
870c81a4 | 785 | interrupt-parent = <&gic>; |
18a4df70 HD |
786 | }; |
787 | }; |