projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 18a4df70 HD |
1 | /include/ "skeleton.dtsi" |
| 2 | ||
| 3 | / { | |
| 4 | compatible = "nvidia,tegra114"; | |
| 5 | interrupt-parent = <&gic>; | |
| 6 | ||
| 7 | gic: interrupt-controller { | |
| 8 | compatible = "arm,cortex-a15-gic"; | |
| 9 | #interrupt-cells = <3>; | |
| 10 | interrupt-controller; | |
| 11 | reg = <0x50041000 0x1000>, | |
| 12 | <0x50042000 0x1000>, | |
| 13 | <0x50044000 0x2000>, | |
| 14 | <0x50046000 0x2000>; | |
| 15 | interrupts = <1 9 0xf04>; | |
| 16 | }; | |
| 17 | ||
| 18 | timer@60005000 { | |
| 19 | compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer"; | |
| 20 | reg = <0x60005000 0x400>; | |
| 21 | interrupts = <0 0 0x04 | |
| 22 | 0 1 0x04 | |
| 23 | 0 41 0x04 | |
| 24 | 0 42 0x04 | |
| 25 | 0 121 0x04 | |
| 26 | 0 122 0x04>; | |
| 672d889c | 27 | clocks = <&tegra_car 5>; |
| 18a4df70 HD |
28 | }; |
| 29 | ||
| 30 | tegra_car: clock { | |
| 672d889c | 31 | compatible = "nvidia,tegra114-car"; |
| 18a4df70 HD |
32 | reg = <0x60006000 0x1000>; |
| 33 | #clock-cells = <1>; | |
| 34 | }; | |
| 35 | ||
| 0dfe42ed HD |
36 | ahb: ahb { |
| 37 | compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb"; | |
| 38 | reg = <0x6000c004 0x14c>; | |
| 39 | }; | |
| 40 | ||
| b16f9183 LD |
41 | gpio: gpio { |
| 42 | compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio"; | |
| 43 | reg = <0x6000d000 0x1000>; | |
| 44 | interrupts = <0 32 0x04 | |
| 45 | 0 33 0x04 | |
| 46 | 0 34 0x04 | |
| 47 | 0 35 0x04 | |
| 48 | 0 55 0x04 | |
| 49 | 0 87 0x04 | |
| 50 | 0 89 0x04 | |
| 51 | 0 125 0x04>; | |
| 52 | #gpio-cells = <2>; | |
| 53 | gpio-controller; | |
| 54 | #interrupt-cells = <2>; | |
| 55 | interrupt-controller; | |
| 56 | }; | |
| 57 | ||
| 031b77af LD |
58 | pinmux: pinmux { |
| 59 | compatible = "nvidia,tegra114-pinmux"; | |
| 60 | reg = <0x70000868 0x148 /* Pad control registers */ | |
| 61 | 0x70003000 0x40c>; /* Mux registers */ | |
| 62 | }; | |
| 63 | ||
| 18a4df70 HD |
64 | serial@70006000 { |
| 65 | compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; | |
| 66 | reg = <0x70006000 0x40>; | |
| 67 | reg-shift = <2>; | |
| 68 | interrupts = <0 36 0x04>; | |
| 69 | status = "disabled"; | |
| 672d889c | 70 | clocks = <&tegra_car 6>; |
| 18a4df70 HD |
71 | }; |
| 72 | ||
| 73 | serial@70006040 { | |
| 74 | compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; | |
| 75 | reg = <0x70006040 0x40>; | |
| 76 | reg-shift = <2>; | |
| 77 | interrupts = <0 37 0x04>; | |
| 78 | status = "disabled"; | |
| 672d889c | 79 | clocks = <&tegra_car 192>; |
| 18a4df70 HD |
80 | }; |
| 81 | ||
| 82 | serial@70006200 { | |
| 83 | compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; | |
| 84 | reg = <0x70006200 0x100>; | |
| 85 | reg-shift = <2>; | |
| 86 | interrupts = <0 46 0x04>; | |
| 87 | status = "disabled"; | |
| 672d889c | 88 | clocks = <&tegra_car 55>; |
| 18a4df70 HD |
89 | }; |
| 90 | ||
| 91 | serial@70006300 { | |
| 92 | compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; | |
| 93 | reg = <0x70006300 0x100>; | |
| 94 | reg-shift = <2>; | |
| 95 | interrupts = <0 90 0x04>; | |
| 96 | status = "disabled"; | |
| 672d889c | 97 | clocks = <&tegra_car 65>; |
| 18a4df70 HD |
98 | }; |
| 99 | ||
| 6c716db5 AC |
100 | pwm: pwm { |
| 101 | compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm"; | |
| 102 | reg = <0x7000a000 0x100>; | |
| 103 | #pwm-cells = <2>; | |
| 104 | clocks = <&tegra_car 17>; | |
| 105 | status = "disabled"; | |
| 106 | }; | |
| 107 | ||
| 18a4df70 HD |
108 | rtc { |
| 109 | compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; | |
| 110 | reg = <0x7000e000 0x100>; | |
| 111 | interrupts = <0 2 0x04>; | |
| 672d889c | 112 | clocks = <&tegra_car 4>; |
| 18a4df70 HD |
113 | }; |
| 114 | ||
| 115 | pmc { | |
| 2b84e53b | 116 | compatible = "nvidia,tegra114-pmc"; |
| 18a4df70 | 117 | reg = <0x7000e400 0x400>; |
| 7021d122 JL |
118 | clocks = <&tegra_car 261>, <&clk32k_in>; |
| 119 | clock-names = "pclk", "clk32k_in"; | |
| 18a4df70 HD |
120 | }; |
| 121 | ||
| 2da13965 HD |
122 | iommu { |
| 123 | compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu"; | |
| 124 | reg = <0x7000f010 0x02c | |
| 125 | 0x7000f1f0 0x010 | |
| 126 | 0x7000f228 0x074>; | |
| 127 | nvidia,#asids = <4>; | |
| 128 | dma-window = <0 0x40000000>; | |
| 129 | nvidia,swgroups = <0x18659fe>; | |
| 130 | nvidia,ahb = <&ahb>; | |
| 131 | }; | |
| 132 | ||
| 933d87a5 PR |
133 | sdhci@78000000 { |
| 134 | compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; | |
| 135 | reg = <0x78000000 0x200>; | |
| 136 | interrupts = <0 14 0x04>; | |
| 137 | clocks = <&tegra_car 14>; | |
| 138 | status = "disable"; | |
| 139 | }; | |
| 140 | ||
| 141 | sdhci@78000200 { | |
| 142 | compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; | |
| 143 | reg = <0x78000200 0x200>; | |
| 144 | interrupts = <0 15 0x04>; | |
| 145 | clocks = <&tegra_car 9>; | |
| 146 | status = "disable"; | |
| 147 | }; | |
| 148 | ||
| 149 | sdhci@78000400 { | |
| 150 | compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; | |
| 151 | reg = <0x78000400 0x200>; | |
| 152 | interrupts = <0 19 0x04>; | |
| 153 | clocks = <&tegra_car 69>; | |
| 154 | status = "disable"; | |
| 155 | }; | |
| 156 | ||
| 157 | sdhci@78000600 { | |
| 158 | compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; | |
| 159 | reg = <0x78000600 0x200>; | |
| 160 | interrupts = <0 31 0x04>; | |
| 161 | clocks = <&tegra_car 15>; | |
| 162 | status = "disable"; | |
| 163 | }; | |
| 164 | ||
| 18a4df70 HD |
165 | cpus { |
| 166 | #address-cells = <1>; | |
| 167 | #size-cells = <0>; | |
| 168 | ||
| 169 | cpu@0 { | |
| 170 | device_type = "cpu"; | |
| 171 | compatible = "arm,cortex-a15"; | |
| 172 | reg = <0>; | |
| 173 | }; | |
| 174 | ||
| 175 | cpu@1 { | |
| 176 | device_type = "cpu"; | |
| 177 | compatible = "arm,cortex-a15"; | |
| 178 | reg = <1>; | |
| 179 | }; | |
| 180 | ||
| 181 | cpu@2 { | |
| 182 | device_type = "cpu"; | |
| 183 | compatible = "arm,cortex-a15"; | |
| 184 | reg = <2>; | |
| 185 | }; | |
| 186 | ||
| 187 | cpu@3 { | |
| 188 | device_type = "cpu"; | |
| 189 | compatible = "arm,cortex-a15"; | |
| 190 | reg = <3>; | |
| 191 | }; | |
| 192 | }; | |
| 193 | ||
| 194 | timer { | |
| 195 | compatible = "arm,armv7-timer"; | |
| 196 | interrupts = <1 13 0xf08>, | |
| 197 | <1 14 0xf08>, | |
| 198 | <1 11 0xf08>, | |
| 199 | <1 10 0xf08>; | |
| 200 | }; | |
| 201 | }; |