projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 18a4df70 HD |
1 | /include/ "skeleton.dtsi" |
| 2 | ||
| 3 | / { | |
| 4 | compatible = "nvidia,tegra114"; | |
| 5 | interrupt-parent = <&gic>; | |
| 6 | ||
| 7 | gic: interrupt-controller { | |
| 8 | compatible = "arm,cortex-a15-gic"; | |
| 9 | #interrupt-cells = <3>; | |
| 10 | interrupt-controller; | |
| 11 | reg = <0x50041000 0x1000>, | |
| 12 | <0x50042000 0x1000>, | |
| 13 | <0x50044000 0x2000>, | |
| 14 | <0x50046000 0x2000>; | |
| 15 | interrupts = <1 9 0xf04>; | |
| 16 | }; | |
| 17 | ||
| 18 | timer@60005000 { | |
| 19 | compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer"; | |
| 20 | reg = <0x60005000 0x400>; | |
| 21 | interrupts = <0 0 0x04 | |
| 22 | 0 1 0x04 | |
| 23 | 0 41 0x04 | |
| 24 | 0 42 0x04 | |
| 25 | 0 121 0x04 | |
| 26 | 0 122 0x04>; | |
| 27 | }; | |
| 28 | ||
| 29 | tegra_car: clock { | |
| 30 | compatible = "nvidia,tegra114-car, nvidia,tegra30-car"; | |
| 31 | reg = <0x60006000 0x1000>; | |
| 32 | #clock-cells = <1>; | |
| 33 | }; | |
| 34 | ||
| 0dfe42ed HD |
35 | ahb: ahb { |
| 36 | compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb"; | |
| 37 | reg = <0x6000c004 0x14c>; | |
| 38 | }; | |
| 39 | ||
| b16f9183 LD |
40 | gpio: gpio { |
| 41 | compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio"; | |
| 42 | reg = <0x6000d000 0x1000>; | |
| 43 | interrupts = <0 32 0x04 | |
| 44 | 0 33 0x04 | |
| 45 | 0 34 0x04 | |
| 46 | 0 35 0x04 | |
| 47 | 0 55 0x04 | |
| 48 | 0 87 0x04 | |
| 49 | 0 89 0x04 | |
| 50 | 0 125 0x04>; | |
| 51 | #gpio-cells = <2>; | |
| 52 | gpio-controller; | |
| 53 | #interrupt-cells = <2>; | |
| 54 | interrupt-controller; | |
| 55 | }; | |
| 56 | ||
| 18a4df70 HD |
57 | serial@70006000 { |
| 58 | compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; | |
| 59 | reg = <0x70006000 0x40>; | |
| 60 | reg-shift = <2>; | |
| 61 | interrupts = <0 36 0x04>; | |
| 62 | status = "disabled"; | |
| 63 | }; | |
| 64 | ||
| 65 | serial@70006040 { | |
| 66 | compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; | |
| 67 | reg = <0x70006040 0x40>; | |
| 68 | reg-shift = <2>; | |
| 69 | interrupts = <0 37 0x04>; | |
| 70 | status = "disabled"; | |
| 71 | }; | |
| 72 | ||
| 73 | serial@70006200 { | |
| 74 | compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; | |
| 75 | reg = <0x70006200 0x100>; | |
| 76 | reg-shift = <2>; | |
| 77 | interrupts = <0 46 0x04>; | |
| 78 | status = "disabled"; | |
| 79 | }; | |
| 80 | ||
| 81 | serial@70006300 { | |
| 82 | compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; | |
| 83 | reg = <0x70006300 0x100>; | |
| 84 | reg-shift = <2>; | |
| 85 | interrupts = <0 90 0x04>; | |
| 86 | status = "disabled"; | |
| 87 | }; | |
| 88 | ||
| 89 | rtc { | |
| 90 | compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; | |
| 91 | reg = <0x7000e000 0x100>; | |
| 92 | interrupts = <0 2 0x04>; | |
| 93 | }; | |
| 94 | ||
| 95 | pmc { | |
| 96 | compatible = "nvidia,tegra114-pmc", "nvidia,tegra30-pmc"; | |
| 97 | reg = <0x7000e400 0x400>; | |
| 98 | }; | |
| 99 | ||
| 2da13965 HD |
100 | iommu { |
| 101 | compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu"; | |
| 102 | reg = <0x7000f010 0x02c | |
| 103 | 0x7000f1f0 0x010 | |
| 104 | 0x7000f228 0x074>; | |
| 105 | nvidia,#asids = <4>; | |
| 106 | dma-window = <0 0x40000000>; | |
| 107 | nvidia,swgroups = <0x18659fe>; | |
| 108 | nvidia,ahb = <&ahb>; | |
| 109 | }; | |
| 110 | ||
| 18a4df70 HD |
111 | cpus { |
| 112 | #address-cells = <1>; | |
| 113 | #size-cells = <0>; | |
| 114 | ||
| 115 | cpu@0 { | |
| 116 | device_type = "cpu"; | |
| 117 | compatible = "arm,cortex-a15"; | |
| 118 | reg = <0>; | |
| 119 | }; | |
| 120 | ||
| 121 | cpu@1 { | |
| 122 | device_type = "cpu"; | |
| 123 | compatible = "arm,cortex-a15"; | |
| 124 | reg = <1>; | |
| 125 | }; | |
| 126 | ||
| 127 | cpu@2 { | |
| 128 | device_type = "cpu"; | |
| 129 | compatible = "arm,cortex-a15"; | |
| 130 | reg = <2>; | |
| 131 | }; | |
| 132 | ||
| 133 | cpu@3 { | |
| 134 | device_type = "cpu"; | |
| 135 | compatible = "arm,cortex-a15"; | |
| 136 | reg = <3>; | |
| 137 | }; | |
| 138 | }; | |
| 139 | ||
| 140 | timer { | |
| 141 | compatible = "arm,armv7-timer"; | |
| 142 | interrupts = <1 13 0xf08>, | |
| 143 | <1 14 0xf08>, | |
| 144 | <1 11 0xf08>, | |
| 145 | <1 10 0xf08>; | |
| 146 | }; | |
| 147 | }; |