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Merge tag 'mvebu-dt-fixes-3.14' of git://git.infradead.org/linux-mvebu into fixes
[deliverable/linux.git] / arch / arm / boot / dts / tegra114.dtsi
CommitLineData
a1c85860 1#include <dt-bindings/clock/tegra114-car.h>
3325f1bc 2#include <dt-bindings/gpio/tegra-gpio.h>
5fc6b0dd 3#include <dt-bindings/pinctrl/pinctrl-tegra.h>
6cecf916 4#include <dt-bindings/interrupt-controller/arm-gic.h>
3325f1bc 5
1bd0bd49 6#include "skeleton.dtsi"
18a4df70
HD		 7
8/ {
9 compatible = "nvidia,tegra114";
10 interrupt-parent = <&gic>;
11
0fb22096
LD		 12 aliases {
13 serial0 = &uarta;
14 serial1 = &uartb;
15 serial2 = &uartc;
16 serial3 = &uartd;
17 };
18
65344b93
MP		 19 host1x@50000000 {
20 compatible = "nvidia,tegra114-host1x", "simple-bus";
21 reg = <0x50000000 0x00028000>;
22 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
23 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
24 clocks = <&tegra_car TEGRA114_CLK_HOST1X>;
25 resets = <&tegra_car 28>;
26 reset-names = "host1x";
27
28 #address-cells = <1>;
29 #size-cells = <1>;
30
31 ranges = <0x54000000 0x54000000 0x01000000>;
32
5648b260
TR		 33 gr2d@54140000 {
34 compatible = "nvidia,tegra114-gr2d", "nvidia,tegra20-gr2d";
35 reg = <0x54140000 0x00040000>;
36 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
37 clocks = <&tegra_car TEGRA114_CLK_GR2D>;
38 resets = <&tegra_car 21>;
39 reset-names = "2d";
40 };
41
032f11f3
TR		 42 gr3d@54180000 {
43 compatible = "nvidia,tegra114-gr3d", "nvidia,tegra20-gr3d";
44 reg = <0x54180000 0x00040000>;
45 clocks = <&tegra_car TEGRA114_CLK_GR3D>;
46 resets = <&tegra_car 24>;
47 reset-names = "3d";
48 };
49
65344b93
MP		 50 dc@54200000 {
51 compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
52 reg = <0x54200000 0x00040000>;
53 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
54 clocks = <&tegra_car TEGRA114_CLK_DISP1>,
55 <&tegra_car TEGRA114_CLK_PLL_P>;
56 clock-names = "dc", "parent";
57 resets = <&tegra_car 27>;
58 reset-names = "dc";
59
60 rgb {
61 status = "disabled";
62 };
63 };
64
65 dc@54240000 {
66 compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
67 reg = <0x54240000 0x00040000>;
68 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
69 clocks = <&tegra_car TEGRA114_CLK_DISP2>,
70 <&tegra_car TEGRA114_CLK_PLL_P>;
71 clock-names = "dc", "parent";
72 resets = <&tegra_car 26>;
73 reset-names = "dc";
74
75 rgb {
76 status = "disabled";
77 };
78 };
79
80 hdmi@54280000 {
81 compatible = "nvidia,tegra114-hdmi";
82 reg = <0x54280000 0x00040000>;
83 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
84 clocks = <&tegra_car TEGRA114_CLK_HDMI>,
85 <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>;
86 clock-names = "hdmi", "parent";
87 resets = <&tegra_car 51>;
88 reset-names = "hdmi";
89 status = "disabled";
90 };
7e4ba90f
TR		 91
92 dsi@54300000 {
93 compatible = "nvidia,tegra114-dsi";
94 reg = <0x54300000 0x00040000>;
95 clocks = <&tegra_car TEGRA114_CLK_DSIA>,
96 <&tegra_car TEGRA114_CLK_DSIALP>,
97 <&tegra_car TEGRA114_CLK_PLL_D_OUT0>;
98 clock-names = "dsi", "lp", "parent";
99 resets = <&tegra_car 48>;
100 reset-names = "dsi";
101 nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
102 status = "disabled";
103
104 #address-cells = <1>;
105 #size-cells = <0>;
106 };
107
108 dsi@54400000 {
109 compatible = "nvidia,tegra114-dsi";
110 reg = <0x54400000 0x00040000>;
111 clocks = <&tegra_car TEGRA114_CLK_DSIB>,
112 <&tegra_car TEGRA114_CLK_DSIBLP>,
113 <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>;
114 clock-names = "dsi", "lp", "parent";
115 resets = <&tegra_car 82>;
116 reset-names = "dsi";
117 nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */
118 status = "disabled";
119
120 #address-cells = <1>;
121 #size-cells = <0>;
122 };
65344b93
MP		 123 };
124
58ecb23f 125 gic: interrupt-controller@50041000 {
18a4df70
HD		 126 compatible = "arm,cortex-a15-gic";
127 #interrupt-cells = <3>;
128 interrupt-controller;
129 reg = <0x50041000 0x1000>,
130 <0x50042000 0x1000>,
131 <0x50044000 0x2000>,
132 <0x50046000 0x2000>;
6cecf916
SW		 133 interrupts = <GIC_PPI 9
134 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
18a4df70
HD		 135 };
136
137 timer@60005000 {
138 compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
139 reg = <0x60005000 0x400>;
6cecf916
SW		 140 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
141 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
142 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
143 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
144 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
145 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
a1c85860 146 clocks = <&tegra_car TEGRA114_CLK_TIMER>;
18a4df70
HD		 147 };
148
58ecb23f 149 tegra_car: clock@60006000 {
672d889c 150 compatible = "nvidia,tegra114-car";
18a4df70
HD		 151 reg = <0x60006000 0x1000>;
152 #clock-cells = <1>;
3393d422 153 #reset-cells = <1>;
18a4df70
HD		 154 };
155
58ecb23f 156 apbdma: dma@6000a000 {
c5d9da4a
LD		 157 compatible = "nvidia,tegra114-apbdma";
158 reg = <0x6000a000 0x1400>;
6cecf916
SW		 159 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
160 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
161 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
162 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
163 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
164 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
165 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
166 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
167 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
168 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
169 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
170 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
171 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
173 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
174 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
175 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
176 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
177 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
178 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
179 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
180 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
181 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
182 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
184 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
185 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
186 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
187 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
188 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
189 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
190 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
a1c85860 191 clocks = <&tegra_car TEGRA114_CLK_APBDMA>;
3393d422
SW		 192 resets = <&tegra_car 34>;
193 reset-names = "dma";
034d023f 194 #dma-cells = <1>;
c5d9da4a
LD		 195 };
196
58ecb23f 197 ahb: ahb@6000c004 {
0dfe42ed
HD		 198 compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
199 reg = <0x6000c004 0x14c>;
200 };
201
58ecb23f 202 gpio: gpio@6000d000 {
b16f9183
LD		 203 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
204 reg = <0x6000d000 0x1000>;
6cecf916
SW		 205 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
206 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
207 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
208 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
209 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
210 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
b16f9183
LD		 213 #gpio-cells = <2>;
214 gpio-controller;
215 #interrupt-cells = <2>;
216 interrupt-controller;
217 };
218
58ecb23f 219 pinmux: pinmux@70000868 {
031b77af
LD		 220 compatible = "nvidia,tegra114-pinmux";
221 reg = <0x70000868 0x148 /* Pad control registers */
222 0x70003000 0x40c>; /* Mux registers */
223 };
224
0fb22096
LD		 225 /*
226 * There are two serial driver i.e. 8250 based simple serial
227 * driver and APB DMA based serial driver for higher baudrate
228 * and performace. To enable the 8250 based driver, the compatible
229 * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable
230 * the APB DMA based serial driver, the comptible is
231 * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart".
232 */
233 uarta: serial@70006000 {
18a4df70
HD		 234 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
235 reg = <0x70006000 0x40>;
236 reg-shift = <2>;
6cecf916 237 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
a1c85860 238 clocks = <&tegra_car TEGRA114_CLK_UARTA>;
3393d422
SW		 239 resets = <&tegra_car 6>;
240 reset-names = "serial";
034d023f
SW		 241 dmas = <&apbdma 8>, <&apbdma 8>;
242 dma-names = "rx", "tx";
3393d422 243 status = "disabled";
18a4df70
HD		 244 };
245
0fb22096 246 uartb: serial@70006040 {
18a4df70
HD		 247 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
248 reg = <0x70006040 0x40>;
249 reg-shift = <2>;
6cecf916 250 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
a1c85860 251 clocks = <&tegra_car TEGRA114_CLK_UARTB>;
3393d422
SW		 252 resets = <&tegra_car 7>;
253 reset-names = "serial";
034d023f
SW		 254 dmas = <&apbdma 9>, <&apbdma 9>;
255 dma-names = "rx", "tx";
3393d422 256 status = "disabled";
18a4df70
HD		 257 };
258
0fb22096 259 uartc: serial@70006200 {
18a4df70
HD		 260 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
261 reg = <0x70006200 0x100>;
262 reg-shift = <2>;
6cecf916 263 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
a1c85860 264 clocks = <&tegra_car TEGRA114_CLK_UARTC>;
3393d422
SW		 265 resets = <&tegra_car 55>;
266 reset-names = "serial";
034d023f
SW		 267 dmas = <&apbdma 10>, <&apbdma 10>;
268 dma-names = "rx", "tx";
3393d422 269 status = "disabled";
18a4df70
HD		 270 };
271
0fb22096 272 uartd: serial@70006300 {
18a4df70
HD		 273 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
274 reg = <0x70006300 0x100>;
275 reg-shift = <2>;
6cecf916 276 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
a1c85860 277 clocks = <&tegra_car TEGRA114_CLK_UARTD>;
3393d422
SW		 278 resets = <&tegra_car 65>;
279 reset-names = "serial";
034d023f
SW		 280 dmas = <&apbdma 19>, <&apbdma 19>;
281 dma-names = "rx", "tx";
3393d422 282 status = "disabled";
18a4df70
HD		 283 };
284
58ecb23f 285 pwm: pwm@7000a000 {
6c716db5
AC		 286 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
287 reg = <0x7000a000 0x100>;
288 #pwm-cells = <2>;
a1c85860 289 clocks = <&tegra_car TEGRA114_CLK_PWM>;
3393d422
SW		 290 resets = <&tegra_car 17>;
291 reset-names = "pwm";
6c716db5
AC		 292 status = "disabled";
293 };
294
3fc2f94e
LD		 295 i2c@7000c000 {
296 compatible = "nvidia,tegra114-i2c";
297 reg = <0x7000c000 0x100>;
6cecf916 298 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
3fc2f94e
LD		 299 #address-cells = <1>;
300 #size-cells = <0>;
a1c85860 301 clocks = <&tegra_car TEGRA114_CLK_I2C1>;
3fc2f94e 302 clock-names = "div-clk";
3393d422
SW		 303 resets = <&tegra_car 12>;
304 reset-names = "i2c";
034d023f
SW		 305 dmas = <&apbdma 21>, <&apbdma 21>;
306 dma-names = "rx", "tx";
3fc2f94e
LD		 307 status = "disabled";
308 };
309
310 i2c@7000c400 {
311 compatible = "nvidia,tegra114-i2c";
312 reg = <0x7000c400 0x100>;
6cecf916 313 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
3fc2f94e
LD		 314 #address-cells = <1>;
315 #size-cells = <0>;
a1c85860 316 clocks = <&tegra_car TEGRA114_CLK_I2C2>;
3fc2f94e 317 clock-names = "div-clk";
3393d422
SW		 318 resets = <&tegra_car 54>;
319 reset-names = "i2c";
034d023f
SW		 320 dmas = <&apbdma 22>, <&apbdma 22>;
321 dma-names = "rx", "tx";
3fc2f94e
LD		 322 status = "disabled";
323 };
324
325 i2c@7000c500 {
326 compatible = "nvidia,tegra114-i2c";
327 reg = <0x7000c500 0x100>;
6cecf916 328 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
3fc2f94e
LD		 329 #address-cells = <1>;
330 #size-cells = <0>;
a1c85860 331 clocks = <&tegra_car TEGRA114_CLK_I2C3>;
3fc2f94e 332 clock-names = "div-clk";
3393d422
SW		 333 resets = <&tegra_car 67>;
334 reset-names = "i2c";
034d023f
SW		 335 dmas = <&apbdma 23>, <&apbdma 23>;
336 dma-names = "rx", "tx";
3fc2f94e
LD		 337 status = "disabled";
338 };
339
340 i2c@7000c700 {
341 compatible = "nvidia,tegra114-i2c";
342 reg = <0x7000c700 0x100>;
6cecf916 343 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
3fc2f94e
LD		 344 #address-cells = <1>;
345 #size-cells = <0>;
a1c85860 346 clocks = <&tegra_car TEGRA114_CLK_I2C4>;
3fc2f94e 347 clock-names = "div-clk";
3393d422
SW		 348 resets = <&tegra_car 103>;
349 reset-names = "i2c";
034d023f
SW		 350 dmas = <&apbdma 26>, <&apbdma 26>;
351 dma-names = "rx", "tx";
3fc2f94e
LD		 352 status = "disabled";
353 };
354
355 i2c@7000d000 {
356 compatible = "nvidia,tegra114-i2c";
357 reg = <0x7000d000 0x100>;
6cecf916 358 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
3fc2f94e
LD		 359 #address-cells = <1>;
360 #size-cells = <0>;
a1c85860 361 clocks = <&tegra_car TEGRA114_CLK_I2C5>;
3fc2f94e 362 clock-names = "div-clk";
3393d422
SW		 363 resets = <&tegra_car 47>;
364 reset-names = "i2c";
034d023f
SW		 365 dmas = <&apbdma 24>, <&apbdma 24>;
366 dma-names = "rx", "tx";
3fc2f94e
LD		 367 status = "disabled";
368 };
369
6ea0297e
LD		 370 spi@7000d400 {
371 compatible = "nvidia,tegra114-spi";
372 reg = <0x7000d400 0x200>;
6cecf916 373 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
6ea0297e
LD		 374 #address-cells = <1>;
375 #size-cells = <0>;
a1c85860 376 clocks = <&tegra_car TEGRA114_CLK_SBC1>;
6ea0297e 377 clock-names = "spi";
3393d422
SW		 378 resets = <&tegra_car 41>;
379 reset-names = "spi";
034d023f
SW		 380 dmas = <&apbdma 15>, <&apbdma 15>;
381 dma-names = "rx", "tx";
6ea0297e
LD		 382 status = "disabled";
383 };
384
385 spi@7000d600 {
386 compatible = "nvidia,tegra114-spi";
387 reg = <0x7000d600 0x200>;
6cecf916 388 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
6ea0297e
LD		 389 #address-cells = <1>;
390 #size-cells = <0>;
a1c85860 391 clocks = <&tegra_car TEGRA114_CLK_SBC2>;
6ea0297e 392 clock-names = "spi";
3393d422
SW		 393 resets = <&tegra_car 44>;
394 reset-names = "spi";
034d023f
SW		 395 dmas = <&apbdma 16>, <&apbdma 16>;
396 dma-names = "rx", "tx";
6ea0297e
LD		 397 status = "disabled";
398 };
399
400 spi@7000d800 {
401 compatible = "nvidia,tegra114-spi";
402 reg = <0x7000d800 0x200>;
6cecf916 403 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
6ea0297e
LD		 404 #address-cells = <1>;
405 #size-cells = <0>;
a1c85860 406 clocks = <&tegra_car TEGRA114_CLK_SBC3>;
6ea0297e 407 clock-names = "spi";
3393d422
SW		 408 resets = <&tegra_car 46>;
409 reset-names = "spi";
034d023f
SW		 410 dmas = <&apbdma 17>, <&apbdma 17>;
411 dma-names = "rx", "tx";
6ea0297e
LD		 412 status = "disabled";
413 };
414
415 spi@7000da00 {
416 compatible = "nvidia,tegra114-spi";
417 reg = <0x7000da00 0x200>;
6cecf916 418 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
6ea0297e
LD		 419 #address-cells = <1>;
420 #size-cells = <0>;
a1c85860 421 clocks = <&tegra_car TEGRA114_CLK_SBC4>;
6ea0297e 422 clock-names = "spi";
3393d422
SW		 423 resets = <&tegra_car 68>;
424 reset-names = "spi";
034d023f
SW		 425 dmas = <&apbdma 18>, <&apbdma 18>;
426 dma-names = "rx", "tx";
6ea0297e
LD		 427 status = "disabled";
428 };
429
430 spi@7000dc00 {
431 compatible = "nvidia,tegra114-spi";
432 reg = <0x7000dc00 0x200>;
6cecf916 433 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
6ea0297e
LD		 434 #address-cells = <1>;
435 #size-cells = <0>;
a1c85860 436 clocks = <&tegra_car TEGRA114_CLK_SBC5>;
6ea0297e 437 clock-names = "spi";
3393d422
SW		 438 resets = <&tegra_car 104>;
439 reset-names = "spi";
034d023f
SW		 440 dmas = <&apbdma 27>, <&apbdma 27>;
441 dma-names = "rx", "tx";
6ea0297e
LD		 442 status = "disabled";
443 };
444
445 spi@7000de00 {
446 compatible = "nvidia,tegra114-spi";
447 reg = <0x7000de00 0x200>;
6cecf916 448 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
6ea0297e
LD		 449 #address-cells = <1>;
450 #size-cells = <0>;
a1c85860 451 clocks = <&tegra_car TEGRA114_CLK_SBC6>;
6ea0297e 452 clock-names = "spi";
3393d422
SW		 453 resets = <&tegra_car 105>;
454 reset-names = "spi";
034d023f
SW		 455 dmas = <&apbdma 28>, <&apbdma 28>;
456 dma-names = "rx", "tx";
6ea0297e
LD		 457 status = "disabled";
458 };
459
58ecb23f 460 rtc@7000e000 {
18a4df70
HD		 461 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
462 reg = <0x7000e000 0x100>;
6cecf916 463 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
a1c85860 464 clocks = <&tegra_car TEGRA114_CLK_RTC>;
18a4df70
HD		 465 };
466
58ecb23f 467 kbc@7000e200 {
cd467b7d
LD		 468 compatible = "nvidia,tegra114-kbc";
469 reg = <0x7000e200 0x100>;
6cecf916 470 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
a1c85860 471 clocks = <&tegra_car TEGRA114_CLK_KBC>;
3393d422
SW		 472 resets = <&tegra_car 36>;
473 reset-names = "kbc";
cd467b7d
LD		 474 status = "disabled";
475 };
476
58ecb23f 477 pmc@7000e400 {
2b84e53b 478 compatible = "nvidia,tegra114-pmc";
18a4df70 479 reg = <0x7000e400 0x400>;
a1c85860 480 clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>;
7021d122 481 clock-names = "pclk", "clk32k_in";
18a4df70
HD		 482 };
483
58ecb23f 484 iommu@70019010 {
2da13965 485 compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";
4cca9593
HD		 486 reg = <0x70019010 0x02c
487 0x700191f0 0x010
488 0x70019228 0x074>;
2da13965
HD		 489 nvidia,#asids = <4>;
490 dma-window = <0 0x40000000>;
491 nvidia,swgroups = <0x18659fe>;
492 nvidia,ahb = <&ahb>;
493 };
494
58ecb23f 495 ahub@70080000 {
15e5c647
SW		 496 compatible = "nvidia,tegra114-ahub";
497 reg = <0x70080000 0x200>,
498 <0x70080200 0x100>,
499 <0x70081000 0x200>;
500 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
15e5c647 501 clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>,
2bd541ff
SW		 502 <&tegra_car TEGRA114_CLK_APBIF>;
503 clock-names = "d_audio", "apbif";
3393d422
SW		 504 resets = <&tegra_car 106>, /* d_audio */
505 <&tegra_car 107>, /* apbif */
506 <&tegra_car 30>, /* i2s0 */
507 <&tegra_car 11>, /* i2s1 */
508 <&tegra_car 18>, /* i2s2 */
509 <&tegra_car 101>, /* i2s3 */
510 <&tegra_car 102>, /* i2s4 */
511 <&tegra_car 108>, /* dam0 */
512 <&tegra_car 109>, /* dam1 */
513 <&tegra_car 110>, /* dam2 */
514 <&tegra_car 10>, /* spdif */
515 <&tegra_car 153>, /* amx */
516 <&tegra_car 154>; /* adx */
517 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
518 "i2s3", "i2s4", "dam0", "dam1", "dam2",
519 "spdif", "amx", "adx";
034d023f
SW		 520 dmas = <&apbdma 1>, <&apbdma 1>,
521 <&apbdma 2>, <&apbdma 2>,
522 <&apbdma 3>, <&apbdma 3>,
523 <&apbdma 4>, <&apbdma 4>,
524 <&apbdma 6>, <&apbdma 6>,
525 <&apbdma 7>, <&apbdma 7>,
526 <&apbdma 12>, <&apbdma 12>,
527 <&apbdma 13>, <&apbdma 13>,
528 <&apbdma 14>, <&apbdma 14>,
529 <&apbdma 29>, <&apbdma 29>;
530 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
531 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
532 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
533 "rx9", "tx9";
15e5c647
SW		 534 ranges;
535 #address-cells = <1>;
536 #size-cells = <1>;
537
538 tegra_i2s0: i2s@70080300 {
539 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
540 reg = <0x70080300 0x100>;
541 nvidia,ahub-cif-ids = <4 4>;
542 clocks = <&tegra_car TEGRA114_CLK_I2S0>;
3393d422
SW		 543 resets = <&tegra_car 30>;
544 reset-names = "i2s";
15e5c647
SW		 545 status = "disabled";
546 };
547
548 tegra_i2s1: i2s@70080400 {
549 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
550 reg = <0x70080400 0x100>;
551 nvidia,ahub-cif-ids = <5 5>;
552 clocks = <&tegra_car TEGRA114_CLK_I2S1>;
3393d422
SW		 553 resets = <&tegra_car 11>;
554 reset-names = "i2s";
15e5c647
SW		 555 status = "disabled";
556 };
557
558 tegra_i2s2: i2s@70080500 {
559 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
560 reg = <0x70080500 0x100>;
561 nvidia,ahub-cif-ids = <6 6>;
562 clocks = <&tegra_car TEGRA114_CLK_I2S2>;
3393d422
SW		 563 resets = <&tegra_car 18>;
564 reset-names = "i2s";
15e5c647
SW		 565 status = "disabled";
566 };
567
568 tegra_i2s3: i2s@70080600 {
569 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
570 reg = <0x70080600 0x100>;
571 nvidia,ahub-cif-ids = <7 7>;
572 clocks = <&tegra_car TEGRA114_CLK_I2S3>;
3393d422
SW		 573 resets = <&tegra_car 101>;
574 reset-names = "i2s";
15e5c647
SW		 575 status = "disabled";
576 };
577
578 tegra_i2s4: i2s@70080700 {
579 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
580 reg = <0x70080700 0x100>;
581 nvidia,ahub-cif-ids = <8 8>;
582 clocks = <&tegra_car TEGRA114_CLK_I2S4>;
3393d422
SW		 583 resets = <&tegra_car 102>;
584 reset-names = "i2s";
15e5c647
SW		 585 status = "disabled";
586 };
587 };
588
e3d04d17
TR		 589 mipi: mipi@700e3000 {
590 compatible = "nvidia,tegra114-mipi";
591 reg = <0x700e3000 0x100>;
592 clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>;
593 #nvidia,mipi-calibrate-cells = <1>;
594 };
595
933d87a5
PR		 596 sdhci@78000000 {
597 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
598 reg = <0x78000000 0x200>;
6cecf916 599 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
a1c85860 600 clocks = <&tegra_car TEGRA114_CLK_SDMMC1>;
3393d422
SW		 601 resets = <&tegra_car 14>;
602 reset-names = "sdhci";
933d87a5
PR		 603 status = "disable";
604 };
605
606 sdhci@78000200 {
607 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
608 reg = <0x78000200 0x200>;
6cecf916 609 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
a1c85860 610 clocks = <&tegra_car TEGRA114_CLK_SDMMC2>;
3393d422
SW		 611 resets = <&tegra_car 9>;
612 reset-names = "sdhci";
933d87a5
PR		 613 status = "disable";
614 };
615
616 sdhci@78000400 {
617 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
618 reg = <0x78000400 0x200>;
6cecf916 619 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
a1c85860 620 clocks = <&tegra_car TEGRA114_CLK_SDMMC3>;
3393d422
SW		 621 resets = <&tegra_car 69>;
622 reset-names = "sdhci";
933d87a5
PR		 623 status = "disable";
624 };
625
626 sdhci@78000600 {
627 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
628 reg = <0x78000600 0x200>;
6cecf916 629 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
a1c85860 630 clocks = <&tegra_car TEGRA114_CLK_SDMMC4>;
3393d422
SW		 631 resets = <&tegra_car 15>;
632 reset-names = "sdhci";
933d87a5
PR		 633 status = "disable";
634 };
635
328dc0ec
MP		 636 usb@7d000000 {
637 compatible = "nvidia,tegra30-ehci", "usb-ehci";
638 reg = <0x7d000000 0x4000>;
639 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
640 phy_type = "utmi";
641 clocks = <&tegra_car TEGRA114_CLK_USBD>;
3393d422
SW		 642 resets = <&tegra_car 22>;
643 reset-names = "usb";
328dc0ec
MP		 644 nvidia,phy = <&phy1>;
645 status = "disabled";
646 };
647
648 phy1: usb-phy@7d000000 {
649 compatible = "nvidia,tegra30-usb-phy";
650 reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
651 phy_type = "utmi";
652 clocks = <&tegra_car TEGRA114_CLK_USBD>,
653 <&tegra_car TEGRA114_CLK_PLL_U>,
654 <&tegra_car TEGRA114_CLK_USBD>;
655 clock-names = "reg", "pll_u", "utmi-pads";
656 nvidia,hssync-start-delay = <0>;
657 nvidia,idle-wait-delay = <17>;
658 nvidia,elastic-limit = <16>;
659 nvidia,term-range-adj = <6>;
660 nvidia,xcvr-setup = <9>;
661 nvidia,xcvr-lsfslew = <0>;
662 nvidia,xcvr-lsrslew = <3>;
663 nvidia,hssquelch-level = <2>;
664 nvidia,hsdiscon-level = <5>;
665 nvidia,xcvr-hsslew = <12>;
666 status = "disabled";
667 };
668
669 usb@7d008000 {
670 compatible = "nvidia,tegra30-ehci", "usb-ehci";
671 reg = <0x7d008000 0x4000>;
672 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
673 phy_type = "utmi";
674 clocks = <&tegra_car TEGRA114_CLK_USB3>;
3393d422
SW		 675 resets = <&tegra_car 59>;
676 reset-names = "usb";
328dc0ec
MP		 677 nvidia,phy = <&phy3>;
678 status = "disabled";
679 };
680
681 phy3: usb-phy@7d008000 {
682 compatible = "nvidia,tegra30-usb-phy";
683 reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
684 phy_type = "utmi";
685 clocks = <&tegra_car TEGRA114_CLK_USB3>,
686 <&tegra_car TEGRA114_CLK_PLL_U>,
687 <&tegra_car TEGRA114_CLK_USBD>;
688 clock-names = "reg", "pll_u", "utmi-pads";
689 nvidia,hssync-start-delay = <0>;
690 nvidia,idle-wait-delay = <17>;
691 nvidia,elastic-limit = <16>;
692 nvidia,term-range-adj = <6>;
693 nvidia,xcvr-setup = <9>;
694 nvidia,xcvr-lsfslew = <0>;
695 nvidia,xcvr-lsrslew = <3>;
696 nvidia,hssquelch-level = <2>;
697 nvidia,hsdiscon-level = <5>;
698 nvidia,xcvr-hsslew = <12>;
699 status = "disabled";
700 };
701
18a4df70
HD		 702 cpus {
703 #address-cells = <1>;
704 #size-cells = <0>;
705
706 cpu@0 {
707 device_type = "cpu";
708 compatible = "arm,cortex-a15";
709 reg = <0>;
710 };
711
712 cpu@1 {
713 device_type = "cpu";
714 compatible = "arm,cortex-a15";
715 reg = <1>;
716 };
717
718 cpu@2 {
719 device_type = "cpu";
720 compatible = "arm,cortex-a15";
721 reg = <2>;
722 };
723
724 cpu@3 {
725 device_type = "cpu";
726 compatible = "arm,cortex-a15";
727 reg = <3>;
728 };
729 };
730
731 timer {
732 compatible = "arm,armv7-timer";
6cecf916
SW		 733 interrupts =
734 <GIC_PPI 13
735 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
736 <GIC_PPI 14
737 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
738 <GIC_PPI 11
739 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
740 <GIC_PPI 10
741 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
18a4df70
HD		 742 };
743};
Linux kernel - Deliverables
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