Commit | Line | Data |
---|---|---|
15e524a4 SW |
1 | /dts-v1/; |
2 | ||
3 | #include <dt-bindings/input/input.h> | |
4 | #include "tegra124.dtsi" | |
5 | ||
6e72cf00 MP |
6 | #include "tegra124-jetson-tk1-emc.dtsi" |
7 | ||
15e524a4 SW |
8 | / { |
9 | model = "NVIDIA Tegra124 Jetson TK1"; | |
10 | compatible = "nvidia,jetson-tk1", "nvidia,tegra124"; | |
11 | ||
12 | aliases { | |
13 | rtc0 = "/i2c@0,7000d000/pmic@40"; | |
14 | rtc1 = "/rtc@0,7000e000"; | |
c90bb7b9 RR |
15 | |
16 | /* This order keeps the mapping DB9 connector <-> ttyS0 */ | |
c4574aa0 | 17 | serial0 = &uartd; |
c90bb7b9 RR |
18 | serial1 = &uarta; |
19 | serial2 = &uartb; | |
15e524a4 SW |
20 | }; |
21 | ||
f5bbb327 JH |
22 | chosen { |
23 | stdout-path = "serial0:115200n8"; | |
24 | }; | |
25 | ||
15e524a4 SW |
26 | memory { |
27 | reg = <0x0 0x80000000 0x0 0x80000000>; | |
28 | }; | |
29 | ||
8e2b9e4d TR |
30 | pcie-controller@0,01003000 { |
31 | status = "okay"; | |
32 | ||
33 | avddio-pex-supply = <&vdd_1v05_run>; | |
34 | dvddio-pex-supply = <&vdd_1v05_run>; | |
35 | avdd-pex-pll-supply = <&vdd_1v05_run>; | |
36 | hvdd-pex-supply = <&vdd_3v3_lp0>; | |
37 | hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>; | |
38 | vddio-pex-ctl-supply = <&vdd_3v3_lp0>; | |
39 | avdd-pll-erefe-supply = <&avdd_1v05_run>; | |
40 | ||
87c68119 | 41 | /* Mini PCIe */ |
8e2b9e4d | 42 | pci@1,0 { |
87c68119 TR |
43 | phys = <&{/padctl@0,7009f000/pads/pcie/lanes/pcie-4}>; |
44 | phy-names = "pcie-0"; | |
8e2b9e4d TR |
45 | status = "okay"; |
46 | }; | |
47 | ||
87c68119 | 48 | /* Gigabit Ethernet */ |
8e2b9e4d | 49 | pci@2,0 { |
87c68119 TR |
50 | phys = <&{/padctl@0,7009f000/pads/pcie/lanes/pcie-2}>; |
51 | phy-names = "pcie-0"; | |
8e2b9e4d TR |
52 | status = "okay"; |
53 | }; | |
54 | }; | |
55 | ||
6054dd39 TR |
56 | host1x@0,50000000 { |
57 | hdmi@0,54280000 { | |
58 | status = "okay"; | |
59 | ||
60 | hdmi-supply = <&vdd_5v0_hdmi>; | |
61 | pll-supply = <&vdd_hdmi_pll>; | |
62 | vdd-supply = <&vdd_3v3_hdmi>; | |
63 | ||
64 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; | |
65 | nvidia,hpd-gpio = | |
66 | <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; | |
67 | }; | |
68 | }; | |
69 | ||
21fa196f AC |
70 | gpu@0,57000000 { |
71 | /* | |
72 | * Node left disabled on purpose - the bootloader will enable | |
73 | * it after having set the VPR up | |
74 | */ | |
75 | vdd-supply = <&vdd_gpu>; | |
76 | }; | |
77 | ||
15e524a4 | 78 | pinmux: pinmux@0,70000868 { |
6dbaff2b SW |
79 | pinctrl-names = "boot"; |
80 | pinctrl-0 = <&state_boot>; | |
15e524a4 | 81 | |
6dbaff2b | 82 | state_boot: pinmux { |
15e524a4 SW |
83 | clk_32k_out_pa0 { |
84 | nvidia,pins = "clk_32k_out_pa0"; | |
85 | nvidia,function = "soc"; | |
86 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
fb816641 | 87 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
88 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
89 | }; | |
90 | uart3_cts_n_pa1 { | |
91 | nvidia,pins = "uart3_cts_n_pa1"; | |
fb816641 SW |
92 | nvidia,function = "gmi"; |
93 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
94 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
95 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
96 | }; |
97 | dap2_fs_pa2 { | |
98 | nvidia,pins = "dap2_fs_pa2"; | |
99 | nvidia,function = "i2s1"; | |
100 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
101 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
fb816641 | 102 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
15e524a4 SW |
103 | }; |
104 | dap2_sclk_pa3 { | |
105 | nvidia,pins = "dap2_sclk_pa3"; | |
106 | nvidia,function = "i2s1"; | |
107 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
108 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
fb816641 | 109 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
15e524a4 SW |
110 | }; |
111 | dap2_din_pa4 { | |
112 | nvidia,pins = "dap2_din_pa4"; | |
113 | nvidia,function = "i2s1"; | |
114 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
fb816641 | 115 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
116 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
117 | }; | |
118 | dap2_dout_pa5 { | |
119 | nvidia,pins = "dap2_dout_pa5"; | |
120 | nvidia,function = "i2s1"; | |
121 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
122 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
fb816641 | 123 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
15e524a4 SW |
124 | }; |
125 | sdmmc3_clk_pa6 { | |
126 | nvidia,pins = "sdmmc3_clk_pa6"; | |
127 | nvidia,function = "sdmmc3"; | |
128 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
129 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
fb816641 | 130 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
131 | }; |
132 | sdmmc3_cmd_pa7 { | |
133 | nvidia,pins = "sdmmc3_cmd_pa7"; | |
134 | nvidia,function = "sdmmc3"; | |
135 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
136 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
137 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
138 | }; | |
139 | pb0 { | |
140 | nvidia,pins = "pb0"; | |
141 | nvidia,function = "uartd"; | |
142 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
fb816641 | 143 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
144 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
145 | }; | |
146 | pb1 { | |
147 | nvidia,pins = "pb1"; | |
148 | nvidia,function = "uartd"; | |
149 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
fb816641 | 150 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
151 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
152 | }; | |
153 | sdmmc3_dat3_pb4 { | |
154 | nvidia,pins = "sdmmc3_dat3_pb4"; | |
155 | nvidia,function = "sdmmc3"; | |
156 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
157 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
158 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
159 | }; | |
160 | sdmmc3_dat2_pb5 { | |
161 | nvidia,pins = "sdmmc3_dat2_pb5"; | |
162 | nvidia,function = "sdmmc3"; | |
163 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
164 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
165 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
166 | }; | |
167 | sdmmc3_dat1_pb6 { | |
168 | nvidia,pins = "sdmmc3_dat1_pb6"; | |
169 | nvidia,function = "sdmmc3"; | |
170 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
171 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
172 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
173 | }; | |
174 | sdmmc3_dat0_pb7 { | |
175 | nvidia,pins = "sdmmc3_dat0_pb7"; | |
176 | nvidia,function = "sdmmc3"; | |
177 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
178 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
179 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
180 | }; | |
181 | uart3_rts_n_pc0 { | |
182 | nvidia,pins = "uart3_rts_n_pc0"; | |
fb816641 SW |
183 | nvidia,function = "gmi"; |
184 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
185 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
186 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
187 | }; | |
188 | uart2_txd_pc2 { | |
189 | nvidia,pins = "uart2_txd_pc2"; | |
190 | nvidia,function = "irda"; | |
191 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
192 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
193 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
194 | }; | |
195 | uart2_rxd_pc3 { | |
196 | nvidia,pins = "uart2_rxd_pc3"; | |
197 | nvidia,function = "irda"; | |
198 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
fb816641 | 199 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
200 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
201 | }; | |
202 | gen1_i2c_scl_pc4 { | |
203 | nvidia,pins = "gen1_i2c_scl_pc4"; | |
204 | nvidia,function = "i2c1"; | |
205 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
206 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
207 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
208 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
209 | }; | |
210 | gen1_i2c_sda_pc5 { | |
211 | nvidia,pins = "gen1_i2c_sda_pc5"; | |
212 | nvidia,function = "i2c1"; | |
213 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
214 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
215 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
216 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
217 | }; | |
218 | pc7 { | |
219 | nvidia,pins = "pc7"; | |
220 | nvidia,function = "rsvd1"; | |
fb816641 SW |
221 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
222 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
223 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
224 | }; |
225 | pg0 { | |
226 | nvidia,pins = "pg0"; | |
15e524a4 | 227 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
fb816641 SW |
228 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
229 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
230 | }; |
231 | pg1 { | |
232 | nvidia,pins = "pg1"; | |
15e524a4 | 233 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
fb816641 SW |
234 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
235 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
236 | }; |
237 | pg2 { | |
238 | nvidia,pins = "pg2"; | |
fb816641 SW |
239 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
240 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
241 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
242 | }; | |
243 | pg3 { | |
244 | nvidia,pins = "pg3"; | |
fb816641 SW |
245 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
246 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
247 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
248 | }; | |
249 | pg4 { | |
250 | nvidia,pins = "pg4"; | |
15e524a4 | 251 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
fb816641 SW |
252 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
253 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
254 | }; |
255 | pg5 { | |
256 | nvidia,pins = "pg5"; | |
257 | nvidia,function = "spi4"; | |
258 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
259 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
260 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
261 | }; | |
262 | pg6 { | |
263 | nvidia,pins = "pg6"; | |
264 | nvidia,function = "spi4"; | |
265 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
266 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
267 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
268 | }; | |
269 | pg7 { | |
270 | nvidia,pins = "pg7"; | |
271 | nvidia,function = "spi4"; | |
272 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
fb816641 | 273 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
274 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
275 | }; | |
276 | ph0 { | |
277 | nvidia,pins = "ph0"; | |
278 | nvidia,function = "gmi"; | |
279 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
280 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
281 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
282 | }; | |
283 | ph1 { | |
284 | nvidia,pins = "ph1"; | |
285 | nvidia,function = "pwm1"; | |
286 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
287 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
288 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
289 | }; | |
290 | ph2 { | |
291 | nvidia,pins = "ph2"; | |
15e524a4 SW |
292 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
293 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
294 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
295 | }; | |
296 | ph3 { | |
297 | nvidia,pins = "ph3"; | |
298 | nvidia,function = "gmi"; | |
fb816641 SW |
299 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
300 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
301 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
302 | }; | |
303 | ph4 { | |
304 | nvidia,pins = "ph4"; | |
fb816641 SW |
305 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
306 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
307 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
308 | }; | |
309 | ph5 { | |
310 | nvidia,pins = "ph5"; | |
311 | nvidia,function = "rsvd2"; | |
fb816641 SW |
312 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
313 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
314 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
315 | }; | |
316 | ph6 { | |
317 | nvidia,pins = "ph6"; | |
318 | nvidia,function = "gmi"; | |
fb816641 SW |
319 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
320 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
321 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
322 | }; |
323 | ph7 { | |
324 | nvidia,pins = "ph7"; | |
15e524a4 SW |
325 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
326 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
fb816641 | 327 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
328 | }; |
329 | pi0 { | |
330 | nvidia,pins = "pi0"; | |
15e524a4 SW |
331 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
332 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
333 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
334 | }; | |
335 | pi1 { | |
336 | nvidia,pins = "pi1"; | |
fb816641 | 337 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
15e524a4 | 338 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
fb816641 | 339 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
340 | }; |
341 | pi2 { | |
342 | nvidia,pins = "pi2"; | |
343 | nvidia,function = "rsvd4"; | |
fb816641 SW |
344 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
345 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
346 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
347 | }; | |
348 | pi3 { | |
349 | nvidia,pins = "pi3"; | |
350 | nvidia,function = "spi4"; | |
351 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
352 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
353 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
354 | }; | |
355 | pi4 { | |
356 | nvidia,pins = "pi4"; | |
357 | nvidia,function = "gmi"; | |
fb816641 SW |
358 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
359 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
360 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
361 | }; | |
362 | pi5 { | |
363 | nvidia,pins = "pi5"; | |
364 | nvidia,function = "rsvd2"; | |
fb816641 SW |
365 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
366 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
367 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
368 | }; |
369 | pi6 { | |
370 | nvidia,pins = "pi6"; | |
fb816641 SW |
371 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
372 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
373 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
374 | }; | |
375 | pi7 { | |
376 | nvidia,pins = "pi7"; | |
377 | nvidia,function = "rsvd1"; | |
378 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
379 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
380 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
381 | }; | |
382 | pj0 { | |
383 | nvidia,pins = "pj0"; | |
fb816641 SW |
384 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
385 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
386 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
387 | }; | |
388 | pj2 { | |
389 | nvidia,pins = "pj2"; | |
390 | nvidia,function = "rsvd1"; | |
fb816641 SW |
391 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
392 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
393 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
394 | }; |
395 | uart2_cts_n_pj5 { | |
396 | nvidia,pins = "uart2_cts_n_pj5"; | |
397 | nvidia,function = "uartb"; | |
398 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
fb816641 | 399 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
400 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
401 | }; | |
402 | uart2_rts_n_pj6 { | |
403 | nvidia,pins = "uart2_rts_n_pj6"; | |
404 | nvidia,function = "uartb"; | |
405 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
406 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
407 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
408 | }; | |
409 | pj7 { | |
410 | nvidia,pins = "pj7"; | |
411 | nvidia,function = "uartd"; | |
412 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
413 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
414 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
415 | }; | |
416 | pk0 { | |
417 | nvidia,pins = "pk0"; | |
fb816641 SW |
418 | nvidia,function = "rsvd1"; |
419 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
420 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
421 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
422 | }; |
423 | pk1 { | |
424 | nvidia,pins = "pk1"; | |
15e524a4 SW |
425 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
426 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
427 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
428 | }; | |
429 | pk2 { | |
430 | nvidia,pins = "pk2"; | |
fb816641 | 431 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
15e524a4 SW |
432 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
433 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
434 | }; | |
435 | pk3 { | |
436 | nvidia,pins = "pk3"; | |
437 | nvidia,function = "gmi"; | |
fb816641 SW |
438 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
439 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
440 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
441 | }; |
442 | pk4 { | |
443 | nvidia,pins = "pk4"; | |
15e524a4 SW |
444 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
445 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
446 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
447 | }; | |
448 | spdif_out_pk5 { | |
449 | nvidia,pins = "spdif_out_pk5"; | |
450 | nvidia,function = "rsvd2"; | |
fb816641 SW |
451 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
452 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
453 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
454 | }; | |
455 | spdif_in_pk6 { | |
456 | nvidia,pins = "spdif_in_pk6"; | |
15e524a4 SW |
457 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
458 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
459 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
460 | }; | |
461 | pk7 { | |
462 | nvidia,pins = "pk7"; | |
463 | nvidia,function = "uartd"; | |
464 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
465 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
466 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
467 | }; | |
468 | dap1_fs_pn0 { | |
469 | nvidia,pins = "dap1_fs_pn0"; | |
fb816641 | 470 | nvidia,function = "rsvd4"; |
15e524a4 | 471 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
fb816641 SW |
472 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
473 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
474 | }; |
475 | dap1_din_pn1 { | |
476 | nvidia,pins = "dap1_din_pn1"; | |
fb816641 | 477 | nvidia,function = "rsvd4"; |
15e524a4 | 478 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
fb816641 SW |
479 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
480 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
481 | }; |
482 | dap1_dout_pn2 { | |
483 | nvidia,pins = "dap1_dout_pn2"; | |
484 | nvidia,function = "sata"; | |
485 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
486 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
487 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
488 | }; | |
489 | dap1_sclk_pn3 { | |
490 | nvidia,pins = "dap1_sclk_pn3"; | |
fb816641 | 491 | nvidia,function = "rsvd4"; |
15e524a4 | 492 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
fb816641 SW |
493 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
494 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
495 | }; |
496 | usb_vbus_en0_pn4 { | |
497 | nvidia,pins = "usb_vbus_en0_pn4"; | |
498 | nvidia,function = "usb"; | |
fb816641 | 499 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
15e524a4 SW |
500 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
501 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
fb816641 | 502 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
15e524a4 SW |
503 | }; |
504 | usb_vbus_en1_pn5 { | |
505 | nvidia,pins = "usb_vbus_en1_pn5"; | |
506 | nvidia,function = "usb"; | |
fb816641 | 507 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
15e524a4 SW |
508 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
509 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
fb816641 | 510 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
15e524a4 SW |
511 | }; |
512 | hdmi_int_pn7 { | |
513 | nvidia,pins = "hdmi_int_pn7"; | |
15e524a4 | 514 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
fb816641 | 515 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
516 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
517 | nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; | |
518 | }; | |
519 | ulpi_data7_po0 { | |
520 | nvidia,pins = "ulpi_data7_po0"; | |
521 | nvidia,function = "ulpi"; | |
fb816641 SW |
522 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
523 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
524 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
525 | }; |
526 | ulpi_data0_po1 { | |
527 | nvidia,pins = "ulpi_data0_po1"; | |
fb816641 SW |
528 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
529 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
530 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
531 | }; | |
532 | ulpi_data1_po2 { | |
533 | nvidia,pins = "ulpi_data1_po2"; | |
534 | nvidia,function = "ulpi"; | |
fb816641 SW |
535 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
536 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
537 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
538 | }; |
539 | ulpi_data2_po3 { | |
540 | nvidia,pins = "ulpi_data2_po3"; | |
541 | nvidia,function = "ulpi"; | |
fb816641 SW |
542 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
543 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
544 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
545 | }; |
546 | ulpi_data3_po4 { | |
547 | nvidia,pins = "ulpi_data3_po4"; | |
fb816641 SW |
548 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
549 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
550 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
551 | }; | |
552 | ulpi_data4_po5 { | |
553 | nvidia,pins = "ulpi_data4_po5"; | |
554 | nvidia,function = "ulpi"; | |
fb816641 SW |
555 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
556 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
557 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
558 | }; |
559 | ulpi_data5_po6 { | |
560 | nvidia,pins = "ulpi_data5_po6"; | |
561 | nvidia,function = "ulpi"; | |
fb816641 SW |
562 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
563 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
564 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
565 | }; | |
566 | ulpi_data6_po7 { | |
567 | nvidia,pins = "ulpi_data6_po7"; | |
568 | nvidia,function = "ulpi"; | |
fb816641 SW |
569 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
570 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
571 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
572 | }; |
573 | dap3_fs_pp0 { | |
574 | nvidia,pins = "dap3_fs_pp0"; | |
575 | nvidia,function = "i2s2"; | |
fb816641 SW |
576 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
577 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
578 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
579 | }; | |
580 | dap3_din_pp1 { | |
581 | nvidia,pins = "dap3_din_pp1"; | |
582 | nvidia,function = "i2s2"; | |
fb816641 SW |
583 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
584 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
585 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
586 | }; | |
587 | dap3_dout_pp2 { | |
588 | nvidia,pins = "dap3_dout_pp2"; | |
15e524a4 SW |
589 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
590 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
591 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
592 | }; | |
593 | dap3_sclk_pp3 { | |
594 | nvidia,pins = "dap3_sclk_pp3"; | |
595 | nvidia,function = "rsvd3"; | |
596 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
597 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
598 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
599 | }; | |
600 | dap4_fs_pp4 { | |
601 | nvidia,pins = "dap4_fs_pp4"; | |
fb816641 | 602 | nvidia,function = "rsvd4"; |
15e524a4 | 603 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
fb816641 SW |
604 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
605 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
606 | }; |
607 | dap4_din_pp5 { | |
608 | nvidia,pins = "dap4_din_pp5"; | |
fb816641 | 609 | nvidia,function = "rsvd3"; |
15e524a4 | 610 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
fb816641 SW |
611 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
612 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
613 | }; |
614 | dap4_dout_pp6 { | |
615 | nvidia,pins = "dap4_dout_pp6"; | |
fb816641 | 616 | nvidia,function = "rsvd4"; |
15e524a4 | 617 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
fb816641 SW |
618 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
619 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
620 | }; |
621 | dap4_sclk_pp7 { | |
622 | nvidia,pins = "dap4_sclk_pp7"; | |
fb816641 | 623 | nvidia,function = "rsvd3"; |
15e524a4 | 624 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
fb816641 SW |
625 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
626 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
627 | }; |
628 | kb_col0_pq0 { | |
629 | nvidia,pins = "kb_col0_pq0"; | |
15e524a4 | 630 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
fb816641 | 631 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
632 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
633 | }; | |
634 | kb_col1_pq1 { | |
635 | nvidia,pins = "kb_col1_pq1"; | |
636 | nvidia,function = "rsvd2"; | |
fb816641 SW |
637 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
638 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
639 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
640 | }; |
641 | kb_col2_pq2 { | |
642 | nvidia,pins = "kb_col2_pq2"; | |
643 | nvidia,function = "rsvd2"; | |
fb816641 SW |
644 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
645 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
646 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
647 | }; |
648 | kb_col3_pq3 { | |
649 | nvidia,pins = "kb_col3_pq3"; | |
fb816641 | 650 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
15e524a4 | 651 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
fb816641 | 652 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
653 | }; |
654 | kb_col4_pq4 { | |
655 | nvidia,pins = "kb_col4_pq4"; | |
656 | nvidia,function = "sdmmc3"; | |
657 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
fb816641 | 658 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
659 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
660 | }; | |
661 | kb_col5_pq5 { | |
662 | nvidia,pins = "kb_col5_pq5"; | |
fb816641 SW |
663 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
664 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
665 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
666 | }; | |
667 | kb_col6_pq6 { | |
668 | nvidia,pins = "kb_col6_pq6"; | |
669 | nvidia,function = "rsvd2"; | |
fb816641 SW |
670 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
671 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
672 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
673 | }; |
674 | kb_col7_pq7 { | |
675 | nvidia,pins = "kb_col7_pq7"; | |
fb816641 SW |
676 | nvidia,function = "rsvd2"; |
677 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
678 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
679 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
680 | }; |
681 | kb_row0_pr0 { | |
682 | nvidia,pins = "kb_row0_pr0"; | |
15e524a4 SW |
683 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
684 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
685 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
686 | }; | |
687 | kb_row1_pr1 { | |
688 | nvidia,pins = "kb_row1_pr1"; | |
689 | nvidia,function = "rsvd2"; | |
fb816641 SW |
690 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
691 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
692 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
693 | }; | |
694 | kb_row2_pr2 { | |
695 | nvidia,pins = "kb_row2_pr2"; | |
15e524a4 SW |
696 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
697 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
698 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
699 | }; | |
700 | kb_row3_pr3 { | |
701 | nvidia,pins = "kb_row3_pr3"; | |
fb816641 SW |
702 | nvidia,function = "kbc"; |
703 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
704 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
705 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
706 | }; | |
707 | kb_row4_pr4 { | |
708 | nvidia,pins = "kb_row4_pr4"; | |
fb816641 SW |
709 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
710 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
711 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
712 | }; | |
713 | kb_row5_pr5 { | |
714 | nvidia,pins = "kb_row5_pr5"; | |
715 | nvidia,function = "rsvd3"; | |
fb816641 SW |
716 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
717 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
718 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
719 | }; | |
720 | kb_row6_pr6 { | |
721 | nvidia,pins = "kb_row6_pr6"; | |
722 | nvidia,function = "displaya_alt"; | |
fb816641 SW |
723 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
724 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
725 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
726 | }; | |
727 | kb_row7_pr7 { | |
728 | nvidia,pins = "kb_row7_pr7"; | |
fb816641 SW |
729 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
730 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
731 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
732 | }; | |
733 | kb_row8_ps0 { | |
734 | nvidia,pins = "kb_row8_ps0"; | |
735 | nvidia,function = "rsvd2"; | |
fb816641 SW |
736 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
737 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
738 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
739 | }; |
740 | kb_row9_ps1 { | |
741 | nvidia,pins = "kb_row9_ps1"; | |
fb816641 | 742 | nvidia,function = "uarta"; |
15e524a4 SW |
743 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
744 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
745 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
746 | }; | |
747 | kb_row10_ps2 { | |
748 | nvidia,pins = "kb_row10_ps2"; | |
fb816641 | 749 | nvidia,function = "uarta"; |
15e524a4 | 750 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
fb816641 | 751 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
752 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
753 | }; | |
754 | kb_row11_ps3 { | |
755 | nvidia,pins = "kb_row11_ps3"; | |
756 | nvidia,function = "rsvd2"; | |
fb816641 SW |
757 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
758 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
759 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
760 | }; | |
761 | kb_row12_ps4 { | |
762 | nvidia,pins = "kb_row12_ps4"; | |
763 | nvidia,function = "rsvd2"; | |
fb816641 SW |
764 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
765 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
766 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
767 | }; | |
768 | kb_row13_ps5 { | |
769 | nvidia,pins = "kb_row13_ps5"; | |
770 | nvidia,function = "rsvd2"; | |
fb816641 SW |
771 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
772 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
773 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
774 | }; |
775 | kb_row14_ps6 { | |
776 | nvidia,pins = "kb_row14_ps6"; | |
777 | nvidia,function = "rsvd2"; | |
fb816641 SW |
778 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
779 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
780 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
781 | }; | |
782 | kb_row15_ps7 { | |
783 | nvidia,pins = "kb_row15_ps7"; | |
fb816641 SW |
784 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
785 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
786 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
787 | }; | |
788 | kb_row16_pt0 { | |
789 | nvidia,pins = "kb_row16_pt0"; | |
15e524a4 SW |
790 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
791 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
792 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
793 | }; | |
794 | kb_row17_pt1 { | |
795 | nvidia,pins = "kb_row17_pt1"; | |
15e524a4 | 796 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
fb816641 SW |
797 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
798 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
799 | }; |
800 | gen2_i2c_scl_pt5 { | |
801 | nvidia,pins = "gen2_i2c_scl_pt5"; | |
802 | nvidia,function = "i2c2"; | |
803 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
804 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
805 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
806 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
807 | }; | |
808 | gen2_i2c_sda_pt6 { | |
809 | nvidia,pins = "gen2_i2c_sda_pt6"; | |
810 | nvidia,function = "i2c2"; | |
811 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
812 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
813 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
814 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
815 | }; | |
816 | sdmmc4_cmd_pt7 { | |
817 | nvidia,pins = "sdmmc4_cmd_pt7"; | |
818 | nvidia,function = "sdmmc4"; | |
819 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
820 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
821 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
822 | }; | |
823 | pu0 { | |
824 | nvidia,pins = "pu0"; | |
15e524a4 SW |
825 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
826 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
fb816641 | 827 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
828 | }; |
829 | pu1 { | |
830 | nvidia,pins = "pu1"; | |
fb816641 | 831 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
15e524a4 SW |
832 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
833 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
834 | }; | |
835 | pu2 { | |
836 | nvidia,pins = "pu2"; | |
fb816641 | 837 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
15e524a4 SW |
838 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
839 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
840 | }; | |
841 | pu3 { | |
842 | nvidia,pins = "pu3"; | |
15e524a4 SW |
843 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
844 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
fb816641 | 845 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
846 | }; |
847 | pu4 { | |
848 | nvidia,pins = "pu4"; | |
15e524a4 SW |
849 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
850 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
fb816641 | 851 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
852 | }; |
853 | pu5 { | |
854 | nvidia,pins = "pu5"; | |
fb816641 | 855 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
15e524a4 SW |
856 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
857 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
858 | }; | |
859 | pu6 { | |
860 | nvidia,pins = "pu6"; | |
fb816641 | 861 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
15e524a4 SW |
862 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
863 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
864 | }; | |
865 | pv0 { | |
866 | nvidia,pins = "pv0"; | |
fb816641 SW |
867 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
868 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
869 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
870 | }; | |
871 | pv1 { | |
872 | nvidia,pins = "pv1"; | |
fb816641 SW |
873 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
874 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
875 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
876 | }; | |
877 | sdmmc3_cd_n_pv2 { | |
878 | nvidia,pins = "sdmmc3_cd_n_pv2"; | |
879 | nvidia,function = "sdmmc3"; | |
880 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
fb816641 | 881 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
882 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
883 | }; | |
884 | sdmmc1_wp_n_pv3 { | |
885 | nvidia,pins = "sdmmc1_wp_n_pv3"; | |
886 | nvidia,function = "sdmmc1"; | |
887 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
888 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
889 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
890 | }; | |
891 | ddc_scl_pv4 { | |
892 | nvidia,pins = "ddc_scl_pv4"; | |
893 | nvidia,function = "i2c4"; | |
894 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
895 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
896 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
897 | nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; | |
898 | }; | |
899 | ddc_sda_pv5 { | |
900 | nvidia,pins = "ddc_sda_pv5"; | |
901 | nvidia,function = "i2c4"; | |
902 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
903 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
904 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
905 | nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; | |
906 | }; | |
907 | gpio_w2_aud_pw2 { | |
908 | nvidia,pins = "gpio_w2_aud_pw2"; | |
909 | nvidia,function = "rsvd2"; | |
fb816641 SW |
910 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
911 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
912 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
913 | }; |
914 | gpio_w3_aud_pw3 { | |
915 | nvidia,pins = "gpio_w3_aud_pw3"; | |
916 | nvidia,function = "spi6"; | |
fb816641 SW |
917 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
918 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
919 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
920 | }; |
921 | dap_mclk1_pw4 { | |
922 | nvidia,pins = "dap_mclk1_pw4"; | |
923 | nvidia,function = "extperiph1"; | |
924 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
925 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
926 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
927 | }; | |
928 | clk2_out_pw5 { | |
929 | nvidia,pins = "clk2_out_pw5"; | |
930 | nvidia,function = "extperiph2"; | |
931 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
932 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
933 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
934 | }; | |
935 | uart3_txd_pw6 { | |
936 | nvidia,pins = "uart3_txd_pw6"; | |
fb816641 SW |
937 | nvidia,function = "rsvd2"; |
938 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
939 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
940 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
941 | }; | |
942 | uart3_rxd_pw7 { | |
943 | nvidia,pins = "uart3_rxd_pw7"; | |
fb816641 SW |
944 | nvidia,function = "rsvd2"; |
945 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
946 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
947 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
948 | }; |
949 | dvfs_pwm_px0 { | |
950 | nvidia,pins = "dvfs_pwm_px0"; | |
951 | nvidia,function = "cldvfs"; | |
952 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
953 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
954 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
955 | }; | |
956 | gpio_x1_aud_px1 { | |
957 | nvidia,pins = "gpio_x1_aud_px1"; | |
15e524a4 | 958 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
fb816641 SW |
959 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
960 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
961 | }; |
962 | dvfs_clk_px2 { | |
963 | nvidia,pins = "dvfs_clk_px2"; | |
964 | nvidia,function = "cldvfs"; | |
965 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
966 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
967 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
968 | }; | |
969 | gpio_x3_aud_px3 { | |
970 | nvidia,pins = "gpio_x3_aud_px3"; | |
971 | nvidia,function = "rsvd4"; | |
fb816641 SW |
972 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
973 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
974 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
975 | }; |
976 | gpio_x4_aud_px4 { | |
977 | nvidia,pins = "gpio_x4_aud_px4"; | |
15e524a4 | 978 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
fb816641 SW |
979 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
980 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
981 | }; |
982 | gpio_x5_aud_px5 { | |
983 | nvidia,pins = "gpio_x5_aud_px5"; | |
984 | nvidia,function = "rsvd4"; | |
fb816641 SW |
985 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
986 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
987 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
988 | }; |
989 | gpio_x6_aud_px6 { | |
990 | nvidia,pins = "gpio_x6_aud_px6"; | |
991 | nvidia,function = "gmi"; | |
fb816641 SW |
992 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
993 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
994 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
995 | }; |
996 | gpio_x7_aud_px7 { | |
997 | nvidia,pins = "gpio_x7_aud_px7"; | |
15e524a4 SW |
998 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
999 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1000 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1001 | }; | |
1002 | ulpi_clk_py0 { | |
1003 | nvidia,pins = "ulpi_clk_py0"; | |
1004 | nvidia,function = "spi1"; | |
1005 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1006 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1007 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1008 | }; | |
1009 | ulpi_dir_py1 { | |
1010 | nvidia,pins = "ulpi_dir_py1"; | |
1011 | nvidia,function = "spi1"; | |
fb816641 SW |
1012 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
1013 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
1014 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
1015 | }; | |
1016 | ulpi_nxt_py2 { | |
1017 | nvidia,pins = "ulpi_nxt_py2"; | |
1018 | nvidia,function = "spi1"; | |
1019 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1020 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1021 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1022 | }; | |
1023 | ulpi_stp_py3 { | |
1024 | nvidia,pins = "ulpi_stp_py3"; | |
1025 | nvidia,function = "spi1"; | |
1026 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1027 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1028 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1029 | }; | |
1030 | sdmmc1_dat3_py4 { | |
1031 | nvidia,pins = "sdmmc1_dat3_py4"; | |
1032 | nvidia,function = "sdmmc1"; | |
fb816641 SW |
1033 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
1034 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1035 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
1036 | }; |
1037 | sdmmc1_dat2_py5 { | |
1038 | nvidia,pins = "sdmmc1_dat2_py5"; | |
1039 | nvidia,function = "sdmmc1"; | |
fb816641 SW |
1040 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
1041 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1042 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
1043 | }; |
1044 | sdmmc1_dat1_py6 { | |
1045 | nvidia,pins = "sdmmc1_dat1_py6"; | |
1046 | nvidia,function = "sdmmc1"; | |
fb816641 SW |
1047 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
1048 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1049 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
1050 | }; |
1051 | sdmmc1_dat0_py7 { | |
1052 | nvidia,pins = "sdmmc1_dat0_py7"; | |
fb816641 SW |
1053 | nvidia,function = "rsvd2"; |
1054 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1055 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1056 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
1057 | }; |
1058 | sdmmc1_clk_pz0 { | |
1059 | nvidia,pins = "sdmmc1_clk_pz0"; | |
fb816641 SW |
1060 | nvidia,function = "rsvd3"; |
1061 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1062 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1063 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
1064 | }; |
1065 | sdmmc1_cmd_pz1 { | |
1066 | nvidia,pins = "sdmmc1_cmd_pz1"; | |
1067 | nvidia,function = "sdmmc1"; | |
fb816641 SW |
1068 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
1069 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1070 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
1071 | }; |
1072 | pwr_i2c_scl_pz6 { | |
1073 | nvidia,pins = "pwr_i2c_scl_pz6"; | |
1074 | nvidia,function = "i2cpwr"; | |
1075 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1076 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1077 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1078 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
1079 | }; | |
1080 | pwr_i2c_sda_pz7 { | |
1081 | nvidia,pins = "pwr_i2c_sda_pz7"; | |
1082 | nvidia,function = "i2cpwr"; | |
1083 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1084 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1085 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1086 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
1087 | }; | |
1088 | sdmmc4_dat0_paa0 { | |
1089 | nvidia,pins = "sdmmc4_dat0_paa0"; | |
1090 | nvidia,function = "sdmmc4"; | |
1091 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1092 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1093 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1094 | }; | |
1095 | sdmmc4_dat1_paa1 { | |
1096 | nvidia,pins = "sdmmc4_dat1_paa1"; | |
1097 | nvidia,function = "sdmmc4"; | |
1098 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1099 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1100 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1101 | }; | |
1102 | sdmmc4_dat2_paa2 { | |
1103 | nvidia,pins = "sdmmc4_dat2_paa2"; | |
1104 | nvidia,function = "sdmmc4"; | |
1105 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1106 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1107 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1108 | }; | |
1109 | sdmmc4_dat3_paa3 { | |
1110 | nvidia,pins = "sdmmc4_dat3_paa3"; | |
1111 | nvidia,function = "sdmmc4"; | |
1112 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1113 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1114 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1115 | }; | |
1116 | sdmmc4_dat4_paa4 { | |
1117 | nvidia,pins = "sdmmc4_dat4_paa4"; | |
1118 | nvidia,function = "sdmmc4"; | |
1119 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1120 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1121 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1122 | }; | |
1123 | sdmmc4_dat5_paa5 { | |
1124 | nvidia,pins = "sdmmc4_dat5_paa5"; | |
1125 | nvidia,function = "sdmmc4"; | |
1126 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1127 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1128 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1129 | }; | |
1130 | sdmmc4_dat6_paa6 { | |
1131 | nvidia,pins = "sdmmc4_dat6_paa6"; | |
1132 | nvidia,function = "sdmmc4"; | |
1133 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1134 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1135 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1136 | }; | |
1137 | sdmmc4_dat7_paa7 { | |
1138 | nvidia,pins = "sdmmc4_dat7_paa7"; | |
1139 | nvidia,function = "sdmmc4"; | |
1140 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1141 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1142 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1143 | }; | |
1144 | pbb0 { | |
1145 | nvidia,pins = "pbb0"; | |
1146 | nvidia,function = "vimclk2_alt"; | |
1147 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1148 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1149 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1150 | }; | |
1151 | cam_i2c_scl_pbb1 { | |
1152 | nvidia,pins = "cam_i2c_scl_pbb1"; | |
1153 | nvidia,function = "i2c3"; | |
1154 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1155 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1156 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1157 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
1158 | }; | |
1159 | cam_i2c_sda_pbb2 { | |
1160 | nvidia,pins = "cam_i2c_sda_pbb2"; | |
1161 | nvidia,function = "i2c3"; | |
1162 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1163 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1164 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1165 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
1166 | }; | |
1167 | pbb3 { | |
1168 | nvidia,pins = "pbb3"; | |
15e524a4 SW |
1169 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
1170 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1171 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1172 | }; | |
1173 | pbb4 { | |
1174 | nvidia,pins = "pbb4"; | |
1175 | nvidia,function = "vgp4"; | |
1176 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1177 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1178 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1179 | }; | |
1180 | pbb5 { | |
1181 | nvidia,pins = "pbb5"; | |
15e524a4 SW |
1182 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
1183 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1184 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1185 | }; | |
1186 | pbb6 { | |
1187 | nvidia,pins = "pbb6"; | |
15e524a4 SW |
1188 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
1189 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1190 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1191 | }; | |
1192 | pbb7 { | |
1193 | nvidia,pins = "pbb7"; | |
15e524a4 SW |
1194 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
1195 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1196 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1197 | }; | |
1198 | cam_mclk_pcc0 { | |
1199 | nvidia,pins = "cam_mclk_pcc0"; | |
1200 | nvidia,function = "vi_alt3"; | |
1201 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1202 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1203 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1204 | }; | |
1205 | pcc1 { | |
1206 | nvidia,pins = "pcc1"; | |
fb816641 | 1207 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
15e524a4 SW |
1208 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
1209 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1210 | }; | |
1211 | pcc2 { | |
1212 | nvidia,pins = "pcc2"; | |
fb816641 | 1213 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
15e524a4 SW |
1214 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
1215 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1216 | }; | |
1217 | sdmmc4_clk_pcc4 { | |
1218 | nvidia,pins = "sdmmc4_clk_pcc4"; | |
1219 | nvidia,function = "sdmmc4"; | |
1220 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1221 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1222 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1223 | }; | |
1224 | clk2_req_pcc5 { | |
1225 | nvidia,pins = "clk2_req_pcc5"; | |
1226 | nvidia,function = "rsvd2"; | |
fb816641 SW |
1227 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
1228 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
1229 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
1230 | }; | |
b0da12d5 SW |
1231 | pex_l0_rst_n_pdd1 { |
1232 | nvidia,pins = "pex_l0_rst_n_pdd1"; | |
1233 | nvidia,function = "pe0"; | |
1234 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1235 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1236 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1237 | }; | |
1238 | pex_l0_clkreq_n_pdd2 { | |
1239 | nvidia,pins = "pex_l0_clkreq_n_pdd2"; | |
1240 | nvidia,function = "pe0"; | |
fb816641 SW |
1241 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
1242 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
b0da12d5 SW |
1243 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
1244 | }; | |
1245 | pex_wake_n_pdd3 { | |
1246 | nvidia,pins = "pex_wake_n_pdd3"; | |
1247 | nvidia,function = "pe"; | |
fb816641 SW |
1248 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
1249 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
b0da12d5 SW |
1250 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
1251 | }; | |
1252 | pex_l1_rst_n_pdd5 { | |
1253 | nvidia,pins = "pex_l1_rst_n_pdd5"; | |
1254 | nvidia,function = "pe1"; | |
1255 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1256 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1257 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1258 | }; | |
1259 | pex_l1_clkreq_n_pdd6 { | |
1260 | nvidia,pins = "pex_l1_clkreq_n_pdd6"; | |
1261 | nvidia,function = "pe1"; | |
fb816641 SW |
1262 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
1263 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
b0da12d5 SW |
1264 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
1265 | }; | |
15e524a4 SW |
1266 | clk3_out_pee0 { |
1267 | nvidia,pins = "clk3_out_pee0"; | |
1268 | nvidia,function = "extperiph3"; | |
1269 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1270 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1271 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1272 | }; | |
1273 | clk3_req_pee1 { | |
1274 | nvidia,pins = "clk3_req_pee1"; | |
1275 | nvidia,function = "rsvd2"; | |
fb816641 SW |
1276 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
1277 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
1278 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
1279 | }; | |
1280 | dap_mclk1_req_pee2 { | |
1281 | nvidia,pins = "dap_mclk1_req_pee2"; | |
15e524a4 SW |
1282 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
1283 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1284 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1285 | }; | |
1286 | hdmi_cec_pee3 { | |
1287 | nvidia,pins = "hdmi_cec_pee3"; | |
1288 | nvidia,function = "cec"; | |
1289 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1290 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1291 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
fb816641 | 1292 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
15e524a4 SW |
1293 | }; |
1294 | sdmmc3_clk_lb_out_pee4 { | |
1295 | nvidia,pins = "sdmmc3_clk_lb_out_pee4"; | |
1296 | nvidia,function = "sdmmc3"; | |
1297 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1298 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1299 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1300 | }; | |
1301 | sdmmc3_clk_lb_in_pee5 { | |
1302 | nvidia,pins = "sdmmc3_clk_lb_in_pee5"; | |
1303 | nvidia,function = "sdmmc3"; | |
1304 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1305 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1306 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1307 | }; | |
1308 | dp_hpd_pff0 { | |
1309 | nvidia,pins = "dp_hpd_pff0"; | |
1310 | nvidia,function = "dp"; | |
fb816641 SW |
1311 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
1312 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
1313 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
1314 | }; | |
1315 | usb_vbus_en2_pff1 { | |
1316 | nvidia,pins = "usb_vbus_en2_pff1"; | |
1317 | nvidia,function = "rsvd2"; | |
fb816641 SW |
1318 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
1319 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
1320 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
1321 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1322 | }; | |
1323 | pff2 { | |
1324 | nvidia,pins = "pff2"; | |
1325 | nvidia,function = "rsvd2"; | |
fb816641 SW |
1326 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
1327 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1328 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
1329 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
1330 | }; | |
1331 | core_pwr_req { | |
1332 | nvidia,pins = "core_pwr_req"; | |
1333 | nvidia,function = "pwron"; | |
1334 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1335 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1336 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1337 | }; | |
1338 | cpu_pwr_req { | |
1339 | nvidia,pins = "cpu_pwr_req"; | |
fb816641 | 1340 | nvidia,function = "cpu"; |
15e524a4 SW |
1341 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
1342 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1343 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1344 | }; | |
1345 | pwr_int_n { | |
1346 | nvidia,pins = "pwr_int_n"; | |
1347 | nvidia,function = "pmi"; | |
1348 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
fb816641 | 1349 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
1350 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
1351 | }; | |
1352 | reset_out_n { | |
1353 | nvidia,pins = "reset_out_n"; | |
1354 | nvidia,function = "reset_out_n"; | |
1355 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1356 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
fb816641 | 1357 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
1358 | }; |
1359 | owr { | |
1360 | nvidia,pins = "owr"; | |
1361 | nvidia,function = "rsvd2"; | |
1362 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1363 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1364 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1365 | nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; | |
1366 | }; | |
1367 | clk_32k_in { | |
1368 | nvidia,pins = "clk_32k_in"; | |
fb816641 | 1369 | nvidia,function = "clk"; |
15e524a4 | 1370 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
fb816641 | 1371 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
1372 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
1373 | }; | |
1374 | jtag_rtck { | |
1375 | nvidia,pins = "jtag_rtck"; | |
1376 | nvidia,function = "rtck"; | |
1377 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1378 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1379 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1380 | }; | |
1381 | }; | |
1382 | }; | |
1383 | ||
c90bb7b9 RR |
1384 | /* |
1385 | * First high speed UART, exposed on the expansion connector J3A2 | |
1386 | * Pin 41: BR_UART1_TXD | |
1387 | * Pin 44: BR_UART1_RXD | |
1388 | */ | |
1389 | serial@70006000 { | |
1390 | compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; | |
1391 | status = "okay"; | |
1392 | }; | |
1393 | ||
1394 | /* | |
1395 | * Second high speed UART, exposed on the expansion connector J3A2 | |
1396 | * Pin 65: UART2_RXD | |
1397 | * Pin 68: UART2_TXD | |
1398 | * Pin 71: UART2_CTS_L | |
1399 | * Pin 74: UART2_RTS_L | |
1400 | */ | |
1401 | serial@70006040 { | |
1402 | compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; | |
1403 | status = "okay"; | |
1404 | }; | |
1405 | ||
15e524a4 SW |
1406 | /* DB9 serial port */ |
1407 | serial@0,70006300 { | |
1408 | status = "okay"; | |
1409 | }; | |
1410 | ||
1411 | /* Expansion GEN1_I2C_*, mini-PCIe I2C, on-board components */ | |
1412 | i2c@0,7000c000 { | |
1413 | status = "okay"; | |
1414 | clock-frequency = <100000>; | |
1415 | ||
98de744e SW |
1416 | rt5639: audio-codec@1c { |
1417 | compatible = "realtek,rt5639"; | |
15e524a4 SW |
1418 | reg = <0x1c>; |
1419 | interrupt-parent = <&gpio>; | |
1420 | interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>; | |
1421 | realtek,ldo1-en-gpios = | |
1422 | <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_HIGH>; | |
1423 | }; | |
1424 | ||
1425 | temperature-sensor@4c { | |
1426 | compatible = "ti,tmp451"; | |
1427 | reg = <0x4c>; | |
1428 | interrupt-parent = <&gpio>; | |
1429 | interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>; | |
1430 | }; | |
1431 | ||
1432 | eeprom@56 { | |
1433 | compatible = "atmel,24c02"; | |
1434 | reg = <0x56>; | |
1435 | pagesize = <8>; | |
1436 | }; | |
1437 | }; | |
1438 | ||
1439 | /* Expansion GEN2_I2C_* */ | |
1440 | i2c@0,7000c400 { | |
1441 | status = "okay"; | |
1442 | clock-frequency = <100000>; | |
1443 | }; | |
1444 | ||
1445 | /* Expansion CAM_I2C_* */ | |
1446 | i2c@0,7000c500 { | |
1447 | status = "okay"; | |
1448 | clock-frequency = <100000>; | |
1449 | }; | |
1450 | ||
1451 | /* HDMI DDC */ | |
6054dd39 | 1452 | hdmi_ddc: i2c@0,7000c700 { |
15e524a4 SW |
1453 | status = "okay"; |
1454 | clock-frequency = <100000>; | |
1455 | }; | |
1456 | ||
1457 | /* Expansion PWR_I2C_*, on-board components */ | |
1458 | i2c@0,7000d000 { | |
1459 | status = "okay"; | |
1460 | clock-frequency = <400000>; | |
1461 | ||
1462 | pmic: pmic@40 { | |
1463 | compatible = "ams,as3722"; | |
1464 | reg = <0x40>; | |
1465 | interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; | |
1466 | ||
1467 | ams,system-power-controller; | |
1468 | ||
1469 | #interrupt-cells = <2>; | |
1470 | interrupt-controller; | |
1471 | ||
1472 | gpio-controller; | |
1473 | #gpio-cells = <2>; | |
1474 | ||
1475 | pinctrl-names = "default"; | |
1476 | pinctrl-0 = <&as3722_default>; | |
1477 | ||
1478 | as3722_default: pinmux { | |
1479 | gpio0 { | |
1480 | pins = "gpio0"; | |
1481 | function = "gpio"; | |
1482 | bias-pull-down; | |
1483 | }; | |
1484 | ||
1485 | gpio1_2_4_7 { | |
1486 | pins = "gpio1", "gpio2", "gpio4", "gpio7"; | |
1487 | function = "gpio"; | |
1488 | bias-pull-up; | |
1489 | }; | |
1490 | ||
1491 | gpio3_5_6 { | |
1492 | pins = "gpio3", "gpio5", "gpio6"; | |
1493 | bias-high-impedance; | |
1494 | }; | |
1495 | }; | |
22b35776 SW |
1496 | |
1497 | regulators { | |
1498 | vsup-sd2-supply = <&vdd_5v0_sys>; | |
1499 | vsup-sd3-supply = <&vdd_5v0_sys>; | |
1500 | vsup-sd4-supply = <&vdd_5v0_sys>; | |
1501 | vsup-sd5-supply = <&vdd_5v0_sys>; | |
1502 | vin-ldo0-supply = <&vdd_1v35_lp0>; | |
1503 | vin-ldo1-6-supply = <&vdd_3v3_run>; | |
1504 | vin-ldo2-5-7-supply = <&vddio_1v8>; | |
1505 | vin-ldo3-4-supply = <&vdd_3v3_sys>; | |
1506 | vin-ldo9-10-supply = <&vdd_5v0_sys>; | |
1507 | vin-ldo11-supply = <&vdd_3v3_run>; | |
1508 | ||
9be1e477 | 1509 | vdd_cpu: sd0 { |
22b35776 SW |
1510 | regulator-name = "+VDD_CPU_AP"; |
1511 | regulator-min-microvolt = <700000>; | |
1512 | regulator-max-microvolt = <1400000>; | |
1513 | regulator-min-microamp = <3500000>; | |
1514 | regulator-max-microamp = <3500000>; | |
1515 | regulator-always-on; | |
1516 | regulator-boot-on; | |
ee913f7a | 1517 | ams,ext-control = <2>; |
22b35776 SW |
1518 | }; |
1519 | ||
1520 | sd1 { | |
1521 | regulator-name = "+VDD_CORE"; | |
1522 | regulator-min-microvolt = <700000>; | |
1523 | regulator-max-microvolt = <1350000>; | |
1524 | regulator-min-microamp = <2500000>; | |
1525 | regulator-max-microamp = <2500000>; | |
1526 | regulator-always-on; | |
1527 | regulator-boot-on; | |
ee913f7a | 1528 | ams,ext-control = <1>; |
22b35776 SW |
1529 | }; |
1530 | ||
1531 | vdd_1v35_lp0: sd2 { | |
1532 | regulator-name = "+1.35V_LP0(sd2)"; | |
1533 | regulator-min-microvolt = <1350000>; | |
1534 | regulator-max-microvolt = <1350000>; | |
1535 | regulator-always-on; | |
1536 | regulator-boot-on; | |
1537 | }; | |
1538 | ||
1539 | sd3 { | |
1540 | regulator-name = "+1.35V_LP0(sd3)"; | |
1541 | regulator-min-microvolt = <1350000>; | |
1542 | regulator-max-microvolt = <1350000>; | |
1543 | regulator-always-on; | |
1544 | regulator-boot-on; | |
1545 | }; | |
1546 | ||
6054dd39 | 1547 | vdd_1v05_run: sd4 { |
22b35776 SW |
1548 | regulator-name = "+1.05V_RUN"; |
1549 | regulator-min-microvolt = <1050000>; | |
1550 | regulator-max-microvolt = <1050000>; | |
1551 | }; | |
1552 | ||
1553 | vddio_1v8: sd5 { | |
1554 | regulator-name = "+1.8V_VDDIO"; | |
1555 | regulator-min-microvolt = <1800000>; | |
1556 | regulator-max-microvolt = <1800000>; | |
1557 | regulator-boot-on; | |
1558 | regulator-always-on; | |
1559 | }; | |
1560 | ||
21fa196f | 1561 | vdd_gpu: sd6 { |
22b35776 SW |
1562 | regulator-name = "+VDD_GPU_AP"; |
1563 | regulator-min-microvolt = <650000>; | |
1564 | regulator-max-microvolt = <1200000>; | |
1565 | regulator-min-microamp = <3500000>; | |
1566 | regulator-max-microamp = <3500000>; | |
1567 | regulator-boot-on; | |
1568 | regulator-always-on; | |
1569 | }; | |
1570 | ||
8e2b9e4d | 1571 | avdd_1v05_run: ldo0 { |
22b35776 SW |
1572 | regulator-name = "+1.05V_RUN_AVDD"; |
1573 | regulator-min-microvolt = <1050000>; | |
1574 | regulator-max-microvolt = <1050000>; | |
1575 | regulator-boot-on; | |
1576 | regulator-always-on; | |
ee913f7a | 1577 | ams,ext-control = <1>; |
22b35776 SW |
1578 | }; |
1579 | ||
1580 | ldo1 { | |
1581 | regulator-name = "+1.8V_RUN_CAM"; | |
1582 | regulator-min-microvolt = <1800000>; | |
1583 | regulator-max-microvolt = <1800000>; | |
1584 | }; | |
1585 | ||
1586 | ldo2 { | |
1587 | regulator-name = "+1.2V_GEN_AVDD"; | |
1588 | regulator-min-microvolt = <1200000>; | |
1589 | regulator-max-microvolt = <1200000>; | |
1590 | regulator-boot-on; | |
1591 | regulator-always-on; | |
1592 | }; | |
1593 | ||
1594 | ldo3 { | |
1595 | regulator-name = "+1.05V_LP0_VDD_RTC"; | |
1596 | regulator-min-microvolt = <1000000>; | |
1597 | regulator-max-microvolt = <1000000>; | |
1598 | regulator-boot-on; | |
1599 | regulator-always-on; | |
1600 | ams,enable-tracking; | |
1601 | }; | |
1602 | ||
1603 | ldo4 { | |
1604 | regulator-name = "+2.8V_RUN_CAM"; | |
1605 | regulator-min-microvolt = <2800000>; | |
1606 | regulator-max-microvolt = <2800000>; | |
1607 | }; | |
1608 | ||
1609 | ldo5 { | |
1610 | regulator-name = "+1.2V_RUN_CAM_FRONT"; | |
1611 | regulator-min-microvolt = <1200000>; | |
1612 | regulator-max-microvolt = <1200000>; | |
1613 | }; | |
1614 | ||
1615 | vddio_sdmmc3: ldo6 { | |
1616 | regulator-name = "+VDDIO_SDMMC3"; | |
1617 | regulator-min-microvolt = <1800000>; | |
1618 | regulator-max-microvolt = <3300000>; | |
1619 | }; | |
1620 | ||
1621 | ldo7 { | |
1622 | regulator-name = "+1.05V_RUN_CAM_REAR"; | |
1623 | regulator-min-microvolt = <1050000>; | |
1624 | regulator-max-microvolt = <1050000>; | |
1625 | }; | |
1626 | ||
1627 | ldo9 { | |
1628 | regulator-name = "+3.3V_RUN_TOUCH"; | |
1629 | regulator-min-microvolt = <2800000>; | |
1630 | regulator-max-microvolt = <2800000>; | |
1631 | }; | |
1632 | ||
1633 | ldo10 { | |
1634 | regulator-name = "+2.8V_RUN_CAM_AF"; | |
1635 | regulator-min-microvolt = <2800000>; | |
1636 | regulator-max-microvolt = <2800000>; | |
1637 | }; | |
1638 | ||
1639 | ldo11 { | |
1640 | regulator-name = "+1.8V_RUN_VPP_FUSE"; | |
1641 | regulator-min-microvolt = <1800000>; | |
1642 | regulator-max-microvolt = <1800000>; | |
1643 | }; | |
1644 | }; | |
15e524a4 SW |
1645 | }; |
1646 | }; | |
1647 | ||
1648 | /* Expansion TS_SPI_* */ | |
1649 | spi@0,7000d400 { | |
1650 | status = "okay"; | |
1651 | }; | |
1652 | ||
1653 | /* Internal SPI */ | |
1654 | spi@0,7000da00 { | |
1655 | status = "okay"; | |
1656 | spi-max-frequency = <25000000>; | |
1657 | spi-flash@0 { | |
1658 | compatible = "winbond,w25q32dw"; | |
1659 | reg = <0>; | |
1660 | spi-max-frequency = <20000000>; | |
1661 | }; | |
1662 | }; | |
1663 | ||
1664 | pmc@0,7000e400 { | |
1665 | nvidia,invert-interrupt; | |
1666 | nvidia,suspend-mode = <1>; | |
1667 | nvidia,cpu-pwr-good-time = <500>; | |
1668 | nvidia,cpu-pwr-off-time = <300>; | |
1669 | nvidia,core-pwr-good-time = <641 3845>; | |
1670 | nvidia,core-pwr-off-time = <61036>; | |
1671 | nvidia,core-power-req-active-high; | |
1672 | nvidia,sys-clock-req-active-high; | |
9c963301 MP |
1673 | |
1674 | i2c-thermtrip { | |
1675 | nvidia,i2c-controller-id = <4>; | |
1676 | nvidia,bus-addr = <0x40>; | |
1677 | nvidia,reg-addr = <0x36>; | |
1678 | nvidia,reg-data = <0x2>; | |
1679 | }; | |
15e524a4 SW |
1680 | }; |
1681 | ||
1b3ce99f MP |
1682 | /* Serial ATA */ |
1683 | sata@0,70020000 { | |
1684 | status = "okay"; | |
1685 | ||
87c68119 TR |
1686 | phys = <&{/padctl@0,7009f000/pads/sata/lanes/sata-0}>; |
1687 | phy-names = "sata-0"; | |
1688 | ||
1b3ce99f MP |
1689 | hvdd-supply = <&vdd_3v3_lp0>; |
1690 | vddio-supply = <&vdd_1v05_run>; | |
1691 | avdd-supply = <&vdd_1v05_run>; | |
1692 | ||
1693 | target-5v-supply = <&vdd_5v0_sata>; | |
1694 | target-12v-supply = <&vdd_12v0_sata>; | |
1695 | }; | |
1696 | ||
4c84472e TR |
1697 | hda@0,70030000 { |
1698 | status = "okay"; | |
1699 | }; | |
1700 | ||
87c68119 TR |
1701 | usb@0,70090000 { |
1702 | phys = <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-0}>, /* Micro A/B */ | |
1703 | <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-1}>, /* Mini PCIe */ | |
1704 | <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-2}>, /* USB3 */ | |
1705 | <&{/padctl@0,7009f000/pads/pcie/lanes/pcie-0}>; /* USB3 */ | |
1706 | phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0"; | |
1707 | ||
1708 | avddio-pex-supply = <&vdd_1v05_run>; | |
1709 | dvddio-pex-supply = <&vdd_1v05_run>; | |
1710 | avdd-usb-supply = <&vdd_3v3_lp0>; | |
1711 | avdd-pll-utmip-supply = <&vddio_1v8>; | |
1712 | avdd-pll-erefe-supply = <&avdd_1v05_run>; | |
1713 | avdd-usb-ss-pll-supply = <&vdd_1v05_run>; | |
1714 | hvdd-usb-ss-supply = <&vdd_3v3_lp0>; | |
1715 | hvdd-usb-ss-pll-e-supply = <&vdd_3v3_lp0>; | |
1716 | ||
1717 | status = "okay"; | |
1718 | }; | |
1719 | ||
62b8db08 | 1720 | padctl@0,7009f000 { |
87c68119 | 1721 | status = "okay"; |
62b8db08 | 1722 | |
87c68119 TR |
1723 | pads { |
1724 | usb2 { | |
1725 | status = "okay"; | |
1726 | ||
1727 | lanes { | |
1728 | usb2-0 { | |
1729 | nvidia,function = "xusb"; | |
1730 | status = "okay"; | |
1731 | }; | |
1732 | ||
1733 | usb2-1 { | |
1734 | nvidia,function = "xusb"; | |
1735 | status = "okay"; | |
1736 | }; | |
1737 | ||
1738 | usb2-2 { | |
1739 | nvidia,function = "xusb"; | |
1740 | status = "okay"; | |
1741 | }; | |
1742 | }; | |
62b8db08 TR |
1743 | }; |
1744 | ||
1745 | pcie { | |
87c68119 TR |
1746 | status = "okay"; |
1747 | ||
1748 | lanes { | |
1749 | pcie-0 { | |
1750 | nvidia,function = "usb3-ss"; | |
1751 | status = "okay"; | |
1752 | }; | |
1753 | ||
1754 | pcie-2 { | |
1755 | nvidia,function = "pcie"; | |
1756 | status = "okay"; | |
1757 | }; | |
1758 | ||
1759 | pcie-4 { | |
1760 | nvidia,function = "pcie"; | |
1761 | status = "okay"; | |
1762 | }; | |
1763 | }; | |
62b8db08 TR |
1764 | }; |
1765 | ||
1766 | sata { | |
87c68119 TR |
1767 | status = "okay"; |
1768 | ||
1769 | lanes { | |
1770 | sata-0 { | |
1771 | nvidia,function = "sata"; | |
1772 | status = "okay"; | |
1773 | }; | |
1774 | }; | |
1775 | }; | |
1776 | }; | |
1777 | ||
1778 | ports { | |
1779 | /* Micro A/B */ | |
1780 | usb2-0 { | |
1781 | status = "okay"; | |
1782 | mode = "otg"; | |
1783 | }; | |
1784 | ||
1785 | /* Mini PCIe */ | |
1786 | usb2-1 { | |
1787 | status = "okay"; | |
1788 | mode = "host"; | |
1789 | }; | |
1790 | ||
1791 | /* USB3 */ | |
1792 | usb2-2 { | |
1793 | status = "okay"; | |
1794 | mode = "host"; | |
1795 | ||
1796 | vbus-supply = <&vdd_usb3_vbus>; | |
1797 | }; | |
1798 | ||
1799 | usb3-0 { | |
1800 | nvidia,usb2-companion = <2>; | |
1801 | status = "okay"; | |
62b8db08 TR |
1802 | }; |
1803 | }; | |
1804 | }; | |
1805 | ||
15e524a4 SW |
1806 | /* SD card */ |
1807 | sdhci@0,700b0400 { | |
1808 | status = "okay"; | |
1809 | cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; | |
1810 | power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; | |
215f21c9 | 1811 | wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>; |
15e524a4 | 1812 | bus-width = <4>; |
9260764c | 1813 | vqmmc-supply = <&vddio_sdmmc3>; |
15e524a4 SW |
1814 | }; |
1815 | ||
1816 | /* eMMC */ | |
1817 | sdhci@0,700b0600 { | |
1818 | status = "okay"; | |
1819 | bus-width = <8>; | |
33f34f0c | 1820 | non-removable; |
15e524a4 SW |
1821 | }; |
1822 | ||
9be1e477 TT |
1823 | /* CPU DFLL clock */ |
1824 | clock@0,70110000 { | |
1825 | status = "okay"; | |
1826 | vdd-cpu-supply = <&vdd_cpu>; | |
1827 | nvidia,i2c-fs-rate = <400000>; | |
1828 | }; | |
1829 | ||
15e524a4 SW |
1830 | ahub@0,70300000 { |
1831 | i2s@0,70301100 { | |
1832 | status = "okay"; | |
1833 | }; | |
1834 | }; | |
1835 | ||
1836 | /* mini-PCIe USB */ | |
1837 | usb@0,7d004000 { | |
1838 | status = "okay"; | |
1839 | }; | |
1840 | ||
1841 | usb-phy@0,7d004000 { | |
1842 | status = "okay"; | |
1843 | }; | |
1844 | ||
1845 | /* USB A connector */ | |
1846 | usb@0,7d008000 { | |
1847 | status = "okay"; | |
1848 | }; | |
1849 | ||
1850 | usb-phy@0,7d008000 { | |
1851 | status = "okay"; | |
1852 | vbus-supply = <&vdd_usb3_vbus>; | |
1853 | }; | |
1854 | ||
1855 | clocks { | |
1856 | compatible = "simple-bus"; | |
1857 | #address-cells = <1>; | |
1858 | #size-cells = <0>; | |
1859 | ||
1860 | clk32k_in: clock@0 { | |
1861 | compatible = "fixed-clock"; | |
1862 | reg = <0>; | |
1863 | #clock-cells = <0>; | |
1864 | clock-frequency = <32768>; | |
1865 | }; | |
1866 | }; | |
1867 | ||
ee9f106f MP |
1868 | cpus { |
1869 | cpu@0 { | |
1870 | vdd-cpu-supply = <&vdd_cpu>; | |
1871 | }; | |
1872 | }; | |
1873 | ||
15e524a4 SW |
1874 | gpio-keys { |
1875 | compatible = "gpio-keys"; | |
1876 | ||
1877 | power { | |
1878 | label = "Power"; | |
1879 | gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; | |
1880 | linux,code = <KEY_POWER>; | |
1881 | debounce-interval = <10>; | |
d1c04d30 | 1882 | wakeup-source; |
15e524a4 SW |
1883 | }; |
1884 | }; | |
1885 | ||
1886 | regulators { | |
1887 | compatible = "simple-bus"; | |
1888 | #address-cells = <1>; | |
1889 | #size-cells = <0>; | |
1890 | ||
22b35776 SW |
1891 | vdd_mux: regulator@0 { |
1892 | compatible = "regulator-fixed"; | |
1893 | reg = <0>; | |
1894 | regulator-name = "+VDD_MUX"; | |
1895 | regulator-min-microvolt = <12000000>; | |
1896 | regulator-max-microvolt = <12000000>; | |
1897 | regulator-always-on; | |
1898 | regulator-boot-on; | |
1899 | }; | |
1900 | ||
1901 | vdd_5v0_sys: regulator@1 { | |
1902 | compatible = "regulator-fixed"; | |
1903 | reg = <1>; | |
1904 | regulator-name = "+5V_SYS"; | |
1905 | regulator-min-microvolt = <5000000>; | |
1906 | regulator-max-microvolt = <5000000>; | |
1907 | regulator-always-on; | |
1908 | regulator-boot-on; | |
1909 | vin-supply = <&vdd_mux>; | |
1910 | }; | |
1911 | ||
1912 | vdd_3v3_sys: regulator@2 { | |
1913 | compatible = "regulator-fixed"; | |
1914 | reg = <2>; | |
1915 | regulator-name = "+3.3V_SYS"; | |
1916 | regulator-min-microvolt = <3300000>; | |
1917 | regulator-max-microvolt = <3300000>; | |
1918 | regulator-always-on; | |
1919 | regulator-boot-on; | |
1920 | vin-supply = <&vdd_mux>; | |
1921 | }; | |
1922 | ||
1923 | vdd_3v3_run: regulator@3 { | |
1924 | compatible = "regulator-fixed"; | |
1925 | reg = <3>; | |
1926 | regulator-name = "+3.3V_RUN"; | |
1927 | regulator-min-microvolt = <3300000>; | |
1928 | regulator-max-microvolt = <3300000>; | |
1929 | regulator-always-on; | |
1930 | regulator-boot-on; | |
1931 | gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; | |
1932 | enable-active-high; | |
1933 | vin-supply = <&vdd_3v3_sys>; | |
1934 | }; | |
1935 | ||
1936 | vdd_3v3_hdmi: regulator@4 { | |
1937 | compatible = "regulator-fixed"; | |
1938 | reg = <4>; | |
1939 | regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; | |
1940 | regulator-min-microvolt = <3300000>; | |
1941 | regulator-max-microvolt = <3300000>; | |
1942 | vin-supply = <&vdd_3v3_run>; | |
1943 | }; | |
1944 | ||
1945 | vdd_usb1_vbus: regulator@7 { | |
1946 | compatible = "regulator-fixed"; | |
1947 | reg = <7>; | |
1948 | regulator-name = "+USB0_VBUS_SW"; | |
1949 | regulator-min-microvolt = <5000000>; | |
1950 | regulator-max-microvolt = <5000000>; | |
1951 | gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; | |
1952 | enable-active-high; | |
1953 | gpio-open-drain; | |
1954 | vin-supply = <&vdd_5v0_sys>; | |
1955 | }; | |
1956 | ||
15e524a4 SW |
1957 | vdd_usb3_vbus: regulator@8 { |
1958 | compatible = "regulator-fixed"; | |
1959 | reg = <8>; | |
1960 | regulator-name = "+5V_USB_HS"; | |
1961 | regulator-min-microvolt = <5000000>; | |
1962 | regulator-max-microvolt = <5000000>; | |
1963 | gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; | |
1964 | enable-active-high; | |
1965 | gpio-open-drain; | |
22b35776 SW |
1966 | vin-supply = <&vdd_5v0_sys>; |
1967 | }; | |
1968 | ||
1969 | vdd_3v3_lp0: regulator@10 { | |
1970 | compatible = "regulator-fixed"; | |
1971 | reg = <10>; | |
1972 | regulator-name = "+3.3V_LP0"; | |
1973 | regulator-min-microvolt = <3300000>; | |
1974 | regulator-max-microvolt = <3300000>; | |
1975 | regulator-always-on; | |
1976 | regulator-boot-on; | |
1977 | gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; | |
1978 | enable-active-high; | |
1979 | vin-supply = <&vdd_3v3_sys>; | |
15e524a4 | 1980 | }; |
6054dd39 TR |
1981 | |
1982 | vdd_hdmi_pll: regulator@11 { | |
1983 | compatible = "regulator-fixed"; | |
1984 | reg = <11>; | |
1985 | regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; | |
1986 | regulator-min-microvolt = <1050000>; | |
1987 | regulator-max-microvolt = <1050000>; | |
1988 | gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; | |
1989 | vin-supply = <&vdd_1v05_run>; | |
1990 | }; | |
1991 | ||
1992 | vdd_5v0_hdmi: regulator@12 { | |
1993 | compatible = "regulator-fixed"; | |
1994 | reg = <12>; | |
1995 | regulator-name = "+5V_HDMI_CON"; | |
1996 | regulator-min-microvolt = <5000000>; | |
1997 | regulator-max-microvolt = <5000000>; | |
1998 | gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; | |
1999 | enable-active-high; | |
2000 | vin-supply = <&vdd_5v0_sys>; | |
2001 | }; | |
1b3ce99f MP |
2002 | |
2003 | /* Molex power connector */ | |
2004 | vdd_5v0_sata: regulator@13 { | |
2005 | compatible = "regulator-fixed"; | |
2006 | reg = <13>; | |
2007 | regulator-name = "+5V_SATA"; | |
2008 | regulator-min-microvolt = <5000000>; | |
2009 | regulator-max-microvolt = <5000000>; | |
2010 | gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>; | |
2011 | enable-active-high; | |
2012 | vin-supply = <&vdd_5v0_sys>; | |
2013 | }; | |
2014 | ||
2015 | vdd_12v0_sata: regulator@14 { | |
2016 | compatible = "regulator-fixed"; | |
2017 | reg = <14>; | |
2018 | regulator-name = "+12V_SATA"; | |
2019 | regulator-min-microvolt = <12000000>; | |
2020 | regulator-max-microvolt = <12000000>; | |
2021 | gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>; | |
2022 | enable-active-high; | |
2023 | vin-supply = <&vdd_mux>; | |
2024 | }; | |
15e524a4 SW |
2025 | }; |
2026 | ||
2027 | sound { | |
2028 | compatible = "nvidia,tegra-audio-rt5640-jetson-tk1", | |
2029 | "nvidia,tegra-audio-rt5640"; | |
2030 | nvidia,model = "NVIDIA Tegra Jetson TK1"; | |
2031 | ||
2032 | nvidia,audio-routing = | |
2033 | "Headphones", "HPOR", | |
2034 | "Headphones", "HPOL", | |
2035 | "Mic Jack", "MICBIAS1", | |
2036 | "IN2P", "Mic Jack"; | |
2037 | ||
2038 | nvidia,i2s-controller = <&tegra_i2s1>; | |
98de744e | 2039 | nvidia,audio-codec = <&rt5639>; |
15e524a4 SW |
2040 | |
2041 | nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_LOW>; | |
2042 | ||
2043 | clocks = <&tegra_car TEGRA124_CLK_PLL_A>, | |
2044 | <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, | |
2045 | <&tegra_car TEGRA124_CLK_EXTERN1>; | |
2046 | clock-names = "pll_a", "pll_a_out0", "mclk"; | |
2047 | }; | |
ed7eac33 MP |
2048 | |
2049 | thermal-zones { | |
2050 | cpu { | |
2051 | trips { | |
2052 | trip@0 { | |
2053 | temperature = <101000>; | |
2054 | hysteresis = <0>; | |
2055 | type = "critical"; | |
2056 | }; | |
2057 | }; | |
2058 | ||
2059 | cooling-maps { | |
2060 | /* There are currently no cooling maps because there are no cooling devices */ | |
2061 | }; | |
2062 | }; | |
2063 | ||
2064 | mem { | |
2065 | trips { | |
2066 | trip@0 { | |
2067 | temperature = <101000>; | |
2068 | hysteresis = <0>; | |
2069 | type = "critical"; | |
2070 | }; | |
2071 | }; | |
2072 | ||
2073 | cooling-maps { | |
2074 | /* There are currently no cooling maps because there are no cooling devices */ | |
2075 | }; | |
2076 | }; | |
2077 | ||
2078 | gpu { | |
2079 | trips { | |
2080 | trip@0 { | |
2081 | temperature = <101000>; | |
2082 | hysteresis = <0>; | |
2083 | type = "critical"; | |
2084 | }; | |
2085 | }; | |
2086 | ||
2087 | cooling-maps { | |
2088 | /* There are currently no cooling maps because there are no cooling devices */ | |
2089 | }; | |
2090 | }; | |
2091 | }; | |
15e524a4 | 2092 | }; |