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ARM: tegra: Enable USB on Venice2
[deliverable/linux.git] / arch / arm / boot / dts / tegra124-venice2.dts
CommitLineData
a1425d42
JL		 1/dts-v1/;
2
146db0ea 3#include <dt-bindings/input/input.h>
a1425d42
JL		 4#include "tegra124.dtsi"
5
6/ {
7 model = "NVIDIA Tegra124 Venice2";
8 compatible = "nvidia,venice2", "nvidia,tegra124";
9
b1afa782
SW		 10 aliases {
11 rtc0 = "/i2c@7000d000/as3722@40";
12 rtc1 = "/rtc@7000e000";
13 };
14
a1425d42
JL		 15 memory {
16 reg = <0x80000000 0x80000000>;
17 };
18
40e231c7
TR		 19 host1x@50000000 {
20 sor@54540000 {
21 status = "okay";
22
23 nvidia,dpaux = <&dpaux>;
24 nvidia,panel = <&panel>;
25 };
26
27 dpaux: dpaux@545c0000 {
28 vdd-supply = <&vdd_3v3_panel>;
29 status = "okay";
30 };
31 };
32
4b20bcbe
LD		 33 pinmux: pinmux@70000868 {
34 pinctrl-names = "default";
35 pinctrl-0 = <&pinmux_default>;
36
37 pinmux_default: common {
38 dap_mclk1_pw4 {
39 nvidia,pins = "dap_mclk1_pw4";
40 nvidia,function = "extperiph1";
41 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
42 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
43 nvidia,tristate = <TEGRA_PIN_DISABLE>;
44 };
45 dap1_din_pn1 {
365c483f
LD		 46 nvidia,pins = "dap1_din_pn1";
47 nvidia,function = "i2s0";
48 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
49 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
50 nvidia,tristate = <TEGRA_PIN_ENABLE>;
51 };
52 dap1_dout_pn2 {
53 nvidia,pins = "dap1_dout_pn2",
4b20bcbe
LD		 54 "dap1_fs_pn0",
55 "dap1_sclk_pn3";
56 nvidia,function = "i2s0";
365c483f 57 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4b20bcbe
LD		 58 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
59 nvidia,tristate = <TEGRA_PIN_ENABLE>;
60 };
61 dap2_din_pa4 {
365c483f 62 nvidia,pins = "dap2_din_pa4";
4b20bcbe
LD		 63 nvidia,function = "i2s1";
64 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
65 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4ffb9385 66 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4b20bcbe 67 };
365c483f
LD		 68 dap2_dout_pa5 {
69 nvidia,pins = "dap2_dout_pa5",
70 "dap2_fs_pa2",
71 "dap2_sclk_pa3";
72 nvidia,function = "i2s1";
4b20bcbe
LD		 73 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
74 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
365c483f 75 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4b20bcbe 76 };
365c483f
LD		 77 dvfs_pwm_px0 {
78 nvidia,pins = "dvfs_pwm_px0",
79 "dvfs_clk_px2";
4b20bcbe
LD		 80 nvidia,function = "cldvfs";
81 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
82 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
83 nvidia,tristate = <TEGRA_PIN_DISABLE>;
84 };
85 ulpi_clk_py0 {
86 nvidia,pins = "ulpi_clk_py0",
4b20bcbe
LD		 87 "ulpi_nxt_py2",
88 "ulpi_stp_py3";
89 nvidia,function = "spi1";
365c483f
LD		 90 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
91 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
92 nvidia,tristate = <TEGRA_PIN_DISABLE>;
93 };
94 ulpi_dir_py1 {
95 nvidia,pins = "ulpi_dir_py1";
96 nvidia,function = "spi1";
4b20bcbe 97 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
365c483f 98 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4b20bcbe
LD		 99 nvidia,tristate = <TEGRA_PIN_DISABLE>;
100 };
101 cam_i2c_scl_pbb1 {
102 nvidia,pins = "cam_i2c_scl_pbb1",
103 "cam_i2c_sda_pbb2";
104 nvidia,function = "i2c3";
105 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
106 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
107 nvidia,tristate = <TEGRA_PIN_DISABLE>;
108 nvidia,lock = <TEGRA_PIN_DISABLE>;
109 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
110 };
111 gen2_i2c_scl_pt5 {
112 nvidia,pins = "gen2_i2c_scl_pt5",
113 "gen2_i2c_sda_pt6";
114 nvidia,function = "i2c2";
115 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
116 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
117 nvidia,tristate = <TEGRA_PIN_DISABLE>;
118 nvidia,lock = <TEGRA_PIN_DISABLE>;
119 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
120 };
121 pg4 {
122 nvidia,pins = "pg4",
123 "pg5",
124 "pg6",
4b20bcbe
LD		 125 "pi3";
126 nvidia,function = "spi4";
127 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
128 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
129 nvidia,tristate = <TEGRA_PIN_DISABLE>;
130 };
365c483f
LD		 131 pg7 {
132 nvidia,pins = "pg7";
133 nvidia,function = "spi4";
4b20bcbe 134 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
365c483f
LD		 135 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
136 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4b20bcbe
LD		 137 };
138 ph1 {
139 nvidia,pins = "ph1";
140 nvidia,function = "pwm1";
141 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
142 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
143 nvidia,tristate = <TEGRA_PIN_DISABLE>;
144 };
365c483f
LD		 145 pk0 {
146 nvidia,pins = "pk0",
147 "kb_row15_ps7",
148 "clk_32k_out_pa0";
149 nvidia,function = "soc";
150 nvidia,pull = <TEGRA_PIN_PULL_UP>;
f5cb19b4 151 nvidia,tristate = <TEGRA_PIN_DISABLE>;
365c483f 152 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
f5cb19b4 153 };
4b20bcbe
LD		 154 sdmmc1_clk_pz0 {
155 nvidia,pins = "sdmmc1_clk_pz0",
156 "sdmmc1_cmd_pz1",
157 "sdmmc1_dat0_py7",
158 "sdmmc1_dat1_py6",
159 "sdmmc1_dat2_py5",
160 "sdmmc1_dat3_py4";
161 nvidia,function = "sdmmc1";
162 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
163 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
164 nvidia,tristate = <TEGRA_PIN_DISABLE>;
165 };
365c483f
LD		 166 sdmmc1_cmd_pz1 {
167 nvidia,pins = "sdmmc1_cmd_pz1",
168 "sdmmc1_dat0_py7",
169 "sdmmc1_dat1_py6",
170 "sdmmc1_dat2_py5",
171 "sdmmc1_dat3_py4";
172 nvidia,function = "sdmmc1";
173 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
174 nvidia,pull = <TEGRA_PIN_PULL_UP>;
175 nvidia,tristate = <TEGRA_PIN_DISABLE>;
176 };
4b20bcbe
LD		 177 sdmmc3_clk_pa6 {
178 nvidia,pins = "sdmmc3_clk_pa6";
179 nvidia,function = "sdmmc3";
180 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
181 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
182 nvidia,tristate = <TEGRA_PIN_DISABLE>;
183 };
184 sdmmc3_cmd_pa7 {
185 nvidia,pins = "sdmmc3_cmd_pa7",
186 "sdmmc3_dat0_pb7",
187 "sdmmc3_dat1_pb6",
188 "sdmmc3_dat2_pb5",
189 "sdmmc3_dat3_pb4",
190 "sdmmc3_clk_lb_out_pee4",
191 "sdmmc3_clk_lb_in_pee5";
192 nvidia,function = "sdmmc3";
193 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
194 nvidia,pull = <TEGRA_PIN_PULL_UP>;
195 nvidia,tristate = <TEGRA_PIN_DISABLE>;
196 };
197 sdmmc4_clk_pcc4 {
198 nvidia,pins = "sdmmc4_clk_pcc4";
199 nvidia,function = "sdmmc4";
200 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
201 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
202 nvidia,tristate = <TEGRA_PIN_DISABLE>;
203 };
204 sdmmc4_cmd_pt7 {
205 nvidia,pins = "sdmmc4_cmd_pt7",
206 "sdmmc4_dat0_paa0",
207 "sdmmc4_dat1_paa1",
208 "sdmmc4_dat2_paa2",
209 "sdmmc4_dat3_paa3",
210 "sdmmc4_dat4_paa4",
211 "sdmmc4_dat5_paa5",
212 "sdmmc4_dat6_paa6",
213 "sdmmc4_dat7_paa7";
214 nvidia,function = "sdmmc4";
215 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
216 nvidia,pull = <TEGRA_PIN_PULL_UP>;
217 nvidia,tristate = <TEGRA_PIN_DISABLE>;
218 };
219 pwr_i2c_scl_pz6 {
220 nvidia,pins = "pwr_i2c_scl_pz6",
221 "pwr_i2c_sda_pz7";
222 nvidia,function = "i2cpwr";
223 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
224 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
225 nvidia,tristate = <TEGRA_PIN_DISABLE>;
365c483f 226 nvidia,lock = <TEGRA_PIN_DISABLE>;
4b20bcbe
LD		 227 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
228 };
229 jtag_rtck {
230 nvidia,pins = "jtag_rtck";
231 nvidia,function = "rtck";
232 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
233 nvidia,pull = <TEGRA_PIN_PULL_UP>;
234 nvidia,tristate = <TEGRA_PIN_DISABLE>;
235 };
236 clk_32k_in {
237 nvidia,pins = "clk_32k_in";
238 nvidia,function = "clk";
239 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
240 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
241 nvidia,tristate = <TEGRA_PIN_DISABLE>;
242 };
243 core_pwr_req {
244 nvidia,pins = "core_pwr_req";
245 nvidia,function = "pwron";
246 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
247 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
248 nvidia,tristate = <TEGRA_PIN_DISABLE>;
249 };
250 cpu_pwr_req {
251 nvidia,pins = "cpu_pwr_req";
252 nvidia,function = "cpu";
253 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
254 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
255 nvidia,tristate = <TEGRA_PIN_DISABLE>;
256 };
257 pwr_int_n {
258 nvidia,pins = "pwr_int_n";
259 nvidia,function = "pmi";
260 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
261 nvidia,pull = <TEGRA_PIN_PULL_UP>;
262 nvidia,tristate = <TEGRA_PIN_DISABLE>;
263 };
264 reset_out_n {
265 nvidia,pins = "reset_out_n";
266 nvidia,function = "reset_out_n";
267 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
268 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
269 nvidia,tristate = <TEGRA_PIN_DISABLE>;
270 };
271 clk3_out_pee0 {
272 nvidia,pins = "clk3_out_pee0";
273 nvidia,function = "extperiph3";
274 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
275 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
276 nvidia,tristate = <TEGRA_PIN_DISABLE>;
277 };
278 dap4_din_pp5 {
365c483f
LD		 279 nvidia,pins = "dap4_din_pp5";
280 nvidia,function = "i2s3";
281 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
282 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
283 nvidia,tristate = <TEGRA_PIN_ENABLE>;
284 };
285 dap4_dout_pp6 {
286 nvidia,pins = "dap4_dout_pp6",
4b20bcbe
LD		 287 "dap4_fs_pp4",
288 "dap4_sclk_pp7";
289 nvidia,function = "i2s3";
365c483f 290 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4b20bcbe
LD		 291 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
292 nvidia,tristate = <TEGRA_PIN_ENABLE>;
293 };
294 gen1_i2c_sda_pc5 {
295 nvidia,pins = "gen1_i2c_sda_pc5",
296 "gen1_i2c_scl_pc4";
297 nvidia,function = "i2c1";
298 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
299 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
300 nvidia,tristate = <TEGRA_PIN_DISABLE>;
301 nvidia,lock = <TEGRA_PIN_DISABLE>;
365c483f 302 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
4b20bcbe 303 };
365c483f
LD		 304 uart2_cts_n_pj5 {
305 nvidia,pins = "uart2_cts_n_pj5";
306 nvidia,function = "uartb";
4b20bcbe 307 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4ffb9385 308 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4b20bcbe
LD		 309 nvidia,tristate = <TEGRA_PIN_DISABLE>;
310 };
365c483f
LD		 311 uart2_rts_n_pj6 {
312 nvidia,pins = "uart2_rts_n_pj6";
4b20bcbe 313 nvidia,function = "uartb";
365c483f 314 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4b20bcbe
LD		 315 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
316 nvidia,tristate = <TEGRA_PIN_DISABLE>;
317 };
318 uart2_rxd_pc3 {
365c483f 319 nvidia,pins = "uart2_rxd_pc3";
4b20bcbe
LD		 320 nvidia,function = "irda";
321 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
322 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
323 nvidia,tristate = <TEGRA_PIN_DISABLE>;
324 };
365c483f
LD		 325 uart2_txd_pc2 {
326 nvidia,pins = "uart2_txd_pc2";
327 nvidia,function = "irda";
328 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
329 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
330 nvidia,tristate = <TEGRA_PIN_DISABLE>;
331 };
4b20bcbe
LD		 332 uart3_cts_n_pa1 {
333 nvidia,pins = "uart3_cts_n_pa1",
365c483f 334 "uart3_rxd_pw7";
4b20bcbe
LD		 335 nvidia,function = "uartc";
336 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
337 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
338 nvidia,tristate = <TEGRA_PIN_DISABLE>;
339 };
365c483f
LD		 340 uart3_rts_n_pc0 {
341 nvidia,pins = "uart3_rts_n_pc0",
342 "uart3_txd_pw6";
343 nvidia,function = "uartc";
344 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
345 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
346 nvidia,tristate = <TEGRA_PIN_DISABLE>;
347 };
4b20bcbe
LD		 348 hdmi_cec_pee3 {
349 nvidia,pins = "hdmi_cec_pee3";
350 nvidia,function = "cec";
351 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
352 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
353 nvidia,tristate = <TEGRA_PIN_DISABLE>;
365c483f
LD		 354 nvidia,lock = <TEGRA_PIN_DISABLE>;
355 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
356 };
357 hdmi_int_pn7 {
358 nvidia,pins = "hdmi_int_pn7";
359 nvidia,function = "rsvd1";
360 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
361 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
362 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4b20bcbe
LD		 363 };
364 ddc_scl_pv4 {
365 nvidia,pins = "ddc_scl_pv4",
366 "ddc_sda_pv5";
367 nvidia,function = "i2c4";
368 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
369 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
370 nvidia,tristate = <TEGRA_PIN_DISABLE>;
365c483f
LD		 371 nvidia,lock = <TEGRA_PIN_DISABLE>;
372 nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
373 };
374 pj7 {
375 nvidia,pins = "pj7",
376 "pk7";
377 nvidia,function = "uartd";
378 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
379 nvidia,tristate = <TEGRA_PIN_DISABLE>;
380 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
381 };
382 pb0 {
383 nvidia,pins = "pb0",
384 "pb1";
385 nvidia,function = "uartd";
386 nvidia,pull = <TEGRA_PIN_PULL_UP>;
387 nvidia,tristate = <TEGRA_PIN_DISABLE>;
388 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
389 };
390 ph0 {
391 nvidia,pins = "ph0";
392 nvidia,function = "pwm0";
393 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
394 nvidia,tristate = <TEGRA_PIN_DISABLE>;
395 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
396 };
397 kb_row10_ps2 {
398 nvidia,pins = "kb_row10_ps2";
399 nvidia,function = "uarta";
400 nvidia,pull = <TEGRA_PIN_PULL_UP>;
401 nvidia,tristate = <TEGRA_PIN_DISABLE>;
402 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
403 };
404 kb_row9_ps1 {
405 nvidia,pins = "kb_row9_ps1";
406 nvidia,function = "uarta";
407 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
408 nvidia,tristate = <TEGRA_PIN_DISABLE>;
409 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
410 };
411 kb_row6_pr6 {
412 nvidia,pins = "kb_row6_pr6";
413 nvidia,function = "displaya_alt";
414 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
415 nvidia,tristate = <TEGRA_PIN_DISABLE>;
416 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4b20bcbe
LD		 417 };
418 usb_vbus_en0_pn4 {
fa15ffaa
TR		 419 nvidia,pins = "usb_vbus_en0_pn4",
420 "usb_vbus_en1_pn5";
4b20bcbe
LD		 421 nvidia,function = "usb";
422 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
fa15ffaa 423 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4b20bcbe
LD		 424 nvidia,tristate = <TEGRA_PIN_DISABLE>;
425 nvidia,lock = <TEGRA_PIN_DISABLE>;
365c483f 426 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
4b20bcbe
LD		 427 };
428 drive_sdio1 {
429 nvidia,pins = "drive_sdio1";
430 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
431 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
432 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
433 nvidia,pull-down-strength = <32>;
434 nvidia,pull-up-strength = <42>;
435 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
436 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
437 };
438 drive_sdio3 {
439 nvidia,pins = "drive_sdio3";
440 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
441 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
442 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
443 nvidia,pull-down-strength = <20>;
444 nvidia,pull-up-strength = <36>;
445 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
446 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
447 };
448 drive_gma {
449 nvidia,pins = "drive_gma";
450 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
451 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
452 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
453 nvidia,pull-down-strength = <1>;
454 nvidia,pull-up-strength = <2>;
455 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
456 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
457 nvidia,drive-type = <1>;
458 };
365c483f
LD		 459 als_irq_l {
460 nvidia,pins = "gpio_x3_aud_px3";
461 nvidia,function = "gmi";
462 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
463 nvidia,tristate = <TEGRA_PIN_ENABLE>;
464 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
465 };
466 codec_irq_l {
467 nvidia,pins = "ph4";
468 nvidia,function = "gmi";
469 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
470 nvidia,tristate = <TEGRA_PIN_DISABLE>;
471 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
472 };
473 lcd_bl_en {
474 nvidia,pins = "ph2";
475 nvidia,function = "gmi";
476 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
477 nvidia,tristate = <TEGRA_PIN_DISABLE>;
478 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
479 };
480 touch_irq_l {
481 nvidia,pins = "gpio_w3_aud_pw3";
482 nvidia,function = "spi6";
483 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
484 nvidia,tristate = <TEGRA_PIN_ENABLE>;
485 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
486 };
487 tpm_davint_l {
488 nvidia,pins = "ph6";
489 nvidia,function = "gmi";
490 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
491 nvidia,tristate = <TEGRA_PIN_ENABLE>;
492 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
493 };
494 ts_irq_l {
495 nvidia,pins = "pk2";
496 nvidia,function = "gmi";
497 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
498 nvidia,tristate = <TEGRA_PIN_ENABLE>;
499 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
500 };
501 ts_reset_l {
502 nvidia,pins = "pk4";
503 nvidia,function = "gmi";
504 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
505 nvidia,tristate = <TEGRA_PIN_DISABLE>;
506 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
507 };
508 ts_shdn_l {
509 nvidia,pins = "pk1";
510 nvidia,function = "gmi";
511 nvidia,pull = <TEGRA_PIN_PULL_UP>;
512 nvidia,tristate = <TEGRA_PIN_DISABLE>;
513 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
514 };
515 ph7 {
516 nvidia,pins = "ph7";
517 nvidia,function = "gmi";
518 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
519 nvidia,tristate = <TEGRA_PIN_DISABLE>;
520 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
521 };
522 kb_col0_ap {
523 nvidia,pins = "kb_col0_pq0";
524 nvidia,function = "rsvd4";
525 nvidia,pull = <TEGRA_PIN_PULL_UP>;
526 nvidia,tristate = <TEGRA_PIN_DISABLE>;
527 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
528 };
529 lid_open {
530 nvidia,pins = "kb_row4_pr4";
531 nvidia,function = "rsvd3";
532 nvidia,pull = <TEGRA_PIN_PULL_UP>;
533 nvidia,tristate = <TEGRA_PIN_DISABLE>;
534 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
535 };
536 en_vdd_sd {
537 nvidia,pins = "kb_row0_pr0";
538 nvidia,function = "rsvd4";
539 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
540 nvidia,tristate = <TEGRA_PIN_DISABLE>;
541 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
542 };
543 ac_ok {
544 nvidia,pins = "pj0";
545 nvidia,function = "gmi";
546 nvidia,pull = <TEGRA_PIN_PULL_UP>;
547 nvidia,tristate = <TEGRA_PIN_ENABLE>;
548 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
549 };
550 sensor_irq_l {
551 nvidia,pins = "pi6";
552 nvidia,function = "gmi";
553 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
554 nvidia,tristate = <TEGRA_PIN_DISABLE>;
555 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
556 };
557 wifi_en {
558 nvidia,pins = "gpio_x7_aud_px7";
559 nvidia,function = "rsvd4";
560 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
561 nvidia,tristate = <TEGRA_PIN_DISABLE>;
562 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
563 };
564 wifi_rst_l {
565 nvidia,pins = "clk2_req_pcc5";
566 nvidia,function = "dap";
567 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
568 nvidia,tristate = <TEGRA_PIN_DISABLE>;
569 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
570 };
571 hp_det_l {
572 nvidia,pins = "ulpi_data1_po2";
573 nvidia,function = "spi3";
574 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
575 nvidia,tristate = <TEGRA_PIN_DISABLE>;
576 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
577 };
4b20bcbe
LD		 578 };
579 };
580
a1425d42
JL		 581 serial@70006000 {
582 status = "okay";
583 };
584
e013485d
TR		 585 pwm: pwm@7000a000 {
586 status = "okay";
587 };
588
9d5b2505
SW		 589 i2c@7000c000 {
590 status = "okay";
591 clock-frequency = <100000>;
b0e1caee
SW		 592
593 acodec: audio-codec@10 {
594 compatible = "maxim,max98090";
595 reg = <0x10>;
596 interrupt-parent = <&gpio>;
597 interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
598 };
9d5b2505
SW		 599 };
600
601 i2c@7000c400 {
602 status = "okay";
603 clock-frequency = <100000>;
604 };
605
606 i2c@7000c500 {
607 status = "okay";
608 clock-frequency = <100000>;
609 };
610
611 i2c@7000c700 {
612 status = "okay";
613 clock-frequency = <100000>;
614 };
615
616 i2c@7000d000 {
617 status = "okay";
fcacaba7
LD		 618 clock-frequency = <400000>;
619
620 as3722: as3722@40 {
621 compatible = "ams,as3722";
622 reg = <0x40>;
623 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
624
7be75df2
LD		 625 ams,system-power-controller;
626
fcacaba7
LD		 627 #interrupt-cells = <2>;
628 interrupt-controller;
629
630 gpio-controller;
631 #gpio-cells = <2>;
632
633 pinctrl-names = "default";
634 pinctrl-0 = <&as3722_default>;
635
636 as3722_default: pinmux {
637 gpio0 {
638 pins = "gpio0";
639 function = "gpio";
640 bias-pull-down;
641 };
642
643 gpio1_2_4_7 {
644 pins = "gpio1", "gpio2", "gpio4", "gpio7";
645 function = "gpio";
646 bias-pull-up;
647 };
648
649 gpio3_6 {
650 pins = "gpio3", "gpio6";
651 bias-high-impedance;
652 };
653
654 gpio5 {
655 pins = "gpio5";
656 function = "clk32k-out";
657 };
658 };
659
660 regulators {
af144b8d
TR		 661 vsup-sd2-supply = <&vdd_5v0_sys>;
662 vsup-sd3-supply = <&vdd_5v0_sys>;
663 vsup-sd4-supply = <&vdd_5v0_sys>;
664 vsup-sd5-supply = <&vdd_5v0_sys>;
665 vin-ldo0-supply = <&vdd_1v35_lp0>;
666 vin-ldo1-6-supply = <&vdd_3v3_run>;
667 vin-ldo2-5-7-supply = <&vddio_1v8>;
668 vin-ldo3-4-supply = <&vdd_3v3_sys>;
669 vin-ldo9-10-supply = <&vdd_5v0_sys>;
670 vin-ldo11-supply = <&vdd_3v3_run>;
fcacaba7
LD		 671
672 sd0 {
af144b8d 673 regulator-name = "+VDD_CPU_AP";
fcacaba7
LD		 674 regulator-min-microvolt = <700000>;
675 regulator-max-microvolt = <1400000>;
676 regulator-min-microamp = <3500000>;
677 regulator-max-microamp = <3500000>;
678 regulator-always-on;
679 regulator-boot-on;
680 ams,external-control = <2>;
681 };
682
683 sd1 {
af144b8d 684 regulator-name = "+VDD_CORE";
fcacaba7
LD		 685 regulator-min-microvolt = <700000>;
686 regulator-max-microvolt = <1350000>;
687 regulator-min-microamp = <2500000>;
688 regulator-max-microamp = <2500000>;
689 regulator-always-on;
690 regulator-boot-on;
691 ams,external-control = <1>;
692 };
693
af144b8d
TR		 694 vdd_1v35_lp0: sd2 {
695 regulator-name = "+1.35V_LP0(sd2)";
fcacaba7
LD		 696 regulator-min-microvolt = <1350000>;
697 regulator-max-microvolt = <1350000>;
698 regulator-always-on;
699 regulator-boot-on;
700 };
701
702 sd3 {
af144b8d 703 regulator-name = "+1.35V_LP0(sd3)";
fcacaba7
LD		 704 regulator-min-microvolt = <1350000>;
705 regulator-max-microvolt = <1350000>;
706 regulator-always-on;
707 regulator-boot-on;
708 };
709
710 sd4 {
af144b8d 711 regulator-name = "+1.05V_RUN";
fcacaba7
LD		 712 regulator-min-microvolt = <1050000>;
713 regulator-max-microvolt = <1050000>;
fcacaba7
LD		 714 };
715
af144b8d
TR		 716 vddio_1v8: sd5 {
717 regulator-name = "+1.8V_VDDIO";
fcacaba7
LD		 718 regulator-min-microvolt = <1800000>;
719 regulator-max-microvolt = <1800000>;
720 regulator-boot-on;
721 regulator-always-on;
722 };
723
724 sd6 {
af144b8d 725 regulator-name = "+VDD_GPU_AP";
fcacaba7
LD		 726 regulator-min-microvolt = <650000>;
727 regulator-max-microvolt = <1200000>;
728 regulator-min-microamp = <3500000>;
729 regulator-max-microamp = <3500000>;
730 regulator-boot-on;
731 regulator-always-on;
732 };
733
734 ldo0 {
af144b8d 735 regulator-name = "+1.05V_RUN_AVDD";
fcacaba7
LD		 736 regulator-min-microvolt = <1050000>;
737 regulator-max-microvolt = <1050000>;
738 regulator-boot-on;
739 regulator-always-on;
740 ams,external-control = <1>;
741 };
742
743 ldo1 {
af144b8d 744 regulator-name = "+1.8V_RUN_CAM";
fcacaba7
LD		 745 regulator-min-microvolt = <1800000>;
746 regulator-max-microvolt = <1800000>;
747 };
748
749 ldo2 {
af144b8d 750 regulator-name = "+1.2V_GEN_AVDD";
fcacaba7
LD		 751 regulator-min-microvolt = <1200000>;
752 regulator-max-microvolt = <1200000>;
753 regulator-boot-on;
754 regulator-always-on;
755 };
756
757 ldo3 {
af144b8d 758 regulator-name = "+1.00V_LP0_VDD_RTC";
fcacaba7
LD		 759 regulator-min-microvolt = <1000000>;
760 regulator-max-microvolt = <1000000>;
761 regulator-boot-on;
762 regulator-always-on;
763 ams,enable-tracking;
764 };
765
431b7be0 766 vdd_run_cam: ldo4 {
af144b8d 767 regulator-name = "+3.3V_RUN_CAM";
fcacaba7
LD		 768 regulator-min-microvolt = <2800000>;
769 regulator-max-microvolt = <2800000>;
fcacaba7
LD		 770 };
771
772 ldo5 {
af144b8d 773 regulator-name = "+1.2V_RUN_CAM_FRONT";
fcacaba7
LD		 774 regulator-min-microvolt = <1200000>;
775 regulator-max-microvolt = <1200000>;
776 };
777
4989b439 778 vddio_sdmmc3: ldo6 {
af144b8d 779 regulator-name = "+VDDIO_SDMMC3";
fcacaba7
LD		 780 regulator-min-microvolt = <1800000>;
781 regulator-max-microvolt = <3300000>;
fcacaba7
LD		 782 };
783
784 ldo7 {
af144b8d 785 regulator-name = "+1.05V_RUN_CAM_REAR";
fcacaba7
LD		 786 regulator-min-microvolt = <1050000>;
787 regulator-max-microvolt = <1050000>;
788 };
789
790 ldo9 {
af144b8d 791 regulator-name = "+2.8V_RUN_TOUCH";
fcacaba7
LD		 792 regulator-min-microvolt = <2800000>;
793 regulator-max-microvolt = <2800000>;
794 };
795
796 ldo10 {
af144b8d 797 regulator-name = "+2.8V_RUN_CAM_AF";
fcacaba7
LD		 798 regulator-min-microvolt = <2800000>;
799 regulator-max-microvolt = <2800000>;
800 };
801
802 ldo11 {
af144b8d 803 regulator-name = "+1.8V_RUN_VPP_FUSE";
fcacaba7
LD		 804 regulator-min-microvolt = <1800000>;
805 regulator-max-microvolt = <1800000>;
806 };
807 };
808 };
9d5b2505
SW		 809 };
810
146db0ea
TR		 811 spi@7000d400 {
812 status = "okay";
813
814 cros-ec@0 {
815 compatible = "google,cros-ec-spi";
816 spi-max-frequency = <4000000>;
817 interrupt-parent = <&gpio>;
818 interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>;
819 reg = <0>;
820
821 google,cros-ec-spi-msg-delay = <2000>;
822
823 cros-ec-keyb {
824 compatible = "google,cros-ec-keyb";
825 keypad,num-rows = <8>;
826 keypad,num-columns = <13>;
827 google,needs-ghost-filter;
828
829 linux,keymap = <
830 MATRIX_KEY(0x00, 0x01, KEY_LEFTMETA)
831 MATRIX_KEY(0x00, 0x02, KEY_F1)
832 MATRIX_KEY(0x00, 0x03, KEY_B)
833 MATRIX_KEY(0x00, 0x04, KEY_F10)
834 MATRIX_KEY(0x00, 0x06, KEY_N)
835 MATRIX_KEY(0x00, 0x08, KEY_EQUAL)
836 MATRIX_KEY(0x00, 0x0a, KEY_RIGHTALT)
837
838 MATRIX_KEY(0x01, 0x01, KEY_ESC)
839 MATRIX_KEY(0x01, 0x02, KEY_F4)
840 MATRIX_KEY(0x01, 0x03, KEY_G)
841 MATRIX_KEY(0x01, 0x04, KEY_F7)
842 MATRIX_KEY(0x01, 0x06, KEY_H)
843 MATRIX_KEY(0x01, 0x08, KEY_APOSTROPHE)
844 MATRIX_KEY(0x01, 0x09, KEY_F9)
845 MATRIX_KEY(0x01, 0x0b, KEY_BACKSPACE)
846
847 MATRIX_KEY(0x02, 0x00, KEY_LEFTCTRL)
848 MATRIX_KEY(0x02, 0x01, KEY_TAB)
849 MATRIX_KEY(0x02, 0x02, KEY_F3)
850 MATRIX_KEY(0x02, 0x03, KEY_T)
851 MATRIX_KEY(0x02, 0x04, KEY_F6)
852 MATRIX_KEY(0x02, 0x05, KEY_RIGHTBRACE)
853 MATRIX_KEY(0x02, 0x06, KEY_Y)
854 MATRIX_KEY(0x02, 0x07, KEY_102ND)
855 MATRIX_KEY(0x02, 0x08, KEY_LEFTBRACE)
856 MATRIX_KEY(0x02, 0x09, KEY_F8)
857
858 MATRIX_KEY(0x03, 0x01, KEY_GRAVE)
859 MATRIX_KEY(0x03, 0x02, KEY_F2)
860 MATRIX_KEY(0x03, 0x03, KEY_5)
861 MATRIX_KEY(0x03, 0x04, KEY_F5)
862 MATRIX_KEY(0x03, 0x06, KEY_6)
863 MATRIX_KEY(0x03, 0x08, KEY_MINUS)
864 MATRIX_KEY(0x03, 0x0b, KEY_BACKSLASH)
865
866 MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL)
867 MATRIX_KEY(0x04, 0x01, KEY_A)
868 MATRIX_KEY(0x04, 0x02, KEY_D)
869 MATRIX_KEY(0x04, 0x03, KEY_F)
870 MATRIX_KEY(0x04, 0x04, KEY_S)
871 MATRIX_KEY(0x04, 0x05, KEY_K)
872 MATRIX_KEY(0x04, 0x06, KEY_J)
873 MATRIX_KEY(0x04, 0x08, KEY_SEMICOLON)
874 MATRIX_KEY(0x04, 0x09, KEY_L)
875 MATRIX_KEY(0x04, 0x0a, KEY_BACKSLASH)
876 MATRIX_KEY(0x04, 0x0b, KEY_ENTER)
877
878 MATRIX_KEY(0x05, 0x01, KEY_Z)
879 MATRIX_KEY(0x05, 0x02, KEY_C)
880 MATRIX_KEY(0x05, 0x03, KEY_V)
881 MATRIX_KEY(0x05, 0x04, KEY_X)
882 MATRIX_KEY(0x05, 0x05, KEY_COMMA)
883 MATRIX_KEY(0x05, 0x06, KEY_M)
884 MATRIX_KEY(0x05, 0x07, KEY_LEFTSHIFT)
885 MATRIX_KEY(0x05, 0x08, KEY_SLASH)
886 MATRIX_KEY(0x05, 0x09, KEY_DOT)
887 MATRIX_KEY(0x05, 0x0b, KEY_SPACE)
888
889 MATRIX_KEY(0x06, 0x01, KEY_1)
890 MATRIX_KEY(0x06, 0x02, KEY_3)
891 MATRIX_KEY(0x06, 0x03, KEY_4)
892 MATRIX_KEY(0x06, 0x04, KEY_2)
893 MATRIX_KEY(0x06, 0x05, KEY_8)
894 MATRIX_KEY(0x06, 0x06, KEY_7)
895 MATRIX_KEY(0x06, 0x08, KEY_0)
896 MATRIX_KEY(0x06, 0x09, KEY_9)
897 MATRIX_KEY(0x06, 0x0a, KEY_LEFTALT)
898 MATRIX_KEY(0x06, 0x0b, KEY_DOWN)
899 MATRIX_KEY(0x06, 0x0c, KEY_RIGHT)
900
901 MATRIX_KEY(0x07, 0x01, KEY_Q)
902 MATRIX_KEY(0x07, 0x02, KEY_E)
903 MATRIX_KEY(0x07, 0x03, KEY_R)
904 MATRIX_KEY(0x07, 0x04, KEY_W)
905 MATRIX_KEY(0x07, 0x05, KEY_I)
906 MATRIX_KEY(0x07, 0x06, KEY_U)
907 MATRIX_KEY(0x07, 0x07, KEY_RIGHTSHIFT)
908 MATRIX_KEY(0x07, 0x08, KEY_P)
909 MATRIX_KEY(0x07, 0x09, KEY_O)
910 MATRIX_KEY(0x07, 0x0b, KEY_UP)
911 MATRIX_KEY(0x07, 0x0c, KEY_LEFT)
912 >;
913 };
914 };
915 };
916
11e5b4f9
SW		 917 spi@7000da00 {
918 status = "okay";
919 spi-max-frequency = <25000000>;
920 spi-flash@0 {
921 compatible = "winbond,w25q32dw";
922 reg = <0>;
923 spi-max-frequency = <20000000>;
924 };
925 };
926
a1425d42
JL		 927 pmc@7000e400 {
928 nvidia,invert-interrupt;
6ec1d127
JL		 929 nvidia,suspend-mode = <1>;
930 nvidia,cpu-pwr-good-time = <500>;
931 nvidia,cpu-pwr-off-time = <300>;
932 nvidia,core-pwr-good-time = <641 3845>;
933 nvidia,core-pwr-off-time = <61036>;
934 nvidia,core-power-req-active-high;
935 nvidia,sys-clock-req-active-high;
a1425d42 936 };
3b86baf2 937
784c7444
SW		 938 sdhci@700b0400 {
939 cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
940 power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
941 status = "okay";
942 bus-width = <4>;
4989b439 943 vmmc-supply = <&vddio_sdmmc3>;
784c7444
SW		 944 };
945
946 sdhci@700b0600 {
947 status = "okay";
948 bus-width = <8>;
949 };
950
b0e1caee
SW		 951 ahub@70300000 {
952 i2s@70301100 {
953 status = "okay";
954 };
955 };
956
431b7be0
TR		 957 usb@7d000000 {
958 status = "okay";
959 };
960
961 usb-phy@7d000000 {
962 status = "okay";
963 vbus-supply = <&vdd_usb1_vbus>;
964 };
965
966 usb@7d004000 {
967 status = "okay";
968 };
969
970 usb-phy@7d004000 {
971 status = "okay";
972 vbus-supply = <&vdd_run_cam>;
973 };
974
975 usb@7d008000 {
976 status = "okay";
977 };
978
979 usb-phy@7d008000 {
980 status = "okay";
981 vbus-supply = <&vdd_usb3_vbus>;
982 };
983
40e231c7
TR		 984 backlight: backlight {
985 compatible = "pwm-backlight";
986
987 enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
988 power-supply = <&vdd_led>;
989 pwms = <&pwm 1 1000000>;
990
991 brightness-levels = <0 4 8 16 32 64 128 255>;
992 default-brightness-level = <6>;
993 };
994
3b86baf2
JL		 995 clocks {
996 compatible = "simple-bus";
997 #address-cells = <1>;
998 #size-cells = <0>;
999
1000 clk32k_in: clock@0 {
1001 compatible = "fixed-clock";
1002 reg=<0>;
1003 #clock-cells = <0>;
1004 clock-frequency = <32768>;
1005 };
1006 };
b0e1caee 1007
3f748d44
TR		 1008 gpio-keys {
1009 compatible = "gpio-keys";
1010
1011 power {
1012 label = "Power";
1013 gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
1014 linux,code = <KEY_POWER>;
1015 debounce-interval = <10>;
1016 gpio-key,wakeup;
1017 };
1018 };
1019
40e231c7
TR		 1020 panel: panel {
1021 compatible = "lg,lp129qe", "simple-panel";
1022
1023 backlight = <&backlight>;
1024 ddc-i2c-bus = <&dpaux>;
1025 };
1026
fcacaba7
LD		 1027 regulators {
1028 compatible = "simple-bus";
1029 #address-cells = <1>;
1030 #size-cells = <0>;
1031
af144b8d 1032 vdd_mux: regulator@0 {
fcacaba7
LD		 1033 compatible = "regulator-fixed";
1034 reg = <0>;
af144b8d
TR		 1035 regulator-name = "+VDD_MUX";
1036 regulator-min-microvolt = <12000000>;
1037 regulator-max-microvolt = <12000000>;
fcacaba7 1038 regulator-always-on;
af144b8d 1039 regulator-boot-on;
fcacaba7
LD		 1040 };
1041
af144b8d 1042 vdd_5v0_sys: regulator@1 {
fcacaba7
LD		 1043 compatible = "regulator-fixed";
1044 reg = <1>;
af144b8d
TR		 1045 regulator-name = "+5V_SYS";
1046 regulator-min-microvolt = <5000000>;
1047 regulator-max-microvolt = <5000000>;
fcacaba7
LD		 1048 regulator-always-on;
1049 regulator-boot-on;
af144b8d 1050 vin-supply = <&vdd_mux>;
fcacaba7
LD		 1051 };
1052
af144b8d 1053 vdd_3v3_sys: regulator@2 {
fcacaba7
LD		 1054 compatible = "regulator-fixed";
1055 reg = <2>;
af144b8d 1056 regulator-name = "+3.3V_SYS";
fcacaba7
LD		 1057 regulator-min-microvolt = <3300000>;
1058 regulator-max-microvolt = <3300000>;
af144b8d
TR		 1059 regulator-always-on;
1060 regulator-boot-on;
1061 vin-supply = <&vdd_mux>;
fcacaba7
LD		 1062 };
1063
af144b8d 1064 vdd_3v3_run: regulator@3 {
fcacaba7
LD		 1065 compatible = "regulator-fixed";
1066 reg = <3>;
af144b8d
TR		 1067 regulator-name = "+3.3V_RUN";
1068 regulator-min-microvolt = <3300000>;
1069 regulator-max-microvolt = <3300000>;
1070 gpio = <&as3722 1 GPIO_ACTIVE_HIGH>;
fcacaba7 1071 enable-active-high;
af144b8d 1072 vin-supply = <&vdd_3v3_sys>;
fcacaba7
LD		 1073 };
1074
af144b8d 1075 vdd_3v3_hdmi: regulator@4 {
fcacaba7
LD		 1076 compatible = "regulator-fixed";
1077 reg = <4>;
af144b8d 1078 regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
fcacaba7
LD		 1079 regulator-min-microvolt = <3300000>;
1080 regulator-max-microvolt = <3300000>;
af144b8d 1081 vin-supply = <&vdd_3v3_run>;
fcacaba7
LD		 1082 };
1083
af144b8d 1084 vdd_led: regulator@5 {
fcacaba7
LD		 1085 compatible = "regulator-fixed";
1086 reg = <5>;
af144b8d
TR		 1087 regulator-name = "+VDD_LED";
1088 gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
fcacaba7 1089 enable-active-high;
af144b8d 1090 vin-supply = <&vdd_mux>;
fcacaba7
LD		 1091 };
1092
af144b8d 1093 vdd_5v0_ts: regulator@6 {
fcacaba7
LD		 1094 compatible = "regulator-fixed";
1095 reg = <6>;
af144b8d 1096 regulator-name = "+5V_VDD_TS_SW";
fcacaba7
LD		 1097 regulator-min-microvolt = <5000000>;
1098 regulator-max-microvolt = <5000000>;
1099 regulator-boot-on;
af144b8d 1100 gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
fcacaba7 1101 enable-active-high;
af144b8d 1102 vin-supply = <&vdd_5v0_sys>;
fcacaba7
LD		 1103 };
1104
af144b8d 1105 vdd_usb1_vbus: regulator@7 {
fcacaba7
LD		 1106 compatible = "regulator-fixed";
1107 reg = <7>;
af144b8d 1108 regulator-name = "+5V_USB_HS";
fcacaba7
LD		 1109 regulator-min-microvolt = <5000000>;
1110 regulator-max-microvolt = <5000000>;
af144b8d 1111 gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
fcacaba7 1112 enable-active-high;
fcacaba7 1113 gpio-open-drain;
af144b8d 1114 vin-supply = <&vdd_5v0_sys>;
fcacaba7
LD		 1115 };
1116
af144b8d 1117 vdd_usb3_vbus: regulator@8 {
fcacaba7
LD		 1118 compatible = "regulator-fixed";
1119 reg = <8>;
af144b8d
TR		 1120 regulator-name = "+5V_USB_SS";
1121 regulator-min-microvolt = <5000000>;
1122 regulator-max-microvolt = <5000000>;
1123 gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
1124 enable-active-high;
1125 gpio-open-drain;
1126 vin-supply = <&vdd_5v0_sys>;
1127 };
1128
1129 vdd_3v3_panel: regulator@9 {
1130 compatible = "regulator-fixed";
1131 reg = <9>;
1132 regulator-name = "+3.3V_PANEL";
fcacaba7
LD		 1133 regulator-min-microvolt = <3300000>;
1134 regulator-max-microvolt = <3300000>;
fcacaba7 1135 gpio = <&as3722 4 GPIO_ACTIVE_HIGH>;
af144b8d
TR		 1136 enable-active-high;
1137 vin-supply = <&vdd_3v3_run>;
1138 };
1139
1140 vdd_3v3_lp0: regulator@10 {
1141 compatible = "regulator-fixed";
1142 reg = <10>;
1143 regulator-name = "+3.3V_LP0";
1144 regulator-min-microvolt = <3300000>;
1145 regulator-max-microvolt = <3300000>;
1146 /*
1147 * TODO: find a way to wire this up with the USB EHCI
1148 * controllers so that it can be enabled on demand.
1149 */
1150 regulator-always-on;
1151 gpio = <&as3722 2 GPIO_ACTIVE_HIGH>;
1152 enable-active-high;
1153 vin-supply = <&vdd_3v3_sys>;
fcacaba7
LD		 1154 };
1155 };
1156
b0e1caee
SW		 1157 sound {
1158 compatible = "nvidia,tegra-audio-max98090-venice2",
1159 "nvidia,tegra-audio-max98090";
1160 nvidia,model = "NVIDIA Tegra Venice2";
1161
1162 nvidia,audio-routing =
1163 "Headphones", "HPR",
1164 "Headphones", "HPL",
1165 "Speakers", "SPKR",
1166 "Speakers", "SPKL",
1167 "Mic Jack", "MICBIAS",
1168 "IN34", "Mic Jack";
1169
1170 nvidia,i2s-controller = <&tegra_i2s1>;
1171 nvidia,audio-codec = <&acodec>;
1172
1173 clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
1174 <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
1175 <&tegra_car TEGRA124_CLK_EXTERN1>;
1176 clock-names = "pll_a", "pll_a_out0", "mclk";
1177 };
a1425d42 1178};
Linux kernel - Deliverables
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