Commit | Line | Data |
---|---|---|
a1425d42 JL |
1 | /dts-v1/; |
2 | ||
3 | #include "tegra124.dtsi" | |
4 | ||
5 | / { | |
6 | model = "NVIDIA Tegra124 Venice2"; | |
7 | compatible = "nvidia,venice2", "nvidia,tegra124"; | |
8 | ||
b1afa782 SW |
9 | aliases { |
10 | rtc0 = "/i2c@7000d000/as3722@40"; | |
11 | rtc1 = "/rtc@7000e000"; | |
12 | }; | |
13 | ||
a1425d42 JL |
14 | memory { |
15 | reg = <0x80000000 0x80000000>; | |
16 | }; | |
17 | ||
4b20bcbe LD |
18 | pinmux: pinmux@70000868 { |
19 | pinctrl-names = "default"; | |
20 | pinctrl-0 = <&pinmux_default>; | |
21 | ||
22 | pinmux_default: common { | |
23 | dap_mclk1_pw4 { | |
24 | nvidia,pins = "dap_mclk1_pw4"; | |
25 | nvidia,function = "extperiph1"; | |
26 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
27 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
28 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
29 | }; | |
30 | dap1_din_pn1 { | |
365c483f LD |
31 | nvidia,pins = "dap1_din_pn1"; |
32 | nvidia,function = "i2s0"; | |
33 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
34 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
35 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
36 | }; | |
37 | dap1_dout_pn2 { | |
38 | nvidia,pins = "dap1_dout_pn2", | |
4b20bcbe LD |
39 | "dap1_fs_pn0", |
40 | "dap1_sclk_pn3"; | |
41 | nvidia,function = "i2s0"; | |
365c483f | 42 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
4b20bcbe LD |
43 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
44 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
45 | }; | |
46 | dap2_din_pa4 { | |
365c483f | 47 | nvidia,pins = "dap2_din_pa4"; |
4b20bcbe LD |
48 | nvidia,function = "i2s1"; |
49 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
50 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
4ffb9385 | 51 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
4b20bcbe | 52 | }; |
365c483f LD |
53 | dap2_dout_pa5 { |
54 | nvidia,pins = "dap2_dout_pa5", | |
55 | "dap2_fs_pa2", | |
56 | "dap2_sclk_pa3"; | |
57 | nvidia,function = "i2s1"; | |
4b20bcbe LD |
58 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
59 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
365c483f | 60 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
4b20bcbe | 61 | }; |
365c483f LD |
62 | dvfs_pwm_px0 { |
63 | nvidia,pins = "dvfs_pwm_px0", | |
64 | "dvfs_clk_px2"; | |
4b20bcbe LD |
65 | nvidia,function = "cldvfs"; |
66 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
67 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
68 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
69 | }; | |
70 | ulpi_clk_py0 { | |
71 | nvidia,pins = "ulpi_clk_py0", | |
4b20bcbe LD |
72 | "ulpi_nxt_py2", |
73 | "ulpi_stp_py3"; | |
74 | nvidia,function = "spi1"; | |
365c483f LD |
75 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
76 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
77 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
78 | }; | |
79 | ulpi_dir_py1 { | |
80 | nvidia,pins = "ulpi_dir_py1"; | |
81 | nvidia,function = "spi1"; | |
4b20bcbe | 82 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
365c483f | 83 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
4b20bcbe LD |
84 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
85 | }; | |
86 | cam_i2c_scl_pbb1 { | |
87 | nvidia,pins = "cam_i2c_scl_pbb1", | |
88 | "cam_i2c_sda_pbb2"; | |
89 | nvidia,function = "i2c3"; | |
90 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
91 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
92 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
93 | nvidia,lock = <TEGRA_PIN_DISABLE>; | |
94 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
95 | }; | |
96 | gen2_i2c_scl_pt5 { | |
97 | nvidia,pins = "gen2_i2c_scl_pt5", | |
98 | "gen2_i2c_sda_pt6"; | |
99 | nvidia,function = "i2c2"; | |
100 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
101 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
102 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
103 | nvidia,lock = <TEGRA_PIN_DISABLE>; | |
104 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
105 | }; | |
106 | pg4 { | |
107 | nvidia,pins = "pg4", | |
108 | "pg5", | |
109 | "pg6", | |
4b20bcbe LD |
110 | "pi3"; |
111 | nvidia,function = "spi4"; | |
112 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
113 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
114 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
115 | }; | |
365c483f LD |
116 | pg7 { |
117 | nvidia,pins = "pg7"; | |
118 | nvidia,function = "spi4"; | |
4b20bcbe | 119 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
365c483f LD |
120 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
121 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
4b20bcbe LD |
122 | }; |
123 | ph1 { | |
124 | nvidia,pins = "ph1"; | |
125 | nvidia,function = "pwm1"; | |
126 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
127 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
128 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
129 | }; | |
365c483f LD |
130 | pk0 { |
131 | nvidia,pins = "pk0", | |
132 | "kb_row15_ps7", | |
133 | "clk_32k_out_pa0"; | |
134 | nvidia,function = "soc"; | |
135 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
f5cb19b4 | 136 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
365c483f | 137 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
f5cb19b4 | 138 | }; |
4b20bcbe LD |
139 | sdmmc1_clk_pz0 { |
140 | nvidia,pins = "sdmmc1_clk_pz0", | |
141 | "sdmmc1_cmd_pz1", | |
142 | "sdmmc1_dat0_py7", | |
143 | "sdmmc1_dat1_py6", | |
144 | "sdmmc1_dat2_py5", | |
145 | "sdmmc1_dat3_py4"; | |
146 | nvidia,function = "sdmmc1"; | |
147 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
148 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
149 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
150 | }; | |
365c483f LD |
151 | sdmmc1_cmd_pz1 { |
152 | nvidia,pins = "sdmmc1_cmd_pz1", | |
153 | "sdmmc1_dat0_py7", | |
154 | "sdmmc1_dat1_py6", | |
155 | "sdmmc1_dat2_py5", | |
156 | "sdmmc1_dat3_py4"; | |
157 | nvidia,function = "sdmmc1"; | |
158 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
159 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
160 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
161 | }; | |
4b20bcbe LD |
162 | sdmmc3_clk_pa6 { |
163 | nvidia,pins = "sdmmc3_clk_pa6"; | |
164 | nvidia,function = "sdmmc3"; | |
165 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
166 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
167 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
168 | }; | |
169 | sdmmc3_cmd_pa7 { | |
170 | nvidia,pins = "sdmmc3_cmd_pa7", | |
171 | "sdmmc3_dat0_pb7", | |
172 | "sdmmc3_dat1_pb6", | |
173 | "sdmmc3_dat2_pb5", | |
174 | "sdmmc3_dat3_pb4", | |
175 | "sdmmc3_clk_lb_out_pee4", | |
176 | "sdmmc3_clk_lb_in_pee5"; | |
177 | nvidia,function = "sdmmc3"; | |
178 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
179 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
180 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
181 | }; | |
182 | sdmmc4_clk_pcc4 { | |
183 | nvidia,pins = "sdmmc4_clk_pcc4"; | |
184 | nvidia,function = "sdmmc4"; | |
185 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
186 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
187 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
188 | }; | |
189 | sdmmc4_cmd_pt7 { | |
190 | nvidia,pins = "sdmmc4_cmd_pt7", | |
191 | "sdmmc4_dat0_paa0", | |
192 | "sdmmc4_dat1_paa1", | |
193 | "sdmmc4_dat2_paa2", | |
194 | "sdmmc4_dat3_paa3", | |
195 | "sdmmc4_dat4_paa4", | |
196 | "sdmmc4_dat5_paa5", | |
197 | "sdmmc4_dat6_paa6", | |
198 | "sdmmc4_dat7_paa7"; | |
199 | nvidia,function = "sdmmc4"; | |
200 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
201 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
202 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
203 | }; | |
204 | pwr_i2c_scl_pz6 { | |
205 | nvidia,pins = "pwr_i2c_scl_pz6", | |
206 | "pwr_i2c_sda_pz7"; | |
207 | nvidia,function = "i2cpwr"; | |
208 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
209 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
210 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
365c483f | 211 | nvidia,lock = <TEGRA_PIN_DISABLE>; |
4b20bcbe LD |
212 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
213 | }; | |
214 | jtag_rtck { | |
215 | nvidia,pins = "jtag_rtck"; | |
216 | nvidia,function = "rtck"; | |
217 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
218 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
219 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
220 | }; | |
221 | clk_32k_in { | |
222 | nvidia,pins = "clk_32k_in"; | |
223 | nvidia,function = "clk"; | |
224 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
225 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
226 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
227 | }; | |
228 | core_pwr_req { | |
229 | nvidia,pins = "core_pwr_req"; | |
230 | nvidia,function = "pwron"; | |
231 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
232 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
233 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
234 | }; | |
235 | cpu_pwr_req { | |
236 | nvidia,pins = "cpu_pwr_req"; | |
237 | nvidia,function = "cpu"; | |
238 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
239 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
240 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
241 | }; | |
242 | pwr_int_n { | |
243 | nvidia,pins = "pwr_int_n"; | |
244 | nvidia,function = "pmi"; | |
245 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
246 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
247 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
248 | }; | |
249 | reset_out_n { | |
250 | nvidia,pins = "reset_out_n"; | |
251 | nvidia,function = "reset_out_n"; | |
252 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
253 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
254 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
255 | }; | |
256 | clk3_out_pee0 { | |
257 | nvidia,pins = "clk3_out_pee0"; | |
258 | nvidia,function = "extperiph3"; | |
259 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
260 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
261 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
262 | }; | |
263 | dap4_din_pp5 { | |
365c483f LD |
264 | nvidia,pins = "dap4_din_pp5"; |
265 | nvidia,function = "i2s3"; | |
266 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
267 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
268 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
269 | }; | |
270 | dap4_dout_pp6 { | |
271 | nvidia,pins = "dap4_dout_pp6", | |
4b20bcbe LD |
272 | "dap4_fs_pp4", |
273 | "dap4_sclk_pp7"; | |
274 | nvidia,function = "i2s3"; | |
365c483f | 275 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
4b20bcbe LD |
276 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
277 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
278 | }; | |
279 | gen1_i2c_sda_pc5 { | |
280 | nvidia,pins = "gen1_i2c_sda_pc5", | |
281 | "gen1_i2c_scl_pc4"; | |
282 | nvidia,function = "i2c1"; | |
283 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
284 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
285 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
286 | nvidia,lock = <TEGRA_PIN_DISABLE>; | |
365c483f | 287 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
4b20bcbe | 288 | }; |
365c483f LD |
289 | uart2_cts_n_pj5 { |
290 | nvidia,pins = "uart2_cts_n_pj5"; | |
291 | nvidia,function = "uartb"; | |
4b20bcbe | 292 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
4ffb9385 | 293 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
4b20bcbe LD |
294 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
295 | }; | |
365c483f LD |
296 | uart2_rts_n_pj6 { |
297 | nvidia,pins = "uart2_rts_n_pj6"; | |
4b20bcbe | 298 | nvidia,function = "uartb"; |
365c483f | 299 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
4b20bcbe LD |
300 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
301 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
302 | }; | |
303 | uart2_rxd_pc3 { | |
365c483f | 304 | nvidia,pins = "uart2_rxd_pc3"; |
4b20bcbe LD |
305 | nvidia,function = "irda"; |
306 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
307 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
308 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
309 | }; | |
365c483f LD |
310 | uart2_txd_pc2 { |
311 | nvidia,pins = "uart2_txd_pc2"; | |
312 | nvidia,function = "irda"; | |
313 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
314 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
315 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
316 | }; | |
4b20bcbe LD |
317 | uart3_cts_n_pa1 { |
318 | nvidia,pins = "uart3_cts_n_pa1", | |
365c483f | 319 | "uart3_rxd_pw7"; |
4b20bcbe LD |
320 | nvidia,function = "uartc"; |
321 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
322 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
323 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
324 | }; | |
365c483f LD |
325 | uart3_rts_n_pc0 { |
326 | nvidia,pins = "uart3_rts_n_pc0", | |
327 | "uart3_txd_pw6"; | |
328 | nvidia,function = "uartc"; | |
329 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
330 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
331 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
332 | }; | |
4b20bcbe LD |
333 | hdmi_cec_pee3 { |
334 | nvidia,pins = "hdmi_cec_pee3"; | |
335 | nvidia,function = "cec"; | |
336 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
337 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
338 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
365c483f LD |
339 | nvidia,lock = <TEGRA_PIN_DISABLE>; |
340 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
341 | }; | |
342 | hdmi_int_pn7 { | |
343 | nvidia,pins = "hdmi_int_pn7"; | |
344 | nvidia,function = "rsvd1"; | |
345 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
346 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
347 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
4b20bcbe LD |
348 | }; |
349 | ddc_scl_pv4 { | |
350 | nvidia,pins = "ddc_scl_pv4", | |
351 | "ddc_sda_pv5"; | |
352 | nvidia,function = "i2c4"; | |
353 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
354 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
355 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
365c483f LD |
356 | nvidia,lock = <TEGRA_PIN_DISABLE>; |
357 | nvidia,rcv-sel = <TEGRA_PIN_ENABLE>; | |
358 | }; | |
359 | pj7 { | |
360 | nvidia,pins = "pj7", | |
361 | "pk7"; | |
362 | nvidia,function = "uartd"; | |
363 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
364 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
365 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
366 | }; | |
367 | pb0 { | |
368 | nvidia,pins = "pb0", | |
369 | "pb1"; | |
370 | nvidia,function = "uartd"; | |
371 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
372 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
373 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
374 | }; | |
375 | ph0 { | |
376 | nvidia,pins = "ph0"; | |
377 | nvidia,function = "pwm0"; | |
378 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
379 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
380 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
381 | }; | |
382 | kb_row10_ps2 { | |
383 | nvidia,pins = "kb_row10_ps2"; | |
384 | nvidia,function = "uarta"; | |
385 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
386 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
387 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
388 | }; | |
389 | kb_row9_ps1 { | |
390 | nvidia,pins = "kb_row9_ps1"; | |
391 | nvidia,function = "uarta"; | |
392 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
393 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
394 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
395 | }; | |
396 | kb_row6_pr6 { | |
397 | nvidia,pins = "kb_row6_pr6"; | |
398 | nvidia,function = "displaya_alt"; | |
399 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
400 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
401 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
4b20bcbe LD |
402 | }; |
403 | usb_vbus_en0_pn4 { | |
404 | nvidia,pins = "usb_vbus_en0_pn4"; | |
405 | nvidia,function = "usb"; | |
406 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
407 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
408 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
409 | nvidia,lock = <TEGRA_PIN_DISABLE>; | |
365c483f | 410 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
4b20bcbe LD |
411 | }; |
412 | usb_vbus_en1_pn5 { | |
413 | nvidia,pins = "usb_vbus_en1_pn5"; | |
414 | nvidia,function = "usb"; | |
415 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
416 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
417 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
418 | nvidia,lock = <TEGRA_PIN_DISABLE>; | |
365c483f | 419 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
4b20bcbe LD |
420 | }; |
421 | drive_sdio1 { | |
422 | nvidia,pins = "drive_sdio1"; | |
423 | nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; | |
424 | nvidia,schmitt = <TEGRA_PIN_DISABLE>; | |
425 | nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; | |
426 | nvidia,pull-down-strength = <32>; | |
427 | nvidia,pull-up-strength = <42>; | |
428 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; | |
429 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; | |
430 | }; | |
431 | drive_sdio3 { | |
432 | nvidia,pins = "drive_sdio3"; | |
433 | nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; | |
434 | nvidia,schmitt = <TEGRA_PIN_DISABLE>; | |
435 | nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; | |
436 | nvidia,pull-down-strength = <20>; | |
437 | nvidia,pull-up-strength = <36>; | |
438 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; | |
439 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; | |
440 | }; | |
441 | drive_gma { | |
442 | nvidia,pins = "drive_gma"; | |
443 | nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; | |
444 | nvidia,schmitt = <TEGRA_PIN_DISABLE>; | |
445 | nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; | |
446 | nvidia,pull-down-strength = <1>; | |
447 | nvidia,pull-up-strength = <2>; | |
448 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; | |
449 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; | |
450 | nvidia,drive-type = <1>; | |
451 | }; | |
365c483f LD |
452 | als_irq_l { |
453 | nvidia,pins = "gpio_x3_aud_px3"; | |
454 | nvidia,function = "gmi"; | |
455 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
456 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
457 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
458 | }; | |
459 | codec_irq_l { | |
460 | nvidia,pins = "ph4"; | |
461 | nvidia,function = "gmi"; | |
462 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
463 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
464 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
465 | }; | |
466 | lcd_bl_en { | |
467 | nvidia,pins = "ph2"; | |
468 | nvidia,function = "gmi"; | |
469 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
470 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
471 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
472 | }; | |
473 | touch_irq_l { | |
474 | nvidia,pins = "gpio_w3_aud_pw3"; | |
475 | nvidia,function = "spi6"; | |
476 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
477 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
478 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
479 | }; | |
480 | tpm_davint_l { | |
481 | nvidia,pins = "ph6"; | |
482 | nvidia,function = "gmi"; | |
483 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
484 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
485 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
486 | }; | |
487 | ts_irq_l { | |
488 | nvidia,pins = "pk2"; | |
489 | nvidia,function = "gmi"; | |
490 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
491 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
492 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
493 | }; | |
494 | ts_reset_l { | |
495 | nvidia,pins = "pk4"; | |
496 | nvidia,function = "gmi"; | |
497 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
498 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
499 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
500 | }; | |
501 | ts_shdn_l { | |
502 | nvidia,pins = "pk1"; | |
503 | nvidia,function = "gmi"; | |
504 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
505 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
506 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
507 | }; | |
508 | ph7 { | |
509 | nvidia,pins = "ph7"; | |
510 | nvidia,function = "gmi"; | |
511 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
512 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
513 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
514 | }; | |
515 | kb_col0_ap { | |
516 | nvidia,pins = "kb_col0_pq0"; | |
517 | nvidia,function = "rsvd4"; | |
518 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
519 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
520 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
521 | }; | |
522 | lid_open { | |
523 | nvidia,pins = "kb_row4_pr4"; | |
524 | nvidia,function = "rsvd3"; | |
525 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
526 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
527 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
528 | }; | |
529 | en_vdd_sd { | |
530 | nvidia,pins = "kb_row0_pr0"; | |
531 | nvidia,function = "rsvd4"; | |
532 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
533 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
534 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
535 | }; | |
536 | ac_ok { | |
537 | nvidia,pins = "pj0"; | |
538 | nvidia,function = "gmi"; | |
539 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
540 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
541 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
542 | }; | |
543 | sensor_irq_l { | |
544 | nvidia,pins = "pi6"; | |
545 | nvidia,function = "gmi"; | |
546 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
547 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
548 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
549 | }; | |
550 | wifi_en { | |
551 | nvidia,pins = "gpio_x7_aud_px7"; | |
552 | nvidia,function = "rsvd4"; | |
553 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
554 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
555 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
556 | }; | |
557 | wifi_rst_l { | |
558 | nvidia,pins = "clk2_req_pcc5"; | |
559 | nvidia,function = "dap"; | |
560 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
561 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
562 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
563 | }; | |
564 | hp_det_l { | |
565 | nvidia,pins = "ulpi_data1_po2"; | |
566 | nvidia,function = "spi3"; | |
567 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
568 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
569 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
570 | }; | |
4b20bcbe LD |
571 | }; |
572 | }; | |
573 | ||
a1425d42 JL |
574 | serial@70006000 { |
575 | status = "okay"; | |
576 | }; | |
577 | ||
e013485d TR |
578 | pwm: pwm@7000a000 { |
579 | status = "okay"; | |
580 | }; | |
581 | ||
9d5b2505 SW |
582 | i2c@7000c000 { |
583 | status = "okay"; | |
584 | clock-frequency = <100000>; | |
b0e1caee SW |
585 | |
586 | acodec: audio-codec@10 { | |
587 | compatible = "maxim,max98090"; | |
588 | reg = <0x10>; | |
589 | interrupt-parent = <&gpio>; | |
590 | interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>; | |
591 | }; | |
9d5b2505 SW |
592 | }; |
593 | ||
594 | i2c@7000c400 { | |
595 | status = "okay"; | |
596 | clock-frequency = <100000>; | |
597 | }; | |
598 | ||
599 | i2c@7000c500 { | |
600 | status = "okay"; | |
601 | clock-frequency = <100000>; | |
602 | }; | |
603 | ||
604 | i2c@7000c700 { | |
605 | status = "okay"; | |
606 | clock-frequency = <100000>; | |
607 | }; | |
608 | ||
609 | i2c@7000d000 { | |
610 | status = "okay"; | |
fcacaba7 LD |
611 | clock-frequency = <400000>; |
612 | ||
613 | as3722: as3722@40 { | |
614 | compatible = "ams,as3722"; | |
615 | reg = <0x40>; | |
616 | interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; | |
617 | ||
618 | #interrupt-cells = <2>; | |
619 | interrupt-controller; | |
620 | ||
621 | gpio-controller; | |
622 | #gpio-cells = <2>; | |
623 | ||
624 | pinctrl-names = "default"; | |
625 | pinctrl-0 = <&as3722_default>; | |
626 | ||
627 | as3722_default: pinmux { | |
628 | gpio0 { | |
629 | pins = "gpio0"; | |
630 | function = "gpio"; | |
631 | bias-pull-down; | |
632 | }; | |
633 | ||
634 | gpio1_2_4_7 { | |
635 | pins = "gpio1", "gpio2", "gpio4", "gpio7"; | |
636 | function = "gpio"; | |
637 | bias-pull-up; | |
638 | }; | |
639 | ||
640 | gpio3_6 { | |
641 | pins = "gpio3", "gpio6"; | |
642 | bias-high-impedance; | |
643 | }; | |
644 | ||
645 | gpio5 { | |
646 | pins = "gpio5"; | |
647 | function = "clk32k-out"; | |
648 | }; | |
649 | }; | |
650 | ||
651 | regulators { | |
652 | vsup-sd2-supply = <&vdd_ac_bat_reg>; | |
653 | vsup-sd3-supply = <&vdd_ac_bat_reg>; | |
654 | vsup-sd4-supply = <&vdd_ac_bat_reg>; | |
655 | vsup-sd5-supply = <&vdd_ac_bat_reg>; | |
656 | vin-ldo0-supply = <&as3722_sd2>; | |
657 | vin-ldo1-6-supply = <&vdd_ac_bat_reg>; | |
658 | vin-ldo2-5-7-supply = <&as3722_sd5>; | |
659 | vin-ldo3-4-supply = <&vdd_ac_bat_reg>; | |
660 | vin-ldo9-10-supply = <&vdd_ac_bat_reg>; | |
661 | vin-ldo11-supply = <&vdd_ac_bat_reg>; | |
662 | ||
663 | sd0 { | |
664 | regulator-name = "vdd-cpu"; | |
665 | regulator-min-microvolt = <700000>; | |
666 | regulator-max-microvolt = <1400000>; | |
667 | regulator-min-microamp = <3500000>; | |
668 | regulator-max-microamp = <3500000>; | |
669 | regulator-always-on; | |
670 | regulator-boot-on; | |
671 | ams,external-control = <2>; | |
672 | }; | |
673 | ||
674 | sd1 { | |
675 | regulator-name = "vdd-core"; | |
676 | regulator-min-microvolt = <700000>; | |
677 | regulator-max-microvolt = <1350000>; | |
678 | regulator-min-microamp = <2500000>; | |
679 | regulator-max-microamp = <2500000>; | |
680 | regulator-always-on; | |
681 | regulator-boot-on; | |
682 | ams,external-control = <1>; | |
683 | }; | |
684 | ||
685 | as3722_sd2: sd2 { | |
686 | regulator-name = "vddio-ddr"; | |
687 | regulator-min-microvolt = <1350000>; | |
688 | regulator-max-microvolt = <1350000>; | |
689 | regulator-always-on; | |
690 | regulator-boot-on; | |
691 | }; | |
692 | ||
693 | sd3 { | |
694 | regulator-name = "vddio-ddr-2phase"; | |
695 | regulator-min-microvolt = <1350000>; | |
696 | regulator-max-microvolt = <1350000>; | |
697 | regulator-always-on; | |
698 | regulator-boot-on; | |
699 | }; | |
700 | ||
701 | sd4 { | |
702 | regulator-name = "avdd-pex-sata"; | |
703 | regulator-min-microvolt = <1050000>; | |
704 | regulator-max-microvolt = <1050000>; | |
705 | regulator-boot-on; | |
706 | regulator-always-on; | |
707 | }; | |
708 | ||
709 | as3722_sd5: sd5 { | |
710 | regulator-name = "vddio-sys"; | |
711 | regulator-min-microvolt = <1800000>; | |
712 | regulator-max-microvolt = <1800000>; | |
713 | regulator-boot-on; | |
714 | regulator-always-on; | |
715 | }; | |
716 | ||
717 | sd6 { | |
718 | regulator-name = "vdd-gpu"; | |
719 | regulator-min-microvolt = <650000>; | |
720 | regulator-max-microvolt = <1200000>; | |
721 | regulator-min-microamp = <3500000>; | |
722 | regulator-max-microamp = <3500000>; | |
723 | regulator-boot-on; | |
724 | regulator-always-on; | |
725 | }; | |
726 | ||
727 | ldo0 { | |
728 | regulator-name = "avdd_pll"; | |
729 | regulator-min-microvolt = <1050000>; | |
730 | regulator-max-microvolt = <1050000>; | |
731 | regulator-boot-on; | |
732 | regulator-always-on; | |
733 | ams,external-control = <1>; | |
734 | }; | |
735 | ||
736 | ldo1 { | |
737 | regulator-name = "run-cam-1.8"; | |
738 | regulator-min-microvolt = <1800000>; | |
739 | regulator-max-microvolt = <1800000>; | |
740 | }; | |
741 | ||
742 | ldo2 { | |
743 | regulator-name = "gen-avdd,vddio-hsic"; | |
744 | regulator-min-microvolt = <1200000>; | |
745 | regulator-max-microvolt = <1200000>; | |
746 | regulator-boot-on; | |
747 | regulator-always-on; | |
748 | }; | |
749 | ||
750 | ldo3 { | |
751 | regulator-name = "vdd-rtc"; | |
752 | regulator-min-microvolt = <1000000>; | |
753 | regulator-max-microvolt = <1000000>; | |
754 | regulator-boot-on; | |
755 | regulator-always-on; | |
756 | ams,enable-tracking; | |
757 | }; | |
758 | ||
759 | ldo4 { | |
760 | regulator-name = "vdd-cam"; | |
761 | regulator-min-microvolt = <2800000>; | |
762 | regulator-max-microvolt = <2800000>; | |
763 | regulator-boot-on; | |
764 | regulator-always-on; | |
765 | }; | |
766 | ||
767 | ldo5 { | |
768 | regulator-name = "vdd-cam-front"; | |
769 | regulator-min-microvolt = <1200000>; | |
770 | regulator-max-microvolt = <1200000>; | |
771 | }; | |
772 | ||
773 | ldo6 { | |
774 | regulator-name = "vddio-sdmmc3"; | |
775 | regulator-min-microvolt = <1800000>; | |
776 | regulator-max-microvolt = <3300000>; | |
777 | regulator-boot-on; | |
778 | regulator-always-on; | |
779 | }; | |
780 | ||
781 | ldo7 { | |
782 | regulator-name = "vdd-cam-rear"; | |
783 | regulator-min-microvolt = <1050000>; | |
784 | regulator-max-microvolt = <1050000>; | |
785 | }; | |
786 | ||
787 | ldo9 { | |
788 | regulator-name = "vdd-touch"; | |
789 | regulator-min-microvolt = <2800000>; | |
790 | regulator-max-microvolt = <2800000>; | |
791 | }; | |
792 | ||
793 | ldo10 { | |
794 | regulator-name = "vdd-cam-af"; | |
795 | regulator-min-microvolt = <2800000>; | |
796 | regulator-max-microvolt = <2800000>; | |
797 | }; | |
798 | ||
799 | ldo11 { | |
800 | regulator-name = "vpp-fuse"; | |
801 | regulator-min-microvolt = <1800000>; | |
802 | regulator-max-microvolt = <1800000>; | |
803 | }; | |
804 | }; | |
805 | }; | |
9d5b2505 SW |
806 | }; |
807 | ||
a1425d42 JL |
808 | pmc@7000e400 { |
809 | nvidia,invert-interrupt; | |
6ec1d127 JL |
810 | nvidia,suspend-mode = <1>; |
811 | nvidia,cpu-pwr-good-time = <500>; | |
812 | nvidia,cpu-pwr-off-time = <300>; | |
813 | nvidia,core-pwr-good-time = <641 3845>; | |
814 | nvidia,core-pwr-off-time = <61036>; | |
815 | nvidia,core-power-req-active-high; | |
816 | nvidia,sys-clock-req-active-high; | |
a1425d42 | 817 | }; |
3b86baf2 | 818 | |
784c7444 SW |
819 | sdhci@700b0400 { |
820 | cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; | |
821 | power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; | |
822 | status = "okay"; | |
823 | bus-width = <4>; | |
824 | }; | |
825 | ||
826 | sdhci@700b0600 { | |
827 | status = "okay"; | |
828 | bus-width = <8>; | |
829 | }; | |
830 | ||
b0e1caee SW |
831 | ahub@70300000 { |
832 | i2s@70301100 { | |
833 | status = "okay"; | |
834 | }; | |
835 | }; | |
836 | ||
3b86baf2 JL |
837 | clocks { |
838 | compatible = "simple-bus"; | |
839 | #address-cells = <1>; | |
840 | #size-cells = <0>; | |
841 | ||
842 | clk32k_in: clock@0 { | |
843 | compatible = "fixed-clock"; | |
844 | reg=<0>; | |
845 | #clock-cells = <0>; | |
846 | clock-frequency = <32768>; | |
847 | }; | |
848 | }; | |
b0e1caee | 849 | |
fcacaba7 LD |
850 | regulators { |
851 | compatible = "simple-bus"; | |
852 | #address-cells = <1>; | |
853 | #size-cells = <0>; | |
854 | ||
855 | vdd_ac_bat_reg: regulator@0 { | |
856 | compatible = "regulator-fixed"; | |
857 | reg = <0>; | |
858 | regulator-name = "vdd_ac_bat"; | |
859 | regulator-min-microvolt = <5000000>; | |
860 | regulator-max-microvolt = <5000000>; | |
861 | regulator-always-on; | |
862 | }; | |
863 | ||
864 | vdd_3v3_reg: regulator@1 { | |
865 | compatible = "regulator-fixed"; | |
866 | reg = <1>; | |
867 | regulator-name = "vdd_3v3"; | |
868 | regulator-min-microvolt = <3300000>; | |
869 | regulator-max-microvolt = <3300000>; | |
870 | regulator-always-on; | |
871 | regulator-boot-on; | |
872 | enable-active-high; | |
873 | gpio = <&as3722 1 GPIO_ACTIVE_HIGH>; | |
874 | }; | |
875 | ||
876 | vdd_3v3_modem_reg: regulator@2 { | |
877 | compatible = "regulator-fixed"; | |
878 | reg = <2>; | |
879 | regulator-name = "vdd-modem-3v3"; | |
880 | regulator-min-microvolt = <3300000>; | |
881 | regulator-max-microvolt = <3300000>; | |
882 | enable-active-high; | |
883 | gpio = <&as3722 2 GPIO_ACTIVE_HIGH>; | |
884 | }; | |
885 | ||
886 | vdd_hdmi_5v0_reg: regulator@3 { | |
887 | compatible = "regulator-fixed"; | |
888 | reg = <3>; | |
889 | regulator-name = "vdd-hdmi-5v0"; | |
890 | regulator-min-microvolt = <5000000>; | |
891 | regulator-max-microvolt = <5000000>; | |
892 | enable-active-high; | |
893 | gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; | |
894 | }; | |
895 | ||
896 | vdd_bl_reg: regulator@4 { | |
897 | compatible = "regulator-fixed"; | |
898 | reg = <4>; | |
899 | regulator-name = "vdd-bl"; | |
900 | regulator-min-microvolt = <3300000>; | |
901 | regulator-max-microvolt = <3300000>; | |
902 | gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_LOW>; | |
903 | }; | |
904 | ||
905 | vdd_ts_sw_5v0: regulator@5 { | |
906 | compatible = "regulator-fixed"; | |
907 | reg = <5>; | |
908 | regulator-name = "vdd_ts_sw"; | |
909 | regulator-min-microvolt = <5000000>; | |
910 | regulator-max-microvolt = <5000000>; | |
911 | enable-active-high; | |
912 | regulator-boot-on; | |
913 | gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_LOW>; | |
914 | }; | |
915 | ||
916 | usb1_vbus_reg: regulator@6 { | |
917 | compatible = "regulator-fixed"; | |
918 | reg = <6>; | |
919 | regulator-name = "usb1_vbus"; | |
920 | regulator-min-microvolt = <5000000>; | |
921 | regulator-max-microvolt = <5000000>; | |
922 | regulator-boot-on; | |
923 | enable-active-high; | |
924 | gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; | |
925 | gpio-open-drain; | |
926 | }; | |
927 | ||
928 | usb3_vbus_reg: regulator@7 { | |
929 | compatible = "regulator-fixed"; | |
930 | reg = <7>; | |
931 | regulator-name = "usb3_vbus"; | |
932 | regulator-min-microvolt = <5000000>; | |
933 | regulator-max-microvolt = <5000000>; | |
934 | regulator-boot-on; | |
935 | enable-active-high; | |
936 | gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; | |
937 | gpio-open-drain; | |
938 | }; | |
939 | ||
940 | panel_3v3_reg: regulator@8 { | |
941 | compatible = "regulator-fixed"; | |
942 | reg = <8>; | |
943 | regulator-name = "panel_3v3"; | |
944 | regulator-min-microvolt = <3300000>; | |
945 | regulator-max-microvolt = <3300000>; | |
946 | enable-active-high; | |
947 | gpio = <&as3722 4 GPIO_ACTIVE_HIGH>; | |
948 | }; | |
949 | }; | |
950 | ||
b0e1caee SW |
951 | sound { |
952 | compatible = "nvidia,tegra-audio-max98090-venice2", | |
953 | "nvidia,tegra-audio-max98090"; | |
954 | nvidia,model = "NVIDIA Tegra Venice2"; | |
955 | ||
956 | nvidia,audio-routing = | |
957 | "Headphones", "HPR", | |
958 | "Headphones", "HPL", | |
959 | "Speakers", "SPKR", | |
960 | "Speakers", "SPKL", | |
961 | "Mic Jack", "MICBIAS", | |
962 | "IN34", "Mic Jack"; | |
963 | ||
964 | nvidia,i2s-controller = <&tegra_i2s1>; | |
965 | nvidia,audio-codec = <&acodec>; | |
966 | ||
967 | clocks = <&tegra_car TEGRA124_CLK_PLL_A>, | |
968 | <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, | |
969 | <&tegra_car TEGRA124_CLK_EXTERN1>; | |
970 | clock-names = "pll_a", "pll_a_out0", "mclk"; | |
971 | }; | |
a1425d42 | 972 | }; |