projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| a1425d42 JL |
1 | /dts-v1/; |
| 2 | ||
| 3 | #include "tegra124.dtsi" | |
| 4 | ||
| 5 | / { | |
| 6 | model = "NVIDIA Tegra124 Venice2"; | |
| 7 | compatible = "nvidia,venice2", "nvidia,tegra124"; | |
| 8 | ||
| 9 | memory { | |
| 10 | reg = <0x80000000 0x80000000>; | |
| 11 | }; | |
| 12 | ||
| 4b20bcbe LD |
13 | pinmux: pinmux@70000868 { |
| 14 | pinctrl-names = "default"; | |
| 15 | pinctrl-0 = <&pinmux_default>; | |
| 16 | ||
| 17 | pinmux_default: common { | |
| 18 | dap_mclk1_pw4 { | |
| 19 | nvidia,pins = "dap_mclk1_pw4"; | |
| 20 | nvidia,function = "extperiph1"; | |
| 21 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 22 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 23 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 24 | }; | |
| 25 | dap1_din_pn1 { | |
| 26 | nvidia,pins = "dap1_din_pn1", | |
| 27 | "dap1_dout_pn2", | |
| 28 | "dap1_fs_pn0", | |
| 29 | "dap1_sclk_pn3"; | |
| 30 | nvidia,function = "i2s0"; | |
| 31 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 32 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 33 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 34 | }; | |
| 35 | dap2_din_pa4 { | |
| 36 | nvidia,pins = "dap2_din_pa4", | |
| 37 | "dap2_dout_pa5", | |
| 38 | "dap2_fs_pa2", | |
| 39 | "dap2_sclk_pa3"; | |
| 40 | nvidia,function = "i2s1"; | |
| 41 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 42 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 4ffb9385 | 43 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 4b20bcbe LD |
44 | }; |
| 45 | dvfs_pwm_px0 { | |
| 46 | nvidia,pins = "dvfs_pwm_px0"; | |
| 47 | nvidia,function = "cldvfs"; | |
| 48 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 49 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 50 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 51 | }; | |
| 52 | dvfs_clk_px2 { | |
| 53 | nvidia,pins = "dvfs_clk_px2"; | |
| 54 | nvidia,function = "cldvfs"; | |
| 55 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 56 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 57 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 58 | }; | |
| 59 | ulpi_clk_py0 { | |
| 60 | nvidia,pins = "ulpi_clk_py0", | |
| 61 | "ulpi_dir_py1", | |
| 62 | "ulpi_nxt_py2", | |
| 63 | "ulpi_stp_py3"; | |
| 64 | nvidia,function = "spi1"; | |
| 65 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 66 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 67 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 68 | }; | |
| 69 | cam_i2c_scl_pbb1 { | |
| 70 | nvidia,pins = "cam_i2c_scl_pbb1", | |
| 71 | "cam_i2c_sda_pbb2"; | |
| 72 | nvidia,function = "i2c3"; | |
| 73 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 74 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 75 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 76 | nvidia,lock = <TEGRA_PIN_DISABLE>; | |
| 77 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
| 78 | }; | |
| 79 | gen2_i2c_scl_pt5 { | |
| 80 | nvidia,pins = "gen2_i2c_scl_pt5", | |
| 81 | "gen2_i2c_sda_pt6"; | |
| 82 | nvidia,function = "i2c2"; | |
| 83 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 84 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 85 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 86 | nvidia,lock = <TEGRA_PIN_DISABLE>; | |
| 87 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
| 88 | }; | |
| 89 | pg4 { | |
| 90 | nvidia,pins = "pg4", | |
| 91 | "pg5", | |
| 92 | "pg6", | |
| 93 | "pg7", | |
| 94 | "pi3"; | |
| 95 | nvidia,function = "spi4"; | |
| 96 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 97 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 98 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 99 | }; | |
| 100 | ph0 { | |
| 101 | nvidia,pins = "ph0"; | |
| 102 | nvidia,function = "pwm0"; | |
| 103 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 104 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 105 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 106 | }; | |
| 107 | ph1 { | |
| 108 | nvidia,pins = "ph1"; | |
| 109 | nvidia,function = "pwm1"; | |
| 110 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 111 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 112 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 113 | }; | |
| f5cb19b4 TR |
114 | ph2 { |
| 115 | nvidia,pins = "ph2"; | |
| 116 | nvidia,function = "gmi"; | |
| 117 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 118 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 119 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 120 | }; | |
| 4b20bcbe LD |
121 | sdmmc1_clk_pz0 { |
| 122 | nvidia,pins = "sdmmc1_clk_pz0", | |
| 123 | "sdmmc1_cmd_pz1", | |
| 124 | "sdmmc1_dat0_py7", | |
| 125 | "sdmmc1_dat1_py6", | |
| 126 | "sdmmc1_dat2_py5", | |
| 127 | "sdmmc1_dat3_py4"; | |
| 128 | nvidia,function = "sdmmc1"; | |
| 129 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 130 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 131 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 132 | }; | |
| 133 | sdmmc3_clk_pa6 { | |
| 134 | nvidia,pins = "sdmmc3_clk_pa6"; | |
| 135 | nvidia,function = "sdmmc3"; | |
| 136 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 137 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 138 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 139 | }; | |
| 140 | sdmmc3_cmd_pa7 { | |
| 141 | nvidia,pins = "sdmmc3_cmd_pa7", | |
| 142 | "sdmmc3_dat0_pb7", | |
| 143 | "sdmmc3_dat1_pb6", | |
| 144 | "sdmmc3_dat2_pb5", | |
| 145 | "sdmmc3_dat3_pb4", | |
| 146 | "sdmmc3_clk_lb_out_pee4", | |
| 147 | "sdmmc3_clk_lb_in_pee5"; | |
| 148 | nvidia,function = "sdmmc3"; | |
| 149 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 150 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 151 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 152 | }; | |
| 153 | sdmmc4_clk_pcc4 { | |
| 154 | nvidia,pins = "sdmmc4_clk_pcc4"; | |
| 155 | nvidia,function = "sdmmc4"; | |
| 156 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 157 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 158 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 159 | }; | |
| 160 | sdmmc4_cmd_pt7 { | |
| 161 | nvidia,pins = "sdmmc4_cmd_pt7", | |
| 162 | "sdmmc4_dat0_paa0", | |
| 163 | "sdmmc4_dat1_paa1", | |
| 164 | "sdmmc4_dat2_paa2", | |
| 165 | "sdmmc4_dat3_paa3", | |
| 166 | "sdmmc4_dat4_paa4", | |
| 167 | "sdmmc4_dat5_paa5", | |
| 168 | "sdmmc4_dat6_paa6", | |
| 169 | "sdmmc4_dat7_paa7"; | |
| 170 | nvidia,function = "sdmmc4"; | |
| 171 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 172 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 173 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 174 | }; | |
| 175 | pwr_i2c_scl_pz6 { | |
| 176 | nvidia,pins = "pwr_i2c_scl_pz6", | |
| 177 | "pwr_i2c_sda_pz7"; | |
| 178 | nvidia,function = "i2cpwr"; | |
| 179 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 180 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 181 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 182 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
| 183 | }; | |
| 184 | jtag_rtck { | |
| 185 | nvidia,pins = "jtag_rtck"; | |
| 186 | nvidia,function = "rtck"; | |
| 187 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 188 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 189 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 190 | }; | |
| 191 | clk_32k_in { | |
| 192 | nvidia,pins = "clk_32k_in"; | |
| 193 | nvidia,function = "clk"; | |
| 194 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 195 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 196 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 197 | }; | |
| 198 | core_pwr_req { | |
| 199 | nvidia,pins = "core_pwr_req"; | |
| 200 | nvidia,function = "pwron"; | |
| 201 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 202 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 203 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 204 | }; | |
| 205 | cpu_pwr_req { | |
| 206 | nvidia,pins = "cpu_pwr_req"; | |
| 207 | nvidia,function = "cpu"; | |
| 208 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 209 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 210 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 211 | }; | |
| 212 | pwr_int_n { | |
| 213 | nvidia,pins = "pwr_int_n"; | |
| 214 | nvidia,function = "pmi"; | |
| 215 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 216 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 217 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 218 | }; | |
| 219 | reset_out_n { | |
| 220 | nvidia,pins = "reset_out_n"; | |
| 221 | nvidia,function = "reset_out_n"; | |
| 222 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 223 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 224 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 225 | }; | |
| 226 | clk3_out_pee0 { | |
| 227 | nvidia,pins = "clk3_out_pee0"; | |
| 228 | nvidia,function = "extperiph3"; | |
| 229 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 230 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 231 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 232 | }; | |
| 233 | dap4_din_pp5 { | |
| 234 | nvidia,pins = "dap4_din_pp5", | |
| 235 | "dap4_dout_pp6", | |
| 236 | "dap4_fs_pp4", | |
| 237 | "dap4_sclk_pp7"; | |
| 238 | nvidia,function = "i2s3"; | |
| 239 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 240 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 241 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 242 | }; | |
| 243 | gen1_i2c_sda_pc5 { | |
| 244 | nvidia,pins = "gen1_i2c_sda_pc5", | |
| 245 | "gen1_i2c_scl_pc4"; | |
| 246 | nvidia,function = "i2c1"; | |
| 247 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 248 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 249 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 250 | nvidia,lock = <TEGRA_PIN_DISABLE>; | |
| 251 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
| 252 | }; | |
| 253 | pu0 { | |
| 254 | nvidia,pins = "pu0", | |
| 255 | "pu1", | |
| 256 | "pu2", | |
| 257 | "pu3"; | |
| 258 | nvidia,function = "uarta"; | |
| 259 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 4ffb9385 | 260 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 4b20bcbe LD |
261 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 262 | }; | |
| 263 | uart2_cts_n_pj5 { | |
| 264 | nvidia,pins = "uart2_cts_n_pj5", | |
| 265 | "uart2_rts_n_pj6"; | |
| 266 | nvidia,function = "uartb"; | |
| 267 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 268 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 269 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 270 | }; | |
| 271 | uart2_rxd_pc3 { | |
| 272 | nvidia,pins = "uart2_rxd_pc3", | |
| 273 | "uart2_txd_pc2"; | |
| 274 | nvidia,function = "irda"; | |
| 275 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 276 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 277 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 278 | }; | |
| 279 | uart3_cts_n_pa1 { | |
| 280 | nvidia,pins = "uart3_cts_n_pa1", | |
| 281 | "uart3_rts_n_pc0", | |
| 282 | "uart3_rxd_pw7", | |
| 283 | "uart3_txd_pw6"; | |
| 284 | nvidia,function = "uartc"; | |
| 285 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 286 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 287 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 288 | }; | |
| 289 | hdmi_cec_pee3 { | |
| 290 | nvidia,pins = "hdmi_cec_pee3"; | |
| 291 | nvidia,function = "cec"; | |
| 292 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 293 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 294 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 295 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
| 296 | }; | |
| 297 | ddc_scl_pv4 { | |
| 298 | nvidia,pins = "ddc_scl_pv4", | |
| 299 | "ddc_sda_pv5"; | |
| 300 | nvidia,function = "i2c4"; | |
| 301 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 302 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 303 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 304 | }; | |
| 305 | usb_vbus_en0_pn4 { | |
| 306 | nvidia,pins = "usb_vbus_en0_pn4"; | |
| 307 | nvidia,function = "usb"; | |
| 308 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 309 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 310 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 311 | nvidia,lock = <TEGRA_PIN_DISABLE>; | |
| 312 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
| 313 | }; | |
| 314 | usb_vbus_en1_pn5 { | |
| 315 | nvidia,pins = "usb_vbus_en1_pn5"; | |
| 316 | nvidia,function = "usb"; | |
| 317 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 318 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 319 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 320 | nvidia,lock = <TEGRA_PIN_DISABLE>; | |
| 321 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
| 322 | }; | |
| 323 | drive_sdio1 { | |
| 324 | nvidia,pins = "drive_sdio1"; | |
| 325 | nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; | |
| 326 | nvidia,schmitt = <TEGRA_PIN_DISABLE>; | |
| 327 | nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; | |
| 328 | nvidia,pull-down-strength = <32>; | |
| 329 | nvidia,pull-up-strength = <42>; | |
| 330 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; | |
| 331 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; | |
| 332 | }; | |
| 333 | drive_sdio3 { | |
| 334 | nvidia,pins = "drive_sdio3"; | |
| 335 | nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; | |
| 336 | nvidia,schmitt = <TEGRA_PIN_DISABLE>; | |
| 337 | nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; | |
| 338 | nvidia,pull-down-strength = <20>; | |
| 339 | nvidia,pull-up-strength = <36>; | |
| 340 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; | |
| 341 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; | |
| 342 | }; | |
| 343 | drive_gma { | |
| 344 | nvidia,pins = "drive_gma"; | |
| 345 | nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; | |
| 346 | nvidia,schmitt = <TEGRA_PIN_DISABLE>; | |
| 347 | nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; | |
| 348 | nvidia,pull-down-strength = <1>; | |
| 349 | nvidia,pull-up-strength = <2>; | |
| 350 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; | |
| 351 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; | |
| 352 | nvidia,drive-type = <1>; | |
| 353 | }; | |
| 354 | }; | |
| 355 | }; | |
| 356 | ||
| a1425d42 JL |
357 | serial@70006000 { |
| 358 | status = "okay"; | |
| 359 | }; | |
| 360 | ||
| e013485d TR |
361 | pwm: pwm@7000a000 { |
| 362 | status = "okay"; | |
| 363 | }; | |
| 364 | ||
| 9d5b2505 SW |
365 | i2c@7000c000 { |
| 366 | status = "okay"; | |
| 367 | clock-frequency = <100000>; | |
| b0e1caee SW |
368 | |
| 369 | acodec: audio-codec@10 { | |
| 370 | compatible = "maxim,max98090"; | |
| 371 | reg = <0x10>; | |
| 372 | interrupt-parent = <&gpio>; | |
| 373 | interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>; | |
| 374 | }; | |
| 9d5b2505 SW |
375 | }; |
| 376 | ||
| 377 | i2c@7000c400 { | |
| 378 | status = "okay"; | |
| 379 | clock-frequency = <100000>; | |
| 380 | }; | |
| 381 | ||
| 382 | i2c@7000c500 { | |
| 383 | status = "okay"; | |
| 384 | clock-frequency = <100000>; | |
| 385 | }; | |
| 386 | ||
| 387 | i2c@7000c700 { | |
| 388 | status = "okay"; | |
| 389 | clock-frequency = <100000>; | |
| 390 | }; | |
| 391 | ||
| 392 | i2c@7000d000 { | |
| 393 | status = "okay"; | |
| 394 | clock-frequency = <100000>; | |
| 395 | }; | |
| 396 | ||
| a1425d42 JL |
397 | pmc@7000e400 { |
| 398 | nvidia,invert-interrupt; | |
| 6ec1d127 JL |
399 | nvidia,suspend-mode = <1>; |
| 400 | nvidia,cpu-pwr-good-time = <500>; | |
| 401 | nvidia,cpu-pwr-off-time = <300>; | |
| 402 | nvidia,core-pwr-good-time = <641 3845>; | |
| 403 | nvidia,core-pwr-off-time = <61036>; | |
| 404 | nvidia,core-power-req-active-high; | |
| 405 | nvidia,sys-clock-req-active-high; | |
| a1425d42 | 406 | }; |
| 3b86baf2 | 407 | |
| 784c7444 SW |
408 | sdhci@700b0400 { |
| 409 | cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; | |
| 410 | power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; | |
| 411 | status = "okay"; | |
| 412 | bus-width = <4>; | |
| 413 | }; | |
| 414 | ||
| 415 | sdhci@700b0600 { | |
| 416 | status = "okay"; | |
| 417 | bus-width = <8>; | |
| 418 | }; | |
| 419 | ||
| b0e1caee SW |
420 | ahub@70300000 { |
| 421 | i2s@70301100 { | |
| 422 | status = "okay"; | |
| 423 | }; | |
| 424 | }; | |
| 425 | ||
| 3b86baf2 JL |
426 | clocks { |
| 427 | compatible = "simple-bus"; | |
| 428 | #address-cells = <1>; | |
| 429 | #size-cells = <0>; | |
| 430 | ||
| 431 | clk32k_in: clock@0 { | |
| 432 | compatible = "fixed-clock"; | |
| 433 | reg=<0>; | |
| 434 | #clock-cells = <0>; | |
| 435 | clock-frequency = <32768>; | |
| 436 | }; | |
| 437 | }; | |
| b0e1caee SW |
438 | |
| 439 | sound { | |
| 440 | compatible = "nvidia,tegra-audio-max98090-venice2", | |
| 441 | "nvidia,tegra-audio-max98090"; | |
| 442 | nvidia,model = "NVIDIA Tegra Venice2"; | |
| 443 | ||
| 444 | nvidia,audio-routing = | |
| 445 | "Headphones", "HPR", | |
| 446 | "Headphones", "HPL", | |
| 447 | "Speakers", "SPKR", | |
| 448 | "Speakers", "SPKL", | |
| 449 | "Mic Jack", "MICBIAS", | |
| 450 | "IN34", "Mic Jack"; | |
| 451 | ||
| 452 | nvidia,i2s-controller = <&tegra_i2s1>; | |
| 453 | nvidia,audio-codec = <&acodec>; | |
| 454 | ||
| 455 | clocks = <&tegra_car TEGRA124_CLK_PLL_A>, | |
| 456 | <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, | |
| 457 | <&tegra_car TEGRA124_CLK_EXTERN1>; | |
| 458 | clock-names = "pll_a", "pll_a_out0", "mclk"; | |
| 459 | }; | |
| a1425d42 | 460 | }; |