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ARM: tegra: Add IOMMU node to GK20A
[deliverable/linux.git] / arch / arm / boot / dts / tegra124-venice2.dts
CommitLineData
a1425d42
JL		 1/dts-v1/;
2
146db0ea 3#include <dt-bindings/input/input.h>
a1425d42
JL		 4#include "tegra124.dtsi"
5
6/ {
7 model = "NVIDIA Tegra124 Venice2";
8 compatible = "nvidia,venice2", "nvidia,tegra124";
9
b1afa782 10 aliases {
e30cb238
SW		 11 rtc0 = "/i2c@0,7000d000/pmic@40";
12 rtc1 = "/rtc@0,7000e000";
c4574aa0 13 serial0 = &uarta;
b1afa782
SW		 14 };
15
a1425d42 16 memory {
e30cb238 17 reg = <0x0 0x80000000 0x0 0x80000000>;
a1425d42
JL		 18 };
19
e30cb238 20 host1x@0,50000000 {
329c39f8
TR		 21 hdmi@0,54280000 {
22 status = "okay";
23
24 vdd-supply = <&vdd_3v3_hdmi>;
25 pll-supply = <&vdd_hdmi_pll>;
26 hdmi-supply = <&vdd_5v0_hdmi>;
27
28 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
29 nvidia,hpd-gpio =
30 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
31 };
32
e30cb238 33 sor@0,54540000 {
40e231c7
TR		 34 status = "okay";
35
36 nvidia,dpaux = <&dpaux>;
37 nvidia,panel = <&panel>;
38 };
39
edfbad06 40 dpaux@0,545c0000 {
40e231c7
TR		 41 vdd-supply = <&vdd_3v3_panel>;
42 status = "okay";
43 };
44 };
45
e30cb238 46 pinmux: pinmux@0,70000868 {
6dbaff2b
SW		 47 pinctrl-names = "boot";
48 pinctrl-0 = <&pinmux_boot>;
4b20bcbe 49
6dbaff2b 50 pinmux_boot: common {
4b20bcbe
LD		 51 dap_mclk1_pw4 {
52 nvidia,pins = "dap_mclk1_pw4";
53 nvidia,function = "extperiph1";
54 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
55 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
56 nvidia,tristate = <TEGRA_PIN_DISABLE>;
57 };
58 dap1_din_pn1 {
365c483f
LD		 59 nvidia,pins = "dap1_din_pn1";
60 nvidia,function = "i2s0";
61 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
62 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
63 nvidia,tristate = <TEGRA_PIN_ENABLE>;
64 };
65 dap1_dout_pn2 {
66 nvidia,pins = "dap1_dout_pn2",
4b20bcbe
LD		 67 "dap1_fs_pn0",
68 "dap1_sclk_pn3";
69 nvidia,function = "i2s0";
365c483f 70 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4b20bcbe
LD		 71 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
72 nvidia,tristate = <TEGRA_PIN_ENABLE>;
73 };
74 dap2_din_pa4 {
365c483f 75 nvidia,pins = "dap2_din_pa4";
4b20bcbe
LD		 76 nvidia,function = "i2s1";
77 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
78 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4ffb9385 79 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4b20bcbe 80 };
365c483f
LD		 81 dap2_dout_pa5 {
82 nvidia,pins = "dap2_dout_pa5",
83 "dap2_fs_pa2",
84 "dap2_sclk_pa3";
85 nvidia,function = "i2s1";
4b20bcbe
LD		 86 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
87 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
365c483f 88 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4b20bcbe 89 };
365c483f
LD		 90 dvfs_pwm_px0 {
91 nvidia,pins = "dvfs_pwm_px0",
92 "dvfs_clk_px2";
4b20bcbe
LD		 93 nvidia,function = "cldvfs";
94 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
95 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
96 nvidia,tristate = <TEGRA_PIN_DISABLE>;
97 };
98 ulpi_clk_py0 {
99 nvidia,pins = "ulpi_clk_py0",
4b20bcbe
LD		 100 "ulpi_nxt_py2",
101 "ulpi_stp_py3";
102 nvidia,function = "spi1";
365c483f
LD		 103 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
104 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
105 nvidia,tristate = <TEGRA_PIN_DISABLE>;
106 };
107 ulpi_dir_py1 {
108 nvidia,pins = "ulpi_dir_py1";
109 nvidia,function = "spi1";
4b20bcbe 110 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
365c483f 111 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4b20bcbe
LD		 112 nvidia,tristate = <TEGRA_PIN_DISABLE>;
113 };
114 cam_i2c_scl_pbb1 {
115 nvidia,pins = "cam_i2c_scl_pbb1",
116 "cam_i2c_sda_pbb2";
117 nvidia,function = "i2c3";
118 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
119 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
120 nvidia,tristate = <TEGRA_PIN_DISABLE>;
121 nvidia,lock = <TEGRA_PIN_DISABLE>;
122 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
123 };
124 gen2_i2c_scl_pt5 {
125 nvidia,pins = "gen2_i2c_scl_pt5",
126 "gen2_i2c_sda_pt6";
127 nvidia,function = "i2c2";
128 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
129 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
130 nvidia,tristate = <TEGRA_PIN_DISABLE>;
131 nvidia,lock = <TEGRA_PIN_DISABLE>;
132 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
133 };
134 pg4 {
135 nvidia,pins = "pg4",
136 "pg5",
137 "pg6",
4b20bcbe
LD		 138 "pi3";
139 nvidia,function = "spi4";
140 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
141 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
142 nvidia,tristate = <TEGRA_PIN_DISABLE>;
143 };
365c483f
LD		 144 pg7 {
145 nvidia,pins = "pg7";
146 nvidia,function = "spi4";
4b20bcbe 147 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
365c483f
LD		 148 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
149 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4b20bcbe
LD		 150 };
151 ph1 {
152 nvidia,pins = "ph1";
153 nvidia,function = "pwm1";
154 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
155 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
156 nvidia,tristate = <TEGRA_PIN_DISABLE>;
157 };
365c483f
LD		 158 pk0 {
159 nvidia,pins = "pk0",
160 "kb_row15_ps7",
161 "clk_32k_out_pa0";
162 nvidia,function = "soc";
163 nvidia,pull = <TEGRA_PIN_PULL_UP>;
f5cb19b4 164 nvidia,tristate = <TEGRA_PIN_DISABLE>;
365c483f 165 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
f5cb19b4 166 };
4b20bcbe 167 sdmmc1_clk_pz0 {
bf5fd5bf 168 nvidia,pins = "sdmmc1_clk_pz0";
4b20bcbe 169 nvidia,function = "sdmmc1";
bf5fd5bf 170 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4b20bcbe
LD		 171 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
172 nvidia,tristate = <TEGRA_PIN_DISABLE>;
173 };
365c483f
LD		 174 sdmmc1_cmd_pz1 {
175 nvidia,pins = "sdmmc1_cmd_pz1",
176 "sdmmc1_dat0_py7",
177 "sdmmc1_dat1_py6",
178 "sdmmc1_dat2_py5",
179 "sdmmc1_dat3_py4";
180 nvidia,function = "sdmmc1";
181 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
182 nvidia,pull = <TEGRA_PIN_PULL_UP>;
183 nvidia,tristate = <TEGRA_PIN_DISABLE>;
184 };
4b20bcbe
LD		 185 sdmmc3_clk_pa6 {
186 nvidia,pins = "sdmmc3_clk_pa6";
187 nvidia,function = "sdmmc3";
188 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
189 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
190 nvidia,tristate = <TEGRA_PIN_DISABLE>;
191 };
192 sdmmc3_cmd_pa7 {
193 nvidia,pins = "sdmmc3_cmd_pa7",
194 "sdmmc3_dat0_pb7",
195 "sdmmc3_dat1_pb6",
196 "sdmmc3_dat2_pb5",
197 "sdmmc3_dat3_pb4",
198 "sdmmc3_clk_lb_out_pee4",
199 "sdmmc3_clk_lb_in_pee5";
200 nvidia,function = "sdmmc3";
201 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
202 nvidia,pull = <TEGRA_PIN_PULL_UP>;
203 nvidia,tristate = <TEGRA_PIN_DISABLE>;
204 };
205 sdmmc4_clk_pcc4 {
206 nvidia,pins = "sdmmc4_clk_pcc4";
207 nvidia,function = "sdmmc4";
208 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
209 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
210 nvidia,tristate = <TEGRA_PIN_DISABLE>;
211 };
212 sdmmc4_cmd_pt7 {
213 nvidia,pins = "sdmmc4_cmd_pt7",
214 "sdmmc4_dat0_paa0",
215 "sdmmc4_dat1_paa1",
216 "sdmmc4_dat2_paa2",
217 "sdmmc4_dat3_paa3",
218 "sdmmc4_dat4_paa4",
219 "sdmmc4_dat5_paa5",
220 "sdmmc4_dat6_paa6",
221 "sdmmc4_dat7_paa7";
222 nvidia,function = "sdmmc4";
223 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
224 nvidia,pull = <TEGRA_PIN_PULL_UP>;
225 nvidia,tristate = <TEGRA_PIN_DISABLE>;
226 };
227 pwr_i2c_scl_pz6 {
228 nvidia,pins = "pwr_i2c_scl_pz6",
229 "pwr_i2c_sda_pz7";
230 nvidia,function = "i2cpwr";
231 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
232 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
233 nvidia,tristate = <TEGRA_PIN_DISABLE>;
365c483f 234 nvidia,lock = <TEGRA_PIN_DISABLE>;
4b20bcbe
LD		 235 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
236 };
237 jtag_rtck {
238 nvidia,pins = "jtag_rtck";
239 nvidia,function = "rtck";
240 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
241 nvidia,pull = <TEGRA_PIN_PULL_UP>;
242 nvidia,tristate = <TEGRA_PIN_DISABLE>;
243 };
244 clk_32k_in {
245 nvidia,pins = "clk_32k_in";
246 nvidia,function = "clk";
247 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
248 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
249 nvidia,tristate = <TEGRA_PIN_DISABLE>;
250 };
251 core_pwr_req {
252 nvidia,pins = "core_pwr_req";
253 nvidia,function = "pwron";
254 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
255 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
256 nvidia,tristate = <TEGRA_PIN_DISABLE>;
257 };
258 cpu_pwr_req {
259 nvidia,pins = "cpu_pwr_req";
260 nvidia,function = "cpu";
261 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
262 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
263 nvidia,tristate = <TEGRA_PIN_DISABLE>;
264 };
265 pwr_int_n {
266 nvidia,pins = "pwr_int_n";
267 nvidia,function = "pmi";
268 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
269 nvidia,pull = <TEGRA_PIN_PULL_UP>;
270 nvidia,tristate = <TEGRA_PIN_DISABLE>;
271 };
272 reset_out_n {
273 nvidia,pins = "reset_out_n";
274 nvidia,function = "reset_out_n";
275 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
276 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
277 nvidia,tristate = <TEGRA_PIN_DISABLE>;
278 };
279 clk3_out_pee0 {
280 nvidia,pins = "clk3_out_pee0";
281 nvidia,function = "extperiph3";
282 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
283 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
284 nvidia,tristate = <TEGRA_PIN_DISABLE>;
285 };
286 dap4_din_pp5 {
365c483f
LD		 287 nvidia,pins = "dap4_din_pp5";
288 nvidia,function = "i2s3";
289 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
290 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
291 nvidia,tristate = <TEGRA_PIN_ENABLE>;
292 };
293 dap4_dout_pp6 {
294 nvidia,pins = "dap4_dout_pp6",
4b20bcbe
LD		 295 "dap4_fs_pp4",
296 "dap4_sclk_pp7";
297 nvidia,function = "i2s3";
365c483f 298 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4b20bcbe
LD		 299 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
300 nvidia,tristate = <TEGRA_PIN_ENABLE>;
301 };
302 gen1_i2c_sda_pc5 {
303 nvidia,pins = "gen1_i2c_sda_pc5",
304 "gen1_i2c_scl_pc4";
305 nvidia,function = "i2c1";
306 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
307 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
308 nvidia,tristate = <TEGRA_PIN_DISABLE>;
309 nvidia,lock = <TEGRA_PIN_DISABLE>;
365c483f 310 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
4b20bcbe 311 };
365c483f
LD		 312 uart2_cts_n_pj5 {
313 nvidia,pins = "uart2_cts_n_pj5";
314 nvidia,function = "uartb";
4b20bcbe 315 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4ffb9385 316 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4b20bcbe
LD		 317 nvidia,tristate = <TEGRA_PIN_DISABLE>;
318 };
365c483f
LD		 319 uart2_rts_n_pj6 {
320 nvidia,pins = "uart2_rts_n_pj6";
4b20bcbe 321 nvidia,function = "uartb";
365c483f 322 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4b20bcbe
LD		 323 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
324 nvidia,tristate = <TEGRA_PIN_DISABLE>;
325 };
326 uart2_rxd_pc3 {
365c483f 327 nvidia,pins = "uart2_rxd_pc3";
4b20bcbe
LD		 328 nvidia,function = "irda";
329 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
330 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
331 nvidia,tristate = <TEGRA_PIN_DISABLE>;
332 };
365c483f
LD		 333 uart2_txd_pc2 {
334 nvidia,pins = "uart2_txd_pc2";
335 nvidia,function = "irda";
336 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
337 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
338 nvidia,tristate = <TEGRA_PIN_DISABLE>;
339 };
4b20bcbe
LD		 340 uart3_cts_n_pa1 {
341 nvidia,pins = "uart3_cts_n_pa1",
365c483f 342 "uart3_rxd_pw7";
4b20bcbe
LD		 343 nvidia,function = "uartc";
344 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
345 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
346 nvidia,tristate = <TEGRA_PIN_DISABLE>;
347 };
365c483f
LD		 348 uart3_rts_n_pc0 {
349 nvidia,pins = "uart3_rts_n_pc0",
350 "uart3_txd_pw6";
351 nvidia,function = "uartc";
352 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
353 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
354 nvidia,tristate = <TEGRA_PIN_DISABLE>;
355 };
4b20bcbe
LD		 356 hdmi_cec_pee3 {
357 nvidia,pins = "hdmi_cec_pee3";
358 nvidia,function = "cec";
359 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
360 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
361 nvidia,tristate = <TEGRA_PIN_DISABLE>;
365c483f
LD		 362 nvidia,lock = <TEGRA_PIN_DISABLE>;
363 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
364 };
365 hdmi_int_pn7 {
366 nvidia,pins = "hdmi_int_pn7";
367 nvidia,function = "rsvd1";
368 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
369 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
370 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4b20bcbe
LD		 371 };
372 ddc_scl_pv4 {
373 nvidia,pins = "ddc_scl_pv4",
374 "ddc_sda_pv5";
375 nvidia,function = "i2c4";
376 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
377 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
378 nvidia,tristate = <TEGRA_PIN_DISABLE>;
365c483f
LD		 379 nvidia,lock = <TEGRA_PIN_DISABLE>;
380 nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
381 };
382 pj7 {
383 nvidia,pins = "pj7",
384 "pk7";
385 nvidia,function = "uartd";
386 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
387 nvidia,tristate = <TEGRA_PIN_DISABLE>;
388 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
389 };
390 pb0 {
391 nvidia,pins = "pb0",
392 "pb1";
393 nvidia,function = "uartd";
394 nvidia,pull = <TEGRA_PIN_PULL_UP>;
395 nvidia,tristate = <TEGRA_PIN_DISABLE>;
396 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
397 };
398 ph0 {
399 nvidia,pins = "ph0";
400 nvidia,function = "pwm0";
401 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
402 nvidia,tristate = <TEGRA_PIN_DISABLE>;
403 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
404 };
405 kb_row10_ps2 {
406 nvidia,pins = "kb_row10_ps2";
407 nvidia,function = "uarta";
408 nvidia,pull = <TEGRA_PIN_PULL_UP>;
409 nvidia,tristate = <TEGRA_PIN_DISABLE>;
410 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
411 };
412 kb_row9_ps1 {
413 nvidia,pins = "kb_row9_ps1";
414 nvidia,function = "uarta";
415 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
416 nvidia,tristate = <TEGRA_PIN_DISABLE>;
417 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
418 };
419 kb_row6_pr6 {
420 nvidia,pins = "kb_row6_pr6";
421 nvidia,function = "displaya_alt";
422 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
423 nvidia,tristate = <TEGRA_PIN_DISABLE>;
424 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4b20bcbe
LD		 425 };
426 usb_vbus_en0_pn4 {
fa15ffaa
TR		 427 nvidia,pins = "usb_vbus_en0_pn4",
428 "usb_vbus_en1_pn5";
4b20bcbe
LD		 429 nvidia,function = "usb";
430 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
fa15ffaa 431 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4b20bcbe
LD		 432 nvidia,tristate = <TEGRA_PIN_DISABLE>;
433 nvidia,lock = <TEGRA_PIN_DISABLE>;
365c483f 434 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
4b20bcbe
LD		 435 };
436 drive_sdio1 {
437 nvidia,pins = "drive_sdio1";
438 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
439 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
4b20bcbe
LD		 440 nvidia,pull-down-strength = <32>;
441 nvidia,pull-up-strength = <42>;
442 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
443 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
444 };
445 drive_sdio3 {
446 nvidia,pins = "drive_sdio3";
447 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
448 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
4b20bcbe
LD		 449 nvidia,pull-down-strength = <20>;
450 nvidia,pull-up-strength = <36>;
451 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
452 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
453 };
454 drive_gma {
455 nvidia,pins = "drive_gma";
456 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
457 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
458 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
459 nvidia,pull-down-strength = <1>;
460 nvidia,pull-up-strength = <2>;
461 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
462 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
463 nvidia,drive-type = <1>;
464 };
365c483f
LD		 465 als_irq_l {
466 nvidia,pins = "gpio_x3_aud_px3";
467 nvidia,function = "gmi";
468 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
469 nvidia,tristate = <TEGRA_PIN_ENABLE>;
470 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
471 };
472 codec_irq_l {
473 nvidia,pins = "ph4";
474 nvidia,function = "gmi";
475 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
476 nvidia,tristate = <TEGRA_PIN_DISABLE>;
477 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
478 };
479 lcd_bl_en {
480 nvidia,pins = "ph2";
481 nvidia,function = "gmi";
482 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
483 nvidia,tristate = <TEGRA_PIN_DISABLE>;
484 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
485 };
486 touch_irq_l {
487 nvidia,pins = "gpio_w3_aud_pw3";
488 nvidia,function = "spi6";
489 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
490 nvidia,tristate = <TEGRA_PIN_ENABLE>;
491 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
492 };
493 tpm_davint_l {
494 nvidia,pins = "ph6";
495 nvidia,function = "gmi";
496 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
497 nvidia,tristate = <TEGRA_PIN_ENABLE>;
498 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
499 };
500 ts_irq_l {
501 nvidia,pins = "pk2";
502 nvidia,function = "gmi";
503 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
504 nvidia,tristate = <TEGRA_PIN_ENABLE>;
505 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
506 };
507 ts_reset_l {
508 nvidia,pins = "pk4";
509 nvidia,function = "gmi";
510 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
511 nvidia,tristate = <TEGRA_PIN_DISABLE>;
512 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
513 };
514 ts_shdn_l {
515 nvidia,pins = "pk1";
516 nvidia,function = "gmi";
517 nvidia,pull = <TEGRA_PIN_PULL_UP>;
518 nvidia,tristate = <TEGRA_PIN_DISABLE>;
519 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
520 };
521 ph7 {
522 nvidia,pins = "ph7";
523 nvidia,function = "gmi";
524 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
525 nvidia,tristate = <TEGRA_PIN_DISABLE>;
526 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
527 };
528 kb_col0_ap {
529 nvidia,pins = "kb_col0_pq0";
530 nvidia,function = "rsvd4";
531 nvidia,pull = <TEGRA_PIN_PULL_UP>;
532 nvidia,tristate = <TEGRA_PIN_DISABLE>;
533 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
534 };
535 lid_open {
536 nvidia,pins = "kb_row4_pr4";
537 nvidia,function = "rsvd3";
538 nvidia,pull = <TEGRA_PIN_PULL_UP>;
539 nvidia,tristate = <TEGRA_PIN_DISABLE>;
540 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
541 };
542 en_vdd_sd {
543 nvidia,pins = "kb_row0_pr0";
544 nvidia,function = "rsvd4";
545 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
546 nvidia,tristate = <TEGRA_PIN_DISABLE>;
547 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
548 };
549 ac_ok {
550 nvidia,pins = "pj0";
551 nvidia,function = "gmi";
552 nvidia,pull = <TEGRA_PIN_PULL_UP>;
553 nvidia,tristate = <TEGRA_PIN_ENABLE>;
554 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
555 };
556 sensor_irq_l {
557 nvidia,pins = "pi6";
558 nvidia,function = "gmi";
559 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
560 nvidia,tristate = <TEGRA_PIN_DISABLE>;
561 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
562 };
563 wifi_en {
564 nvidia,pins = "gpio_x7_aud_px7";
565 nvidia,function = "rsvd4";
566 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
567 nvidia,tristate = <TEGRA_PIN_DISABLE>;
568 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
569 };
570 wifi_rst_l {
571 nvidia,pins = "clk2_req_pcc5";
572 nvidia,function = "dap";
573 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
574 nvidia,tristate = <TEGRA_PIN_DISABLE>;
575 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
576 };
577 hp_det_l {
578 nvidia,pins = "ulpi_data1_po2";
579 nvidia,function = "spi3";
580 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
581 nvidia,tristate = <TEGRA_PIN_DISABLE>;
582 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
583 };
4b20bcbe
LD		 584 };
585 };
586
e30cb238 587 serial@0,70006000 {
a1425d42
JL		 588 status = "okay";
589 };
590
edfbad06 591 pwm@0,7000a000 {
e013485d
TR		 592 status = "okay";
593 };
594
e30cb238 595 i2c@0,7000c000 {
9d5b2505
SW		 596 status = "okay";
597 clock-frequency = <100000>;
b0e1caee
SW		 598
599 acodec: audio-codec@10 {
600 compatible = "maxim,max98090";
601 reg = <0x10>;
602 interrupt-parent = <&gpio>;
603 interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
604 };
9d5b2505
SW		 605 };
606
e30cb238 607 i2c@0,7000c400 {
9d5b2505
SW		 608 status = "okay";
609 clock-frequency = <100000>;
bf8f0392
SW		 610
611 trackpad@4b {
612 compatible = "atmel,maxtouch";
613 reg = <0x4b>;
614 interrupt-parent = <&gpio>;
615 interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_LOW>;
616 linux,gpio-keymap = <0 0 0 BTN_LEFT>;
617 };
9d5b2505
SW		 618 };
619
e30cb238 620 i2c@0,7000c500 {
9d5b2505
SW		 621 status = "okay";
622 clock-frequency = <100000>;
623 };
624
329c39f8 625 hdmi_ddc: i2c@0,7000c700 {
9d5b2505
SW		 626 status = "okay";
627 clock-frequency = <100000>;
628 };
629
e30cb238 630 i2c@0,7000d000 {
9d5b2505 631 status = "okay";
fcacaba7
LD		 632 clock-frequency = <400000>;
633
fdc44f94 634 pmic: pmic@40 {
fcacaba7
LD		 635 compatible = "ams,as3722";
636 reg = <0x40>;
637 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
638
7be75df2
LD		 639 ams,system-power-controller;
640
fcacaba7
LD		 641 #interrupt-cells = <2>;
642 interrupt-controller;
643
644 gpio-controller;
645 #gpio-cells = <2>;
646
647 pinctrl-names = "default";
648 pinctrl-0 = <&as3722_default>;
649
650 as3722_default: pinmux {
651 gpio0 {
652 pins = "gpio0";
653 function = "gpio";
654 bias-pull-down;
655 };
656
657 gpio1_2_4_7 {
658 pins = "gpio1", "gpio2", "gpio4", "gpio7";
659 function = "gpio";
660 bias-pull-up;
661 };
662
663 gpio3_6 {
664 pins = "gpio3", "gpio6";
665 bias-high-impedance;
666 };
667
668 gpio5 {
669 pins = "gpio5";
670 function = "clk32k-out";
671 };
672 };
673
674 regulators {
af144b8d
TR		 675 vsup-sd2-supply = <&vdd_5v0_sys>;
676 vsup-sd3-supply = <&vdd_5v0_sys>;
677 vsup-sd4-supply = <&vdd_5v0_sys>;
678 vsup-sd5-supply = <&vdd_5v0_sys>;
679 vin-ldo0-supply = <&vdd_1v35_lp0>;
680 vin-ldo1-6-supply = <&vdd_3v3_run>;
681 vin-ldo2-5-7-supply = <&vddio_1v8>;
682 vin-ldo3-4-supply = <&vdd_3v3_sys>;
683 vin-ldo9-10-supply = <&vdd_5v0_sys>;
684 vin-ldo11-supply = <&vdd_3v3_run>;
fcacaba7
LD		 685
686 sd0 {
af144b8d 687 regulator-name = "+VDD_CPU_AP";
fcacaba7
LD		 688 regulator-min-microvolt = <700000>;
689 regulator-max-microvolt = <1400000>;
690 regulator-min-microamp = <3500000>;
691 regulator-max-microamp = <3500000>;
692 regulator-always-on;
693 regulator-boot-on;
ee913f7a 694 ams,ext-control = <2>;
fcacaba7
LD		 695 };
696
697 sd1 {
af144b8d 698 regulator-name = "+VDD_CORE";
fcacaba7
LD		 699 regulator-min-microvolt = <700000>;
700 regulator-max-microvolt = <1350000>;
701 regulator-min-microamp = <2500000>;
702 regulator-max-microamp = <2500000>;
703 regulator-always-on;
704 regulator-boot-on;
ee913f7a 705 ams,ext-control = <1>;
fcacaba7
LD		 706 };
707
af144b8d
TR		 708 vdd_1v35_lp0: sd2 {
709 regulator-name = "+1.35V_LP0(sd2)";
fcacaba7
LD		 710 regulator-min-microvolt = <1350000>;
711 regulator-max-microvolt = <1350000>;
712 regulator-always-on;
713 regulator-boot-on;
714 };
715
716 sd3 {
af144b8d 717 regulator-name = "+1.35V_LP0(sd3)";
fcacaba7
LD		 718 regulator-min-microvolt = <1350000>;
719 regulator-max-microvolt = <1350000>;
720 regulator-always-on;
721 regulator-boot-on;
722 };
723
329c39f8 724 vdd_1v05_run: sd4 {
af144b8d 725 regulator-name = "+1.05V_RUN";
fcacaba7
LD		 726 regulator-min-microvolt = <1050000>;
727 regulator-max-microvolt = <1050000>;
fcacaba7
LD		 728 };
729
af144b8d
TR		 730 vddio_1v8: sd5 {
731 regulator-name = "+1.8V_VDDIO";
fcacaba7
LD		 732 regulator-min-microvolt = <1800000>;
733 regulator-max-microvolt = <1800000>;
734 regulator-boot-on;
735 regulator-always-on;
736 };
737
738 sd6 {
af144b8d 739 regulator-name = "+VDD_GPU_AP";
fcacaba7
LD		 740 regulator-min-microvolt = <650000>;
741 regulator-max-microvolt = <1200000>;
742 regulator-min-microamp = <3500000>;
743 regulator-max-microamp = <3500000>;
744 regulator-boot-on;
745 regulator-always-on;
746 };
747
748 ldo0 {
af144b8d 749 regulator-name = "+1.05V_RUN_AVDD";
fcacaba7
LD		 750 regulator-min-microvolt = <1050000>;
751 regulator-max-microvolt = <1050000>;
752 regulator-boot-on;
753 regulator-always-on;
ee913f7a 754 ams,ext-control = <1>;
fcacaba7
LD		 755 };
756
757 ldo1 {
af144b8d 758 regulator-name = "+1.8V_RUN_CAM";
fcacaba7
LD		 759 regulator-min-microvolt = <1800000>;
760 regulator-max-microvolt = <1800000>;
761 };
762
763 ldo2 {
af144b8d 764 regulator-name = "+1.2V_GEN_AVDD";
fcacaba7
LD		 765 regulator-min-microvolt = <1200000>;
766 regulator-max-microvolt = <1200000>;
767 regulator-boot-on;
768 regulator-always-on;
769 };
770
771 ldo3 {
af144b8d 772 regulator-name = "+1.00V_LP0_VDD_RTC";
fcacaba7
LD		 773 regulator-min-microvolt = <1000000>;
774 regulator-max-microvolt = <1000000>;
775 regulator-boot-on;
776 regulator-always-on;
777 ams,enable-tracking;
778 };
779
431b7be0 780 vdd_run_cam: ldo4 {
af144b8d 781 regulator-name = "+3.3V_RUN_CAM";
fcacaba7
LD		 782 regulator-min-microvolt = <2800000>;
783 regulator-max-microvolt = <2800000>;
fcacaba7
LD		 784 };
785
786 ldo5 {
af144b8d 787 regulator-name = "+1.2V_RUN_CAM_FRONT";
fcacaba7
LD		 788 regulator-min-microvolt = <1200000>;
789 regulator-max-microvolt = <1200000>;
790 };
791
4989b439 792 vddio_sdmmc3: ldo6 {
af144b8d 793 regulator-name = "+VDDIO_SDMMC3";
fcacaba7
LD		 794 regulator-min-microvolt = <1800000>;
795 regulator-max-microvolt = <3300000>;
fcacaba7
LD		 796 };
797
798 ldo7 {
af144b8d 799 regulator-name = "+1.05V_RUN_CAM_REAR";
fcacaba7
LD		 800 regulator-min-microvolt = <1050000>;
801 regulator-max-microvolt = <1050000>;
802 };
803
804 ldo9 {
af144b8d 805 regulator-name = "+2.8V_RUN_TOUCH";
fcacaba7
LD		 806 regulator-min-microvolt = <2800000>;
807 regulator-max-microvolt = <2800000>;
808 };
809
810 ldo10 {
af144b8d 811 regulator-name = "+2.8V_RUN_CAM_AF";
fcacaba7
LD		 812 regulator-min-microvolt = <2800000>;
813 regulator-max-microvolt = <2800000>;
814 };
815
816 ldo11 {
af144b8d 817 regulator-name = "+1.8V_RUN_VPP_FUSE";
fcacaba7
LD		 818 regulator-min-microvolt = <1800000>;
819 regulator-max-microvolt = <1800000>;
820 };
821 };
822 };
9d5b2505
SW		 823 };
824
e30cb238 825 spi@0,7000d400 {
146db0ea
TR		 826 status = "okay";
827
f01dd55a 828 cros_ec: cros-ec@0 {
146db0ea
TR		 829 compatible = "google,cros-ec-spi";
830 spi-max-frequency = <4000000>;
831 interrupt-parent = <&gpio>;
832 interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>;
833 reg = <0>;
834
835 google,cros-ec-spi-msg-delay = <2000>;
72ceddda
DA		 836
837 i2c-tunnel {
838 compatible = "google,cros-ec-i2c-tunnel";
839 #address-cells = <1>;
840 #size-cells = <0>;
841
842 google,remote-bus = <0>;
843
844 charger: bq24735@9 {
845 compatible = "ti,bq24735";
846 reg = <0x9>;
847 interrupt-parent = <&gpio>;
848 interrupts = <TEGRA_GPIO(J, 0)
849 GPIO_ACTIVE_HIGH>;
850 ti,ac-detect-gpios = <&gpio
851 TEGRA_GPIO(J, 0)
852 GPIO_ACTIVE_HIGH>;
853 };
854
855 battery: sbs-battery@b {
856 compatible = "sbs,sbs-battery";
857 reg = <0xb>;
858 sbs,i2c-retry-count = <2>;
859 sbs,poll-retry-count = <1>;
860 };
861 };
146db0ea
TR		 862 };
863 };
864
e30cb238 865 spi@0,7000da00 {
11e5b4f9
SW		 866 status = "okay";
867 spi-max-frequency = <25000000>;
868 spi-flash@0 {
869 compatible = "winbond,w25q32dw";
870 reg = <0>;
871 spi-max-frequency = <20000000>;
872 };
873 };
874
e30cb238 875 pmc@0,7000e400 {
a1425d42 876 nvidia,invert-interrupt;
6ec1d127
JL		 877 nvidia,suspend-mode = <1>;
878 nvidia,cpu-pwr-good-time = <500>;
879 nvidia,cpu-pwr-off-time = <300>;
880 nvidia,core-pwr-good-time = <641 3845>;
881 nvidia,core-pwr-off-time = <61036>;
882 nvidia,core-power-req-active-high;
883 nvidia,sys-clock-req-active-high;
a1425d42 884 };
3b86baf2 885
0f3d3bf8
DR		 886 hda@0,70030000 {
887 status = "okay";
888 };
889
e30cb238 890 sdhci@0,700b0400 {
784c7444
SW		 891 cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
892 power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
2be8f4a6 893 wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
784c7444
SW		 894 status = "okay";
895 bus-width = <4>;
49228cae 896 vqmmc-supply = <&vddio_sdmmc3>;
784c7444
SW		 897 };
898
e30cb238 899 sdhci@0,700b0600 {
784c7444
SW		 900 status = "okay";
901 bus-width = <8>;
ecb53f51 902 non-removable;
784c7444
SW		 903 };
904
e30cb238
SW		 905 ahub@0,70300000 {
906 i2s@0,70301100 {
b0e1caee
SW		 907 status = "okay";
908 };
909 };
910
e30cb238 911 usb@0,7d000000 {
431b7be0
TR		 912 status = "okay";
913 };
914
e30cb238 915 usb-phy@0,7d000000 {
431b7be0
TR		 916 status = "okay";
917 vbus-supply = <&vdd_usb1_vbus>;
918 };
919
e30cb238 920 usb@0,7d004000 {
431b7be0
TR		 921 status = "okay";
922 };
923
e30cb238 924 usb-phy@0,7d004000 {
431b7be0
TR		 925 status = "okay";
926 vbus-supply = <&vdd_run_cam>;
927 };
928
e30cb238 929 usb@0,7d008000 {
431b7be0
TR		 930 status = "okay";
931 };
932
e30cb238 933 usb-phy@0,7d008000 {
431b7be0
TR		 934 status = "okay";
935 vbus-supply = <&vdd_usb3_vbus>;
936 };
937
40e231c7
TR		 938 backlight: backlight {
939 compatible = "pwm-backlight";
940
941 enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
942 power-supply = <&vdd_led>;
943 pwms = <&pwm 1 1000000>;
944
945 brightness-levels = <0 4 8 16 32 64 128 255>;
946 default-brightness-level = <6>;
947 };
948
3b86baf2
JL		 949 clocks {
950 compatible = "simple-bus";
951 #address-cells = <1>;
952 #size-cells = <0>;
953
954 clk32k_in: clock@0 {
955 compatible = "fixed-clock";
4b356608 956 reg = <0>;
3b86baf2
JL		 957 #clock-cells = <0>;
958 clock-frequency = <32768>;
959 };
960 };
b0e1caee 961
3f748d44
TR		 962 gpio-keys {
963 compatible = "gpio-keys";
964
965 power {
966 label = "Power";
967 gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
968 linux,code = <KEY_POWER>;
969 debounce-interval = <10>;
970 gpio-key,wakeup;
971 };
972 };
973
40e231c7
TR		 974 panel: panel {
975 compatible = "lg,lp129qe", "simple-panel";
976
977 backlight = <&backlight>;
978 ddc-i2c-bus = <&dpaux>;
979 };
980
fcacaba7
LD		 981 regulators {
982 compatible = "simple-bus";
983 #address-cells = <1>;
984 #size-cells = <0>;
985
af144b8d 986 vdd_mux: regulator@0 {
fcacaba7
LD		 987 compatible = "regulator-fixed";
988 reg = <0>;
af144b8d
TR		 989 regulator-name = "+VDD_MUX";
990 regulator-min-microvolt = <12000000>;
991 regulator-max-microvolt = <12000000>;
fcacaba7 992 regulator-always-on;
af144b8d 993 regulator-boot-on;
fcacaba7
LD		 994 };
995
af144b8d 996 vdd_5v0_sys: regulator@1 {
fcacaba7
LD		 997 compatible = "regulator-fixed";
998 reg = <1>;
af144b8d
TR		 999 regulator-name = "+5V_SYS";
1000 regulator-min-microvolt = <5000000>;
1001 regulator-max-microvolt = <5000000>;
fcacaba7
LD		 1002 regulator-always-on;
1003 regulator-boot-on;
af144b8d 1004 vin-supply = <&vdd_mux>;
fcacaba7
LD		 1005 };
1006
af144b8d 1007 vdd_3v3_sys: regulator@2 {
fcacaba7
LD		 1008 compatible = "regulator-fixed";
1009 reg = <2>;
af144b8d 1010 regulator-name = "+3.3V_SYS";
fcacaba7
LD		 1011 regulator-min-microvolt = <3300000>;
1012 regulator-max-microvolt = <3300000>;
af144b8d
TR		 1013 regulator-always-on;
1014 regulator-boot-on;
1015 vin-supply = <&vdd_mux>;
fcacaba7
LD		 1016 };
1017
af144b8d 1018 vdd_3v3_run: regulator@3 {
fcacaba7
LD		 1019 compatible = "regulator-fixed";
1020 reg = <3>;
af144b8d
TR		 1021 regulator-name = "+3.3V_RUN";
1022 regulator-min-microvolt = <3300000>;
1023 regulator-max-microvolt = <3300000>;
c7fe7672
SW		 1024 regulator-always-on;
1025 regulator-boot-on;
fdc44f94 1026 gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
fcacaba7 1027 enable-active-high;
af144b8d 1028 vin-supply = <&vdd_3v3_sys>;
fcacaba7
LD		 1029 };
1030
af144b8d 1031 vdd_3v3_hdmi: regulator@4 {
fcacaba7
LD		 1032 compatible = "regulator-fixed";
1033 reg = <4>;
af144b8d 1034 regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
fcacaba7
LD		 1035 regulator-min-microvolt = <3300000>;
1036 regulator-max-microvolt = <3300000>;
af144b8d 1037 vin-supply = <&vdd_3v3_run>;
fcacaba7
LD		 1038 };
1039
af144b8d 1040 vdd_led: regulator@5 {
fcacaba7
LD		 1041 compatible = "regulator-fixed";
1042 reg = <5>;
af144b8d 1043 regulator-name = "+VDD_LED";
467b9b56
TR		 1044 regulator-min-microvolt = <3300000>;
1045 regulator-max-microvolt = <3300000>;
af144b8d 1046 gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
fcacaba7 1047 enable-active-high;
af144b8d 1048 vin-supply = <&vdd_mux>;
fcacaba7
LD		 1049 };
1050
af144b8d 1051 vdd_5v0_ts: regulator@6 {
fcacaba7
LD		 1052 compatible = "regulator-fixed";
1053 reg = <6>;
af144b8d 1054 regulator-name = "+5V_VDD_TS_SW";
fcacaba7
LD		 1055 regulator-min-microvolt = <5000000>;
1056 regulator-max-microvolt = <5000000>;
1057 regulator-boot-on;
af144b8d 1058 gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
fcacaba7 1059 enable-active-high;
af144b8d 1060 vin-supply = <&vdd_5v0_sys>;
fcacaba7
LD		 1061 };
1062
af144b8d 1063 vdd_usb1_vbus: regulator@7 {
fcacaba7
LD		 1064 compatible = "regulator-fixed";
1065 reg = <7>;
af144b8d 1066 regulator-name = "+5V_USB_HS";
fcacaba7
LD		 1067 regulator-min-microvolt = <5000000>;
1068 regulator-max-microvolt = <5000000>;
af144b8d 1069 gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
fcacaba7 1070 enable-active-high;
fcacaba7 1071 gpio-open-drain;
af144b8d 1072 vin-supply = <&vdd_5v0_sys>;
fcacaba7
LD		 1073 };
1074
af144b8d 1075 vdd_usb3_vbus: regulator@8 {
fcacaba7
LD		 1076 compatible = "regulator-fixed";
1077 reg = <8>;
af144b8d
TR		 1078 regulator-name = "+5V_USB_SS";
1079 regulator-min-microvolt = <5000000>;
1080 regulator-max-microvolt = <5000000>;
1081 gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
1082 enable-active-high;
1083 gpio-open-drain;
1084 vin-supply = <&vdd_5v0_sys>;
1085 };
1086
1087 vdd_3v3_panel: regulator@9 {
1088 compatible = "regulator-fixed";
1089 reg = <9>;
1090 regulator-name = "+3.3V_PANEL";
fcacaba7
LD		 1091 regulator-min-microvolt = <3300000>;
1092 regulator-max-microvolt = <3300000>;
fdc44f94 1093 gpio = <&pmic 4 GPIO_ACTIVE_HIGH>;
af144b8d
TR		 1094 enable-active-high;
1095 vin-supply = <&vdd_3v3_run>;
1096 };
1097
1098 vdd_3v3_lp0: regulator@10 {
1099 compatible = "regulator-fixed";
1100 reg = <10>;
1101 regulator-name = "+3.3V_LP0";
1102 regulator-min-microvolt = <3300000>;
1103 regulator-max-microvolt = <3300000>;
1104 /*
1105 * TODO: find a way to wire this up with the USB EHCI
1106 * controllers so that it can be enabled on demand.
1107 */
1108 regulator-always-on;
fdc44f94 1109 gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
fcacaba7 1110 enable-active-high;
af144b8d 1111 vin-supply = <&vdd_3v3_sys>;
fcacaba7 1112 };
329c39f8
TR		 1113
1114 vdd_hdmi_pll: regulator@11 {
1115 compatible = "regulator-fixed";
1116 reg = <11>;
1117 regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL";
1118 regulator-min-microvolt = <1050000>;
1119 regulator-max-microvolt = <1050000>;
1120 gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
1121 vin-supply = <&vdd_1v05_run>;
1122 };
1123
1124 vdd_5v0_hdmi: regulator@12 {
1125 compatible = "regulator-fixed";
1126 reg = <12>;
1127 regulator-name = "+5V_HDMI_CON";
1128 regulator-min-microvolt = <5000000>;
1129 regulator-max-microvolt = <5000000>;
1130 gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
1131 enable-active-high;
1132 vin-supply = <&vdd_5v0_sys>;
1133 };
fcacaba7
LD		 1134 };
1135
b0e1caee
SW		 1136 sound {
1137 compatible = "nvidia,tegra-audio-max98090-venice2",
1138 "nvidia,tegra-audio-max98090";
1139 nvidia,model = "NVIDIA Tegra Venice2";
1140
1141 nvidia,audio-routing =
1142 "Headphones", "HPR",
1143 "Headphones", "HPL",
1144 "Speakers", "SPKR",
1145 "Speakers", "SPKL",
1146 "Mic Jack", "MICBIAS",
1147 "IN34", "Mic Jack";
1148
1149 nvidia,i2s-controller = <&tegra_i2s1>;
1150 nvidia,audio-codec = <&acodec>;
1151
1152 clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
1153 <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
1154 <&tegra_car TEGRA124_CLK_EXTERN1>;
1155 clock-names = "pll_a", "pll_a_out0", "mclk";
1156 };
a1425d42 1157};
f01dd55a
DA		 1158
1159#include "cros-ec-keyboard.dtsi"
Linux kernel - Deliverables
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