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ARM: tegra: add ams AS3722 device to Venice2 DT
[deliverable/linux.git] / arch / arm / boot / dts / tegra124-venice2.dts
CommitLineData
a1425d42
JL		 1/dts-v1/;
2
3#include "tegra124.dtsi"
4
5/ {
6 model = "NVIDIA Tegra124 Venice2";
7 compatible = "nvidia,venice2", "nvidia,tegra124";
8
9 memory {
10 reg = <0x80000000 0x80000000>;
11 };
12
4b20bcbe
LD		 13 pinmux: pinmux@70000868 {
14 pinctrl-names = "default";
15 pinctrl-0 = <&pinmux_default>;
16
17 pinmux_default: common {
18 dap_mclk1_pw4 {
19 nvidia,pins = "dap_mclk1_pw4";
20 nvidia,function = "extperiph1";
21 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
22 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
23 nvidia,tristate = <TEGRA_PIN_DISABLE>;
24 };
25 dap1_din_pn1 {
365c483f
LD		 26 nvidia,pins = "dap1_din_pn1";
27 nvidia,function = "i2s0";
28 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
29 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
30 nvidia,tristate = <TEGRA_PIN_ENABLE>;
31 };
32 dap1_dout_pn2 {
33 nvidia,pins = "dap1_dout_pn2",
4b20bcbe
LD		 34 "dap1_fs_pn0",
35 "dap1_sclk_pn3";
36 nvidia,function = "i2s0";
365c483f 37 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4b20bcbe
LD		 38 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
39 nvidia,tristate = <TEGRA_PIN_ENABLE>;
40 };
41 dap2_din_pa4 {
365c483f 42 nvidia,pins = "dap2_din_pa4";
4b20bcbe
LD		 43 nvidia,function = "i2s1";
44 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
45 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4ffb9385 46 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4b20bcbe 47 };
365c483f
LD		 48 dap2_dout_pa5 {
49 nvidia,pins = "dap2_dout_pa5",
50 "dap2_fs_pa2",
51 "dap2_sclk_pa3";
52 nvidia,function = "i2s1";
4b20bcbe
LD		 53 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
54 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
365c483f 55 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4b20bcbe 56 };
365c483f
LD		 57 dvfs_pwm_px0 {
58 nvidia,pins = "dvfs_pwm_px0",
59 "dvfs_clk_px2";
4b20bcbe
LD		 60 nvidia,function = "cldvfs";
61 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
62 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
63 nvidia,tristate = <TEGRA_PIN_DISABLE>;
64 };
65 ulpi_clk_py0 {
66 nvidia,pins = "ulpi_clk_py0",
4b20bcbe
LD		 67 "ulpi_nxt_py2",
68 "ulpi_stp_py3";
69 nvidia,function = "spi1";
365c483f
LD		 70 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
71 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
72 nvidia,tristate = <TEGRA_PIN_DISABLE>;
73 };
74 ulpi_dir_py1 {
75 nvidia,pins = "ulpi_dir_py1";
76 nvidia,function = "spi1";
4b20bcbe 77 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
365c483f 78 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4b20bcbe
LD		 79 nvidia,tristate = <TEGRA_PIN_DISABLE>;
80 };
81 cam_i2c_scl_pbb1 {
82 nvidia,pins = "cam_i2c_scl_pbb1",
83 "cam_i2c_sda_pbb2";
84 nvidia,function = "i2c3";
85 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
86 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
87 nvidia,tristate = <TEGRA_PIN_DISABLE>;
88 nvidia,lock = <TEGRA_PIN_DISABLE>;
89 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
90 };
91 gen2_i2c_scl_pt5 {
92 nvidia,pins = "gen2_i2c_scl_pt5",
93 "gen2_i2c_sda_pt6";
94 nvidia,function = "i2c2";
95 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
96 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
97 nvidia,tristate = <TEGRA_PIN_DISABLE>;
98 nvidia,lock = <TEGRA_PIN_DISABLE>;
99 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
100 };
101 pg4 {
102 nvidia,pins = "pg4",
103 "pg5",
104 "pg6",
4b20bcbe
LD		 105 "pi3";
106 nvidia,function = "spi4";
107 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
108 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
109 nvidia,tristate = <TEGRA_PIN_DISABLE>;
110 };
365c483f
LD		 111 pg7 {
112 nvidia,pins = "pg7";
113 nvidia,function = "spi4";
4b20bcbe 114 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
365c483f
LD		 115 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
116 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4b20bcbe
LD		 117 };
118 ph1 {
119 nvidia,pins = "ph1";
120 nvidia,function = "pwm1";
121 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
122 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
123 nvidia,tristate = <TEGRA_PIN_DISABLE>;
124 };
365c483f
LD		 125 pk0 {
126 nvidia,pins = "pk0",
127 "kb_row15_ps7",
128 "clk_32k_out_pa0";
129 nvidia,function = "soc";
130 nvidia,pull = <TEGRA_PIN_PULL_UP>;
f5cb19b4 131 nvidia,tristate = <TEGRA_PIN_DISABLE>;
365c483f 132 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
f5cb19b4 133 };
4b20bcbe
LD		 134 sdmmc1_clk_pz0 {
135 nvidia,pins = "sdmmc1_clk_pz0",
136 "sdmmc1_cmd_pz1",
137 "sdmmc1_dat0_py7",
138 "sdmmc1_dat1_py6",
139 "sdmmc1_dat2_py5",
140 "sdmmc1_dat3_py4";
141 nvidia,function = "sdmmc1";
142 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
143 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
144 nvidia,tristate = <TEGRA_PIN_DISABLE>;
145 };
365c483f
LD		 146 sdmmc1_cmd_pz1 {
147 nvidia,pins = "sdmmc1_cmd_pz1",
148 "sdmmc1_dat0_py7",
149 "sdmmc1_dat1_py6",
150 "sdmmc1_dat2_py5",
151 "sdmmc1_dat3_py4";
152 nvidia,function = "sdmmc1";
153 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
154 nvidia,pull = <TEGRA_PIN_PULL_UP>;
155 nvidia,tristate = <TEGRA_PIN_DISABLE>;
156 };
4b20bcbe
LD		 157 sdmmc3_clk_pa6 {
158 nvidia,pins = "sdmmc3_clk_pa6";
159 nvidia,function = "sdmmc3";
160 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
161 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
162 nvidia,tristate = <TEGRA_PIN_DISABLE>;
163 };
164 sdmmc3_cmd_pa7 {
165 nvidia,pins = "sdmmc3_cmd_pa7",
166 "sdmmc3_dat0_pb7",
167 "sdmmc3_dat1_pb6",
168 "sdmmc3_dat2_pb5",
169 "sdmmc3_dat3_pb4",
170 "sdmmc3_clk_lb_out_pee4",
171 "sdmmc3_clk_lb_in_pee5";
172 nvidia,function = "sdmmc3";
173 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
174 nvidia,pull = <TEGRA_PIN_PULL_UP>;
175 nvidia,tristate = <TEGRA_PIN_DISABLE>;
176 };
177 sdmmc4_clk_pcc4 {
178 nvidia,pins = "sdmmc4_clk_pcc4";
179 nvidia,function = "sdmmc4";
180 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
181 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
182 nvidia,tristate = <TEGRA_PIN_DISABLE>;
183 };
184 sdmmc4_cmd_pt7 {
185 nvidia,pins = "sdmmc4_cmd_pt7",
186 "sdmmc4_dat0_paa0",
187 "sdmmc4_dat1_paa1",
188 "sdmmc4_dat2_paa2",
189 "sdmmc4_dat3_paa3",
190 "sdmmc4_dat4_paa4",
191 "sdmmc4_dat5_paa5",
192 "sdmmc4_dat6_paa6",
193 "sdmmc4_dat7_paa7";
194 nvidia,function = "sdmmc4";
195 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
196 nvidia,pull = <TEGRA_PIN_PULL_UP>;
197 nvidia,tristate = <TEGRA_PIN_DISABLE>;
198 };
199 pwr_i2c_scl_pz6 {
200 nvidia,pins = "pwr_i2c_scl_pz6",
201 "pwr_i2c_sda_pz7";
202 nvidia,function = "i2cpwr";
203 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
204 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
205 nvidia,tristate = <TEGRA_PIN_DISABLE>;
365c483f 206 nvidia,lock = <TEGRA_PIN_DISABLE>;
4b20bcbe
LD		 207 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
208 };
209 jtag_rtck {
210 nvidia,pins = "jtag_rtck";
211 nvidia,function = "rtck";
212 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
213 nvidia,pull = <TEGRA_PIN_PULL_UP>;
214 nvidia,tristate = <TEGRA_PIN_DISABLE>;
215 };
216 clk_32k_in {
217 nvidia,pins = "clk_32k_in";
218 nvidia,function = "clk";
219 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
220 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
221 nvidia,tristate = <TEGRA_PIN_DISABLE>;
222 };
223 core_pwr_req {
224 nvidia,pins = "core_pwr_req";
225 nvidia,function = "pwron";
226 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
227 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
228 nvidia,tristate = <TEGRA_PIN_DISABLE>;
229 };
230 cpu_pwr_req {
231 nvidia,pins = "cpu_pwr_req";
232 nvidia,function = "cpu";
233 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
234 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
235 nvidia,tristate = <TEGRA_PIN_DISABLE>;
236 };
237 pwr_int_n {
238 nvidia,pins = "pwr_int_n";
239 nvidia,function = "pmi";
240 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
241 nvidia,pull = <TEGRA_PIN_PULL_UP>;
242 nvidia,tristate = <TEGRA_PIN_DISABLE>;
243 };
244 reset_out_n {
245 nvidia,pins = "reset_out_n";
246 nvidia,function = "reset_out_n";
247 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
248 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
249 nvidia,tristate = <TEGRA_PIN_DISABLE>;
250 };
251 clk3_out_pee0 {
252 nvidia,pins = "clk3_out_pee0";
253 nvidia,function = "extperiph3";
254 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
255 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
256 nvidia,tristate = <TEGRA_PIN_DISABLE>;
257 };
258 dap4_din_pp5 {
365c483f
LD		 259 nvidia,pins = "dap4_din_pp5";
260 nvidia,function = "i2s3";
261 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
262 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
263 nvidia,tristate = <TEGRA_PIN_ENABLE>;
264 };
265 dap4_dout_pp6 {
266 nvidia,pins = "dap4_dout_pp6",
4b20bcbe
LD		 267 "dap4_fs_pp4",
268 "dap4_sclk_pp7";
269 nvidia,function = "i2s3";
365c483f 270 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4b20bcbe
LD		 271 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
272 nvidia,tristate = <TEGRA_PIN_ENABLE>;
273 };
274 gen1_i2c_sda_pc5 {
275 nvidia,pins = "gen1_i2c_sda_pc5",
276 "gen1_i2c_scl_pc4";
277 nvidia,function = "i2c1";
278 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
279 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
280 nvidia,tristate = <TEGRA_PIN_DISABLE>;
281 nvidia,lock = <TEGRA_PIN_DISABLE>;
365c483f 282 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
4b20bcbe 283 };
365c483f
LD		 284 uart2_cts_n_pj5 {
285 nvidia,pins = "uart2_cts_n_pj5";
286 nvidia,function = "uartb";
4b20bcbe 287 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4ffb9385 288 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4b20bcbe
LD		 289 nvidia,tristate = <TEGRA_PIN_DISABLE>;
290 };
365c483f
LD		 291 uart2_rts_n_pj6 {
292 nvidia,pins = "uart2_rts_n_pj6";
4b20bcbe 293 nvidia,function = "uartb";
365c483f 294 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4b20bcbe
LD		 295 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
296 nvidia,tristate = <TEGRA_PIN_DISABLE>;
297 };
298 uart2_rxd_pc3 {
365c483f 299 nvidia,pins = "uart2_rxd_pc3";
4b20bcbe
LD		 300 nvidia,function = "irda";
301 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
302 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
303 nvidia,tristate = <TEGRA_PIN_DISABLE>;
304 };
365c483f
LD		 305 uart2_txd_pc2 {
306 nvidia,pins = "uart2_txd_pc2";
307 nvidia,function = "irda";
308 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
309 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
310 nvidia,tristate = <TEGRA_PIN_DISABLE>;
311 };
4b20bcbe
LD		 312 uart3_cts_n_pa1 {
313 nvidia,pins = "uart3_cts_n_pa1",
365c483f 314 "uart3_rxd_pw7";
4b20bcbe
LD		 315 nvidia,function = "uartc";
316 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
317 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
318 nvidia,tristate = <TEGRA_PIN_DISABLE>;
319 };
365c483f
LD		 320 uart3_rts_n_pc0 {
321 nvidia,pins = "uart3_rts_n_pc0",
322 "uart3_txd_pw6";
323 nvidia,function = "uartc";
324 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
325 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
326 nvidia,tristate = <TEGRA_PIN_DISABLE>;
327 };
4b20bcbe
LD		 328 hdmi_cec_pee3 {
329 nvidia,pins = "hdmi_cec_pee3";
330 nvidia,function = "cec";
331 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
332 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
333 nvidia,tristate = <TEGRA_PIN_DISABLE>;
365c483f
LD		 334 nvidia,lock = <TEGRA_PIN_DISABLE>;
335 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
336 };
337 hdmi_int_pn7 {
338 nvidia,pins = "hdmi_int_pn7";
339 nvidia,function = "rsvd1";
340 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
341 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
342 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4b20bcbe
LD		 343 };
344 ddc_scl_pv4 {
345 nvidia,pins = "ddc_scl_pv4",
346 "ddc_sda_pv5";
347 nvidia,function = "i2c4";
348 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
349 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
350 nvidia,tristate = <TEGRA_PIN_DISABLE>;
365c483f
LD		 351 nvidia,lock = <TEGRA_PIN_DISABLE>;
352 nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
353 };
354 pj7 {
355 nvidia,pins = "pj7",
356 "pk7";
357 nvidia,function = "uartd";
358 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
359 nvidia,tristate = <TEGRA_PIN_DISABLE>;
360 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
361 };
362 pb0 {
363 nvidia,pins = "pb0",
364 "pb1";
365 nvidia,function = "uartd";
366 nvidia,pull = <TEGRA_PIN_PULL_UP>;
367 nvidia,tristate = <TEGRA_PIN_DISABLE>;
368 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
369 };
370 ph0 {
371 nvidia,pins = "ph0";
372 nvidia,function = "pwm0";
373 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
374 nvidia,tristate = <TEGRA_PIN_DISABLE>;
375 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
376 };
377 kb_row10_ps2 {
378 nvidia,pins = "kb_row10_ps2";
379 nvidia,function = "uarta";
380 nvidia,pull = <TEGRA_PIN_PULL_UP>;
381 nvidia,tristate = <TEGRA_PIN_DISABLE>;
382 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
383 };
384 kb_row9_ps1 {
385 nvidia,pins = "kb_row9_ps1";
386 nvidia,function = "uarta";
387 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
388 nvidia,tristate = <TEGRA_PIN_DISABLE>;
389 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
390 };
391 kb_row6_pr6 {
392 nvidia,pins = "kb_row6_pr6";
393 nvidia,function = "displaya_alt";
394 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
395 nvidia,tristate = <TEGRA_PIN_DISABLE>;
396 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4b20bcbe
LD		 397 };
398 usb_vbus_en0_pn4 {
399 nvidia,pins = "usb_vbus_en0_pn4";
400 nvidia,function = "usb";
401 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
402 nvidia,pull = <TEGRA_PIN_PULL_UP>;
403 nvidia,tristate = <TEGRA_PIN_DISABLE>;
404 nvidia,lock = <TEGRA_PIN_DISABLE>;
365c483f 405 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
4b20bcbe
LD		 406 };
407 usb_vbus_en1_pn5 {
408 nvidia,pins = "usb_vbus_en1_pn5";
409 nvidia,function = "usb";
410 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
411 nvidia,pull = <TEGRA_PIN_PULL_UP>;
412 nvidia,tristate = <TEGRA_PIN_DISABLE>;
413 nvidia,lock = <TEGRA_PIN_DISABLE>;
365c483f 414 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
4b20bcbe
LD		 415 };
416 drive_sdio1 {
417 nvidia,pins = "drive_sdio1";
418 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
419 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
420 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
421 nvidia,pull-down-strength = <32>;
422 nvidia,pull-up-strength = <42>;
423 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
424 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
425 };
426 drive_sdio3 {
427 nvidia,pins = "drive_sdio3";
428 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
429 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
430 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
431 nvidia,pull-down-strength = <20>;
432 nvidia,pull-up-strength = <36>;
433 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
434 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
435 };
436 drive_gma {
437 nvidia,pins = "drive_gma";
438 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
439 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
440 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
441 nvidia,pull-down-strength = <1>;
442 nvidia,pull-up-strength = <2>;
443 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
444 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
445 nvidia,drive-type = <1>;
446 };
365c483f
LD		 447 als_irq_l {
448 nvidia,pins = "gpio_x3_aud_px3";
449 nvidia,function = "gmi";
450 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
451 nvidia,tristate = <TEGRA_PIN_ENABLE>;
452 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
453 };
454 codec_irq_l {
455 nvidia,pins = "ph4";
456 nvidia,function = "gmi";
457 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
458 nvidia,tristate = <TEGRA_PIN_DISABLE>;
459 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
460 };
461 lcd_bl_en {
462 nvidia,pins = "ph2";
463 nvidia,function = "gmi";
464 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
465 nvidia,tristate = <TEGRA_PIN_DISABLE>;
466 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
467 };
468 touch_irq_l {
469 nvidia,pins = "gpio_w3_aud_pw3";
470 nvidia,function = "spi6";
471 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
472 nvidia,tristate = <TEGRA_PIN_ENABLE>;
473 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
474 };
475 tpm_davint_l {
476 nvidia,pins = "ph6";
477 nvidia,function = "gmi";
478 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
479 nvidia,tristate = <TEGRA_PIN_ENABLE>;
480 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
481 };
482 ts_irq_l {
483 nvidia,pins = "pk2";
484 nvidia,function = "gmi";
485 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
486 nvidia,tristate = <TEGRA_PIN_ENABLE>;
487 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
488 };
489 ts_reset_l {
490 nvidia,pins = "pk4";
491 nvidia,function = "gmi";
492 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
493 nvidia,tristate = <TEGRA_PIN_DISABLE>;
494 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
495 };
496 ts_shdn_l {
497 nvidia,pins = "pk1";
498 nvidia,function = "gmi";
499 nvidia,pull = <TEGRA_PIN_PULL_UP>;
500 nvidia,tristate = <TEGRA_PIN_DISABLE>;
501 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
502 };
503 ph7 {
504 nvidia,pins = "ph7";
505 nvidia,function = "gmi";
506 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
507 nvidia,tristate = <TEGRA_PIN_DISABLE>;
508 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
509 };
510 kb_col0_ap {
511 nvidia,pins = "kb_col0_pq0";
512 nvidia,function = "rsvd4";
513 nvidia,pull = <TEGRA_PIN_PULL_UP>;
514 nvidia,tristate = <TEGRA_PIN_DISABLE>;
515 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
516 };
517 lid_open {
518 nvidia,pins = "kb_row4_pr4";
519 nvidia,function = "rsvd3";
520 nvidia,pull = <TEGRA_PIN_PULL_UP>;
521 nvidia,tristate = <TEGRA_PIN_DISABLE>;
522 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
523 };
524 en_vdd_sd {
525 nvidia,pins = "kb_row0_pr0";
526 nvidia,function = "rsvd4";
527 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
528 nvidia,tristate = <TEGRA_PIN_DISABLE>;
529 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
530 };
531 ac_ok {
532 nvidia,pins = "pj0";
533 nvidia,function = "gmi";
534 nvidia,pull = <TEGRA_PIN_PULL_UP>;
535 nvidia,tristate = <TEGRA_PIN_ENABLE>;
536 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
537 };
538 sensor_irq_l {
539 nvidia,pins = "pi6";
540 nvidia,function = "gmi";
541 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
542 nvidia,tristate = <TEGRA_PIN_DISABLE>;
543 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
544 };
545 wifi_en {
546 nvidia,pins = "gpio_x7_aud_px7";
547 nvidia,function = "rsvd4";
548 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
549 nvidia,tristate = <TEGRA_PIN_DISABLE>;
550 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
551 };
552 wifi_rst_l {
553 nvidia,pins = "clk2_req_pcc5";
554 nvidia,function = "dap";
555 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
556 nvidia,tristate = <TEGRA_PIN_DISABLE>;
557 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
558 };
559 hp_det_l {
560 nvidia,pins = "ulpi_data1_po2";
561 nvidia,function = "spi3";
562 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
563 nvidia,tristate = <TEGRA_PIN_DISABLE>;
564 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
565 };
4b20bcbe
LD		 566 };
567 };
568
a1425d42
JL		 569 serial@70006000 {
570 status = "okay";
571 };
572
e013485d
TR		 573 pwm: pwm@7000a000 {
574 status = "okay";
575 };
576
9d5b2505
SW		 577 i2c@7000c000 {
578 status = "okay";
579 clock-frequency = <100000>;
b0e1caee
SW		 580
581 acodec: audio-codec@10 {
582 compatible = "maxim,max98090";
583 reg = <0x10>;
584 interrupt-parent = <&gpio>;
585 interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
586 };
9d5b2505
SW		 587 };
588
589 i2c@7000c400 {
590 status = "okay";
591 clock-frequency = <100000>;
592 };
593
594 i2c@7000c500 {
595 status = "okay";
596 clock-frequency = <100000>;
597 };
598
599 i2c@7000c700 {
600 status = "okay";
601 clock-frequency = <100000>;
602 };
603
604 i2c@7000d000 {
605 status = "okay";
fcacaba7
LD		 606 clock-frequency = <400000>;
607
608 as3722: as3722@40 {
609 compatible = "ams,as3722";
610 reg = <0x40>;
611 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
612
613 #interrupt-cells = <2>;
614 interrupt-controller;
615
616 gpio-controller;
617 #gpio-cells = <2>;
618
619 pinctrl-names = "default";
620 pinctrl-0 = <&as3722_default>;
621
622 as3722_default: pinmux {
623 gpio0 {
624 pins = "gpio0";
625 function = "gpio";
626 bias-pull-down;
627 };
628
629 gpio1_2_4_7 {
630 pins = "gpio1", "gpio2", "gpio4", "gpio7";
631 function = "gpio";
632 bias-pull-up;
633 };
634
635 gpio3_6 {
636 pins = "gpio3", "gpio6";
637 bias-high-impedance;
638 };
639
640 gpio5 {
641 pins = "gpio5";
642 function = "clk32k-out";
643 };
644 };
645
646 regulators {
647 vsup-sd2-supply = <&vdd_ac_bat_reg>;
648 vsup-sd3-supply = <&vdd_ac_bat_reg>;
649 vsup-sd4-supply = <&vdd_ac_bat_reg>;
650 vsup-sd5-supply = <&vdd_ac_bat_reg>;
651 vin-ldo0-supply = <&as3722_sd2>;
652 vin-ldo1-6-supply = <&vdd_ac_bat_reg>;
653 vin-ldo2-5-7-supply = <&as3722_sd5>;
654 vin-ldo3-4-supply = <&vdd_ac_bat_reg>;
655 vin-ldo9-10-supply = <&vdd_ac_bat_reg>;
656 vin-ldo11-supply = <&vdd_ac_bat_reg>;
657
658 sd0 {
659 regulator-name = "vdd-cpu";
660 regulator-min-microvolt = <700000>;
661 regulator-max-microvolt = <1400000>;
662 regulator-min-microamp = <3500000>;
663 regulator-max-microamp = <3500000>;
664 regulator-always-on;
665 regulator-boot-on;
666 ams,external-control = <2>;
667 };
668
669 sd1 {
670 regulator-name = "vdd-core";
671 regulator-min-microvolt = <700000>;
672 regulator-max-microvolt = <1350000>;
673 regulator-min-microamp = <2500000>;
674 regulator-max-microamp = <2500000>;
675 regulator-always-on;
676 regulator-boot-on;
677 ams,external-control = <1>;
678 };
679
680 as3722_sd2: sd2 {
681 regulator-name = "vddio-ddr";
682 regulator-min-microvolt = <1350000>;
683 regulator-max-microvolt = <1350000>;
684 regulator-always-on;
685 regulator-boot-on;
686 };
687
688 sd3 {
689 regulator-name = "vddio-ddr-2phase";
690 regulator-min-microvolt = <1350000>;
691 regulator-max-microvolt = <1350000>;
692 regulator-always-on;
693 regulator-boot-on;
694 };
695
696 sd4 {
697 regulator-name = "avdd-pex-sata";
698 regulator-min-microvolt = <1050000>;
699 regulator-max-microvolt = <1050000>;
700 regulator-boot-on;
701 regulator-always-on;
702 };
703
704 as3722_sd5: sd5 {
705 regulator-name = "vddio-sys";
706 regulator-min-microvolt = <1800000>;
707 regulator-max-microvolt = <1800000>;
708 regulator-boot-on;
709 regulator-always-on;
710 };
711
712 sd6 {
713 regulator-name = "vdd-gpu";
714 regulator-min-microvolt = <650000>;
715 regulator-max-microvolt = <1200000>;
716 regulator-min-microamp = <3500000>;
717 regulator-max-microamp = <3500000>;
718 regulator-boot-on;
719 regulator-always-on;
720 };
721
722 ldo0 {
723 regulator-name = "avdd_pll";
724 regulator-min-microvolt = <1050000>;
725 regulator-max-microvolt = <1050000>;
726 regulator-boot-on;
727 regulator-always-on;
728 ams,external-control = <1>;
729 };
730
731 ldo1 {
732 regulator-name = "run-cam-1.8";
733 regulator-min-microvolt = <1800000>;
734 regulator-max-microvolt = <1800000>;
735 };
736
737 ldo2 {
738 regulator-name = "gen-avdd,vddio-hsic";
739 regulator-min-microvolt = <1200000>;
740 regulator-max-microvolt = <1200000>;
741 regulator-boot-on;
742 regulator-always-on;
743 };
744
745 ldo3 {
746 regulator-name = "vdd-rtc";
747 regulator-min-microvolt = <1000000>;
748 regulator-max-microvolt = <1000000>;
749 regulator-boot-on;
750 regulator-always-on;
751 ams,enable-tracking;
752 };
753
754 ldo4 {
755 regulator-name = "vdd-cam";
756 regulator-min-microvolt = <2800000>;
757 regulator-max-microvolt = <2800000>;
758 regulator-boot-on;
759 regulator-always-on;
760 };
761
762 ldo5 {
763 regulator-name = "vdd-cam-front";
764 regulator-min-microvolt = <1200000>;
765 regulator-max-microvolt = <1200000>;
766 };
767
768 ldo6 {
769 regulator-name = "vddio-sdmmc3";
770 regulator-min-microvolt = <1800000>;
771 regulator-max-microvolt = <3300000>;
772 regulator-boot-on;
773 regulator-always-on;
774 };
775
776 ldo7 {
777 regulator-name = "vdd-cam-rear";
778 regulator-min-microvolt = <1050000>;
779 regulator-max-microvolt = <1050000>;
780 };
781
782 ldo9 {
783 regulator-name = "vdd-touch";
784 regulator-min-microvolt = <2800000>;
785 regulator-max-microvolt = <2800000>;
786 };
787
788 ldo10 {
789 regulator-name = "vdd-cam-af";
790 regulator-min-microvolt = <2800000>;
791 regulator-max-microvolt = <2800000>;
792 };
793
794 ldo11 {
795 regulator-name = "vpp-fuse";
796 regulator-min-microvolt = <1800000>;
797 regulator-max-microvolt = <1800000>;
798 };
799 };
800 };
9d5b2505
SW		 801 };
802
a1425d42
JL		 803 pmc@7000e400 {
804 nvidia,invert-interrupt;
6ec1d127
JL		 805 nvidia,suspend-mode = <1>;
806 nvidia,cpu-pwr-good-time = <500>;
807 nvidia,cpu-pwr-off-time = <300>;
808 nvidia,core-pwr-good-time = <641 3845>;
809 nvidia,core-pwr-off-time = <61036>;
810 nvidia,core-power-req-active-high;
811 nvidia,sys-clock-req-active-high;
a1425d42 812 };
3b86baf2 813
784c7444
SW		 814 sdhci@700b0400 {
815 cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
816 power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
817 status = "okay";
818 bus-width = <4>;
819 };
820
821 sdhci@700b0600 {
822 status = "okay";
823 bus-width = <8>;
824 };
825
b0e1caee
SW		 826 ahub@70300000 {
827 i2s@70301100 {
828 status = "okay";
829 };
830 };
831
3b86baf2
JL		 832 clocks {
833 compatible = "simple-bus";
834 #address-cells = <1>;
835 #size-cells = <0>;
836
837 clk32k_in: clock@0 {
838 compatible = "fixed-clock";
839 reg=<0>;
840 #clock-cells = <0>;
841 clock-frequency = <32768>;
842 };
843 };
b0e1caee 844
fcacaba7
LD		 845 regulators {
846 compatible = "simple-bus";
847 #address-cells = <1>;
848 #size-cells = <0>;
849
850 vdd_ac_bat_reg: regulator@0 {
851 compatible = "regulator-fixed";
852 reg = <0>;
853 regulator-name = "vdd_ac_bat";
854 regulator-min-microvolt = <5000000>;
855 regulator-max-microvolt = <5000000>;
856 regulator-always-on;
857 };
858
859 vdd_3v3_reg: regulator@1 {
860 compatible = "regulator-fixed";
861 reg = <1>;
862 regulator-name = "vdd_3v3";
863 regulator-min-microvolt = <3300000>;
864 regulator-max-microvolt = <3300000>;
865 regulator-always-on;
866 regulator-boot-on;
867 enable-active-high;
868 gpio = <&as3722 1 GPIO_ACTIVE_HIGH>;
869 };
870
871 vdd_3v3_modem_reg: regulator@2 {
872 compatible = "regulator-fixed";
873 reg = <2>;
874 regulator-name = "vdd-modem-3v3";
875 regulator-min-microvolt = <3300000>;
876 regulator-max-microvolt = <3300000>;
877 enable-active-high;
878 gpio = <&as3722 2 GPIO_ACTIVE_HIGH>;
879 };
880
881 vdd_hdmi_5v0_reg: regulator@3 {
882 compatible = "regulator-fixed";
883 reg = <3>;
884 regulator-name = "vdd-hdmi-5v0";
885 regulator-min-microvolt = <5000000>;
886 regulator-max-microvolt = <5000000>;
887 enable-active-high;
888 gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
889 };
890
891 vdd_bl_reg: regulator@4 {
892 compatible = "regulator-fixed";
893 reg = <4>;
894 regulator-name = "vdd-bl";
895 regulator-min-microvolt = <3300000>;
896 regulator-max-microvolt = <3300000>;
897 gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_LOW>;
898 };
899
900 vdd_ts_sw_5v0: regulator@5 {
901 compatible = "regulator-fixed";
902 reg = <5>;
903 regulator-name = "vdd_ts_sw";
904 regulator-min-microvolt = <5000000>;
905 regulator-max-microvolt = <5000000>;
906 enable-active-high;
907 regulator-boot-on;
908 gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_LOW>;
909 };
910
911 usb1_vbus_reg: regulator@6 {
912 compatible = "regulator-fixed";
913 reg = <6>;
914 regulator-name = "usb1_vbus";
915 regulator-min-microvolt = <5000000>;
916 regulator-max-microvolt = <5000000>;
917 regulator-boot-on;
918 enable-active-high;
919 gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
920 gpio-open-drain;
921 };
922
923 usb3_vbus_reg: regulator@7 {
924 compatible = "regulator-fixed";
925 reg = <7>;
926 regulator-name = "usb3_vbus";
927 regulator-min-microvolt = <5000000>;
928 regulator-max-microvolt = <5000000>;
929 regulator-boot-on;
930 enable-active-high;
931 gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
932 gpio-open-drain;
933 };
934
935 panel_3v3_reg: regulator@8 {
936 compatible = "regulator-fixed";
937 reg = <8>;
938 regulator-name = "panel_3v3";
939 regulator-min-microvolt = <3300000>;
940 regulator-max-microvolt = <3300000>;
941 enable-active-high;
942 gpio = <&as3722 4 GPIO_ACTIVE_HIGH>;
943 };
944 };
945
b0e1caee
SW		 946 sound {
947 compatible = "nvidia,tegra-audio-max98090-venice2",
948 "nvidia,tegra-audio-max98090";
949 nvidia,model = "NVIDIA Tegra Venice2";
950
951 nvidia,audio-routing =
952 "Headphones", "HPR",
953 "Headphones", "HPL",
954 "Speakers", "SPKR",
955 "Speakers", "SPKL",
956 "Mic Jack", "MICBIAS",
957 "IN34", "Mic Jack";
958
959 nvidia,i2s-controller = <&tegra_i2s1>;
960 nvidia,audio-codec = <&acodec>;
961
962 clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
963 <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
964 <&tegra_car TEGRA124_CLK_EXTERN1>;
965 clock-names = "pll_a", "pll_a_out0", "mclk";
966 };
a1425d42 967};
Linux kernel - Deliverables
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