[deliverable/linux.git] / arch / arm / boot / dts / tegra124.dtsi

#include <dt-bindings/clock/tegra124-car.h>
#include <dt-bindings/gpio/tegra-gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

#include "skeleton.dtsi"

/ {
	compatible = "nvidia,tegra124";
	interrupt-parent = <&gic>;

	gic: interrupt-controller@50041000 {
		compatible = "arm,cortex-a15-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x50041000 0x1000>,
		      <0x50042000 0x1000>,
		      <0x50044000 0x2000>,
		      <0x50046000 0x2000>;
		interrupts = <GIC_PPI 9
			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
	};

	timer@60005000 {
		compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
		reg = <0x60005000 0x400>;
		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA124_CLK_TIMER>;
	};

	tegra_car: clock@60006000 {
		compatible = "nvidia,tegra124-car";
		reg = <0x60006000 0x1000>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	gpio: gpio@6000d000 {
		compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
		reg = <0x6000d000 0x1000>;
		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	apbdma: dma@60020000 {
		compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
		reg = <0x60020000 0x1400>;
		interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
		resets = <&tegra_car 34>;
		reset-names = "dma";
		#dma-cells = <1>;
	};

	pinmux: pinmux@70000868 {
		compatible = "nvidia,tegra124-pinmux";
		reg = <0x70000868 0x164>,	/* Pad control registers */
		      <0x70003000 0x434>;	/* Mux registers */
	};

	/*
	 * There are two serial driver i.e. 8250 based simple serial
	 * driver and APB DMA based serial driver for higher baudrate
	 * and performace. To enable the 8250 based driver, the compatible
	 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
	 * the APB DMA based serial driver, the comptible is
	 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
	 */
	serial@70006000 {
		compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
		reg = <0x70006000 0x40>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA124_CLK_UARTA>;
		resets = <&tegra_car 6>;
		reset-names = "serial";
		dmas = <&apbdma 8>, <&apbdma 8>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	serial@70006040 {
		compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
		reg = <0x70006040 0x40>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA124_CLK_UARTB>;
		resets = <&tegra_car 7>;
		reset-names = "serial";
		dmas = <&apbdma 9>, <&apbdma 9>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	serial@70006200 {
		compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
		reg = <0x70006200 0x40>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA124_CLK_UARTC>;
		resets = <&tegra_car 55>;
		reset-names = "serial";
		dmas = <&apbdma 10>, <&apbdma 10>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	serial@70006300 {
		compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
		reg = <0x70006300 0x40>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA124_CLK_UARTD>;
		resets = <&tegra_car 65>;
		reset-names = "serial";
		dmas = <&apbdma 19>, <&apbdma 19>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	serial@70006400 {
		compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
		reg = <0x70006400 0x40>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA124_CLK_UARTE>;
		resets = <&tegra_car 66>;
		reset-names = "serial";
		dmas = <&apbdma 20>, <&apbdma 20>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	i2c@7000c000 {
		compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
		reg = <0x7000c000 0x100>;
		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA124_CLK_I2C1>;
		clock-names = "div-clk";
		resets = <&tegra_car 12>;
		reset-names = "i2c";
		dmas = <&apbdma 21>, <&apbdma 21>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	i2c@7000c400 {
		compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
		reg = <0x7000c400 0x100>;
		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA124_CLK_I2C2>;
		clock-names = "div-clk";
		resets = <&tegra_car 54>;
		reset-names = "i2c";
		dmas = <&apbdma 22>, <&apbdma 22>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	i2c@7000c500 {
		compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
		reg = <0x7000c500 0x100>;
		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA124_CLK_I2C3>;
		clock-names = "div-clk";
		resets = <&tegra_car 67>;
		reset-names = "i2c";
		dmas = <&apbdma 23>, <&apbdma 23>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	i2c@7000c700 {
		compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
		reg = <0x7000c700 0x100>;
		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA124_CLK_I2C4>;
		clock-names = "div-clk";
		resets = <&tegra_car 103>;
		reset-names = "i2c";
		dmas = <&apbdma 26>, <&apbdma 26>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	i2c@7000d000 {
		compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
		reg = <0x7000d000 0x100>;
		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA124_CLK_I2C5>;
		clock-names = "div-clk";
		resets = <&tegra_car 47>;
		reset-names = "i2c";
		dmas = <&apbdma 24>, <&apbdma 24>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	i2c@7000d100 {
		compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
		reg = <0x7000d100 0x100>;
		interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA124_CLK_I2C6>;
		clock-names = "div-clk";
		resets = <&tegra_car 166>;
		reset-names = "i2c";
		dmas = <&apbdma 30>, <&apbdma 30>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	rtc@7000e000 {
		compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
		reg = <0x7000e000 0x100>;
		interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA124_CLK_RTC>;
	};

	pmc@7000e400 {
		compatible = "nvidia,tegra124-pmc";
		reg = <0x7000e400 0x400>;
		clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
		clock-names = "pclk", "clk32k_in";
	};

	sdhci@700b0000 {
		compatible = "nvidia,tegra124-sdhci";
		reg = <0x700b0000 0x200>;
		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
		resets = <&tegra_car 14>;
		reset-names = "sdhci";
		status = "disable";
	};

	sdhci@700b0200 {
		compatible = "nvidia,tegra124-sdhci";
		reg = <0x700b0200 0x200>;
		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
		resets = <&tegra_car 9>;
		reset-names = "sdhci";
		status = "disable";
	};

	sdhci@700b0400 {
		compatible = "nvidia,tegra124-sdhci";
		reg = <0x700b0400 0x200>;
		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
		resets = <&tegra_car 69>;
		reset-names = "sdhci";
		status = "disable";
	};

	sdhci@700b0600 {
		compatible = "nvidia,tegra124-sdhci";
		reg = <0x700b0600 0x200>;
		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
		resets = <&tegra_car 15>;
		reset-names = "sdhci";
		status = "disable";
	};

	ahub@70300000 {
		compatible = "nvidia,tegra124-ahub";
		reg = <0x70300000 0x200>,
		      <0x70300800 0x800>,
		      <0x70300200 0x600>;
		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
			 <&tegra_car TEGRA124_CLK_APBIF>;
		clock-names = "d_audio", "apbif";
		resets = <&tegra_car 106>, /* d_audio */
			 <&tegra_car 107>, /* apbif */
			 <&tegra_car 30>,  /* i2s0 */
			 <&tegra_car 11>,  /* i2s1 */
			 <&tegra_car 18>,  /* i2s2 */
			 <&tegra_car 101>, /* i2s3 */
			 <&tegra_car 102>, /* i2s4 */
			 <&tegra_car 108>, /* dam0 */
			 <&tegra_car 109>, /* dam1 */
			 <&tegra_car 110>, /* dam2 */
			 <&tegra_car 10>,  /* spdif */
			 <&tegra_car 153>, /* amx */
			 <&tegra_car 185>, /* amx1 */
			 <&tegra_car 154>, /* adx */
			 <&tegra_car 180>, /* adx1 */
			 <&tegra_car 186>, /* afc0 */
			 <&tegra_car 187>, /* afc1 */
			 <&tegra_car 188>, /* afc2 */
			 <&tegra_car 189>, /* afc3 */
			 <&tegra_car 190>, /* afc4 */
			 <&tegra_car 191>; /* afc5 */
		reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
			      "i2s3", "i2s4", "dam0", "dam1", "dam2",
			      "spdif", "amx", "amx1", "adx", "adx1",
			      "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
		dmas = <&apbdma 1>, <&apbdma 1>,
		       <&apbdma 2>, <&apbdma 2>,
		       <&apbdma 3>, <&apbdma 3>,
		       <&apbdma 4>, <&apbdma 4>,
		       <&apbdma 6>, <&apbdma 6>,
		       <&apbdma 7>, <&apbdma 7>,
		       <&apbdma 12>, <&apbdma 12>,
		       <&apbdma 13>, <&apbdma 13>,
		       <&apbdma 14>, <&apbdma 14>,
		       <&apbdma 29>, <&apbdma 29>;
		dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
			    "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
			    "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
			    "rx9", "tx9";
		ranges;
		#address-cells = <1>;
		#size-cells = <1>;

		tegra_i2s0: i2s@70301000 {
			compatible = "nvidia,tegra124-i2s";
			reg = <0x70301000 0x100>;
			nvidia,ahub-cif-ids = <4 4>;
			clocks = <&tegra_car TEGRA124_CLK_I2S0>;
			resets = <&tegra_car 30>;
			reset-names = "i2s";
			status = "disabled";
		};

		tegra_i2s1: i2s@70301100 {
			compatible = "nvidia,tegra124-i2s";
			reg = <0x70301100 0x100>;
			nvidia,ahub-cif-ids = <5 5>;
			clocks = <&tegra_car TEGRA124_CLK_I2S1>;
			resets = <&tegra_car 11>;
			reset-names = "i2s";
			status = "disabled";
		};

		tegra_i2s2: i2s@70301200 {
			compatible = "nvidia,tegra124-i2s";
			reg = <0x70301200 0x100>;
			nvidia,ahub-cif-ids = <6 6>;
			clocks = <&tegra_car TEGRA124_CLK_I2S2>;
			resets = <&tegra_car 18>;
			reset-names = "i2s";
			status = "disabled";
		};

		tegra_i2s3: i2s@70301300 {
			compatible = "nvidia,tegra124-i2s";
			reg = <0x70301300 0x100>;
			nvidia,ahub-cif-ids = <7 7>;
			clocks = <&tegra_car TEGRA124_CLK_I2S3>;
			resets = <&tegra_car 101>;
			reset-names = "i2s";
			status = "disabled";
		};

		tegra_i2s4: i2s@70301400 {
			compatible = "nvidia,tegra124-i2s";
			reg = <0x70301400 0x100>;
			nvidia,ahub-cif-ids = <8 8>;
			clocks = <&tegra_car TEGRA124_CLK_I2S4>;
			resets = <&tegra_car 102>;
			reset-names = "i2s";
			status = "disabled";
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <1>;
		};

		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <2>;
		};

		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <3>;
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};
};
Commit	Line	Data
3b86baf2	1	#include <dt-bindings/clock/tegra124-car.h>
0a9375d1	2	#include <dt-bindings/gpio/tegra-gpio.h>
ad03b1a7 JL	3	#include <dt-bindings/interrupt-controller/arm-gic.h>
	4
	5	#include "skeleton.dtsi"
	6
	7	/ {
	8	compatible = "nvidia,tegra124";
	9	interrupt-parent = <&gic>;
	10
	11	gic: interrupt-controller@50041000 {
	12	compatible = "arm,cortex-a15-gic";
	13	#interrupt-cells = <3>;
	14	interrupt-controller;
	15	reg = <0x50041000 0x1000>,
	16	<0x50042000 0x1000>,
	17	<0x50044000 0x2000>,
	18	<0x50046000 0x2000>;
	19	interrupts = <GIC_PPI 9
	20	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	21	};
	22
	23	timer@60005000 {
	24	compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
	25	reg = <0x60005000 0x400>;
	26	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	27	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
	28	<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
	29	<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
	30	<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
	31	<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
3b86baf2 JL	32	clocks = <&tegra_car TEGRA124_CLK_TIMER>;
	33	};
	34
	35	tegra_car: clock@60006000 {
	36	compatible = "nvidia,tegra124-car";
	37	reg = <0x60006000 0x1000>;
	38	#clock-cells = <1>;
f71e4f03	39	#reset-cells = <1>;
ad03b1a7 JL	40	};
ad03b1a7 JL	41
0a9375d1 SW	42	gpio: gpio@6000d000 {
	43	compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
	44	reg = <0x6000d000 0x1000>;
	45	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
	46	<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
	47	<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
	48	<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
	49	<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
	50	<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
	51	<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
	52	<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
	53	#gpio-cells = <2>;
	54	gpio-controller;
	55	#interrupt-cells = <2>;
	56	interrupt-controller;
	57	};
	58
2f5a913e SW	59	apbdma: dma@60020000 {
	60	compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
	61	reg = <0x60020000 0x1400>;
	62	interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
	63	<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
	64	<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
	65	<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
	66	<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
	67	<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
	68	<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
	69	<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
	70	<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
	71	<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
	72	<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
	73	<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
	74	<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
	75	<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
	76	<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
	77	<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
	78	<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
	79	<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
	80	<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
	81	<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
	82	<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
	83	<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
	84	<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
	85	<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
	86	<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
	87	<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
	88	<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
	89	<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
	90	<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
	91	<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
	92	<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
	93	<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
	94	clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
	95	resets = <&tegra_car 34>;
	96	reset-names = "dma";
	97	#dma-cells = <1>;
	98	};
	99
caefe637 SW	100	pinmux: pinmux@70000868 {
	101	compatible = "nvidia,tegra124-pinmux";
	102	reg = <0x70000868 0x164>, /* Pad control registers */
	103	<0x70003000 0x434>; /* Mux registers */
	104	};
	105
ad03b1a7 JL	106	/*
	107	* There are two serial driver i.e. 8250 based simple serial
	108	* driver and APB DMA based serial driver for higher baudrate
	109	* and performace. To enable the 8250 based driver, the compatible
	110	* is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
	111	* the APB DMA based serial driver, the comptible is
	112	* "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
	113	*/
	114	serial@70006000 {
	115	compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
	116	reg = <0x70006000 0x40>;
	117	reg-shift = <2>;
	118	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
3b86baf2	119	clocks = <&tegra_car TEGRA124_CLK_UARTA>;
f71e4f03 SW	120	resets = <&tegra_car 6>;
f71e4f03 SW	121	reset-names = "serial";
2f5a913e SW	122	dmas = <&apbdma 8>, <&apbdma 8>;
2f5a913e SW	123	dma-names = "rx", "tx";
ad03b1a7 JL	124	status = "disabled";
	125	};
	126
	127	serial@70006040 {
	128	compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
	129	reg = <0x70006040 0x40>;
	130	reg-shift = <2>;
	131	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
3b86baf2	132	clocks = <&tegra_car TEGRA124_CLK_UARTB>;
f71e4f03 SW	133	resets = <&tegra_car 7>;
f71e4f03 SW	134	reset-names = "serial";
2f5a913e SW	135	dmas = <&apbdma 9>, <&apbdma 9>;
2f5a913e SW	136	dma-names = "rx", "tx";
ad03b1a7 JL	137	status = "disabled";
	138	};
	139
	140	serial@70006200 {
	141	compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
	142	reg = <0x70006200 0x40>;
	143	reg-shift = <2>;
	144	interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
3b86baf2	145	clocks = <&tegra_car TEGRA124_CLK_UARTC>;
f71e4f03 SW	146	resets = <&tegra_car 55>;
f71e4f03 SW	147	reset-names = "serial";
2f5a913e SW	148	dmas = <&apbdma 10>, <&apbdma 10>;
2f5a913e SW	149	dma-names = "rx", "tx";
ad03b1a7 JL	150	status = "disabled";
	151	};
	152
	153	serial@70006300 {
	154	compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
	155	reg = <0x70006300 0x40>;
	156	reg-shift = <2>;
	157	interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
3b86baf2	158	clocks = <&tegra_car TEGRA124_CLK_UARTD>;
f71e4f03 SW	159	resets = <&tegra_car 65>;
f71e4f03 SW	160	reset-names = "serial";
2f5a913e SW	161	dmas = <&apbdma 19>, <&apbdma 19>;
2f5a913e SW	162	dma-names = "rx", "tx";
ad03b1a7 JL	163	status = "disabled";
	164	};
	165
	166	serial@70006400 {
	167	compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
	168	reg = <0x70006400 0x40>;
	169	reg-shift = <2>;
	170	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
3b86baf2	171	clocks = <&tegra_car TEGRA124_CLK_UARTE>;
f71e4f03 SW	172	resets = <&tegra_car 66>;
f71e4f03 SW	173	reset-names = "serial";
2f5a913e SW	174	dmas = <&apbdma 20>, <&apbdma 20>;
2f5a913e SW	175	dma-names = "rx", "tx";
ad03b1a7 JL	176	status = "disabled";
	177	};
	178
4f607460 SW	179	i2c@7000c000 {
	180	compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
	181	reg = <0x7000c000 0x100>;
	182	interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
	183	#address-cells = <1>;
	184	#size-cells = <0>;
	185	clocks = <&tegra_car TEGRA124_CLK_I2C1>;
	186	clock-names = "div-clk";
	187	resets = <&tegra_car 12>;
	188	reset-names = "i2c";
	189	dmas = <&apbdma 21>, <&apbdma 21>;
	190	dma-names = "rx", "tx";
	191	status = "disabled";
	192	};
	193
	194	i2c@7000c400 {
	195	compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
	196	reg = <0x7000c400 0x100>;
	197	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
	198	#address-cells = <1>;
	199	#size-cells = <0>;
	200	clocks = <&tegra_car TEGRA124_CLK_I2C2>;
	201	clock-names = "div-clk";
	202	resets = <&tegra_car 54>;
	203	reset-names = "i2c";
	204	dmas = <&apbdma 22>, <&apbdma 22>;
	205	dma-names = "rx", "tx";
	206	status = "disabled";
	207	};
	208
	209	i2c@7000c500 {
	210	compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
	211	reg = <0x7000c500 0x100>;
	212	interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
	213	#address-cells = <1>;
	214	#size-cells = <0>;
	215	clocks = <&tegra_car TEGRA124_CLK_I2C3>;
	216	clock-names = "div-clk";
	217	resets = <&tegra_car 67>;
	218	reset-names = "i2c";
	219	dmas = <&apbdma 23>, <&apbdma 23>;
	220	dma-names = "rx", "tx";
	221	status = "disabled";
	222	};
	223
	224	i2c@7000c700 {
	225	compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
	226	reg = <0x7000c700 0x100>;
	227	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
	228	#address-cells = <1>;
	229	#size-cells = <0>;
	230	clocks = <&tegra_car TEGRA124_CLK_I2C4>;
	231	clock-names = "div-clk";
	232	resets = <&tegra_car 103>;
	233	reset-names = "i2c";
	234	dmas = <&apbdma 26>, <&apbdma 26>;
	235	dma-names = "rx", "tx";
	236	status = "disabled";
	237	};
	238
	239	i2c@7000d000 {
	240	compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
	241	reg = <0x7000d000 0x100>;
	242	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
243	#address-cells = <1>;
244	#size-cells = <0>;
245	clocks = <&tegra_car TEGRA124_CLK_I2C5>;
246	clock-names = "div-clk";
247	resets = <&tegra_car 47>;
248	reset-names = "i2c";
249	dmas = <&apbdma 24>, <&apbdma 24>;
250	dma-names = "rx", "tx";
251	status = "disabled";
252	};
253
254	i2c@7000d100 {
255	compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
256	reg = <0x7000d100 0x100>;
257	interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
258	#address-cells = <1>;
259	#size-cells = <0>;
260	clocks = <&tegra_car TEGRA124_CLK_I2C6>;
261	clock-names = "div-clk";
262	resets = <&tegra_car 166>;
263	reset-names = "i2c";
264	dmas = <&apbdma 30>, <&apbdma 30>;
265	dma-names = "rx", "tx";
266	status = "disabled";
267	};
268
ad03b1a7 JL	269	rtc@7000e000 {
	270	compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
	271	reg = <0x7000e000 0x100>;
	272	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
3b86baf2	273	clocks = <&tegra_car TEGRA124_CLK_RTC>;
ad03b1a7 JL	274	};
	275
	276	pmc@7000e400 {
	277	compatible = "nvidia,tegra124-pmc";
	278	reg = <0x7000e400 0x400>;
3b86baf2 JL	279	clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
3b86baf2 JL	280	clock-names = "pclk", "clk32k_in";
ad03b1a7 JL	281	};
ad03b1a7 JL	282
784c7444 SW	283	sdhci@700b0000 {
	284	compatible = "nvidia,tegra124-sdhci";
	285	reg = <0x700b0000 0x200>;
	286	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	287	clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
	288	resets = <&tegra_car 14>;
	289	reset-names = "sdhci";
	290	status = "disable";
	291	};
	292
	293	sdhci@700b0200 {
	294	compatible = "nvidia,tegra124-sdhci";
	295	reg = <0x700b0200 0x200>;
	296	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
	297	clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
	298	resets = <&tegra_car 9>;
	299	reset-names = "sdhci";
	300	status = "disable";
	301	};
	302
	303	sdhci@700b0400 {
	304	compatible = "nvidia,tegra124-sdhci";
	305	reg = <0x700b0400 0x200>;
	306	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	307	clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
	308	resets = <&tegra_car 69>;
	309	reset-names = "sdhci";
	310	status = "disable";
	311	};
	312
	313	sdhci@700b0600 {
	314	compatible = "nvidia,tegra124-sdhci";
	315	reg = <0x700b0600 0x200>;
	316	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	317	clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
	318	resets = <&tegra_car 15>;
	319	reset-names = "sdhci";
	320	status = "disable";
	321	};
	322
e6655578 SW	323	ahub@70300000 {
	324	compatible = "nvidia,tegra124-ahub";
	325	reg = <0x70300000 0x200>,
	326	<0x70300800 0x800>,
	327	<0x70300200 0x600>;
	328	interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
	329	clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
	330	<&tegra_car TEGRA124_CLK_APBIF>;
	331	clock-names = "d_audio", "apbif";
	332	resets = <&tegra_car 106>, /* d_audio */
	333	<&tegra_car 107>, /* apbif */
	334	<&tegra_car 30>, /* i2s0 */
	335	<&tegra_car 11>, /* i2s1 */
	336	<&tegra_car 18>, /* i2s2 */
	337	<&tegra_car 101>, /* i2s3 */
	338	<&tegra_car 102>, /* i2s4 */
	339	<&tegra_car 108>, /* dam0 */
	340	<&tegra_car 109>, /* dam1 */
	341	<&tegra_car 110>, /* dam2 */
	342	<&tegra_car 10>, /* spdif */
	343	<&tegra_car 153>, /* amx */
	344	<&tegra_car 185>, /* amx1 */
	345	<&tegra_car 154>, /* adx */
	346	<&tegra_car 180>, /* adx1 */
	347	<&tegra_car 186>, /* afc0 */
	348	<&tegra_car 187>, /* afc1 */
	349	<&tegra_car 188>, /* afc2 */
	350	<&tegra_car 189>, /* afc3 */
	351	<&tegra_car 190>, /* afc4 */
	352	<&tegra_car 191>; /* afc5 */
	353	reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
	354	"i2s3", "i2s4", "dam0", "dam1", "dam2",
	355	"spdif", "amx", "amx1", "adx", "adx1",
	356	"afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
	357	dmas = <&apbdma 1>, <&apbdma 1>,
	358	<&apbdma 2>, <&apbdma 2>,
	359	<&apbdma 3>, <&apbdma 3>,
	360	<&apbdma 4>, <&apbdma 4>,
	361	<&apbdma 6>, <&apbdma 6>,
	362	<&apbdma 7>, <&apbdma 7>,
	363	<&apbdma 12>, <&apbdma 12>,
	364	<&apbdma 13>, <&apbdma 13>,
	365	<&apbdma 14>, <&apbdma 14>,
	366	<&apbdma 29>, <&apbdma 29>;
	367	dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
	368	"rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
	369	"rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
	370	"rx9", "tx9";
	371	ranges;
	372	#address-cells = <1>;
	373	#size-cells = <1>;
	374
	375	tegra_i2s0: i2s@70301000 {
	376	compatible = "nvidia,tegra124-i2s";
	377	reg = <0x70301000 0x100>;
	378	nvidia,ahub-cif-ids = <4 4>;
	379	clocks = <&tegra_car TEGRA124_CLK_I2S0>;
	380	resets = <&tegra_car 30>;
	381	reset-names = "i2s";
	382	status = "disabled";
	383	};
	384
	385	tegra_i2s1: i2s@70301100 {
	386	compatible = "nvidia,tegra124-i2s";
387	reg = <0x70301100 0x100>;
388	nvidia,ahub-cif-ids = <5 5>;
389	clocks = <&tegra_car TEGRA124_CLK_I2S1>;
390	resets = <&tegra_car 11>;
391	reset-names = "i2s";
392	status = "disabled";
393	};
394
395	tegra_i2s2: i2s@70301200 {
396	compatible = "nvidia,tegra124-i2s";
397	reg = <0x70301200 0x100>;
398	nvidia,ahub-cif-ids = <6 6>;
399	clocks = <&tegra_car TEGRA124_CLK_I2S2>;
400	resets = <&tegra_car 18>;
401	reset-names = "i2s";
402	status = "disabled";
403	};
404
405	tegra_i2s3: i2s@70301300 {
406	compatible = "nvidia,tegra124-i2s";
407	reg = <0x70301300 0x100>;
408	nvidia,ahub-cif-ids = <7 7>;
409	clocks = <&tegra_car TEGRA124_CLK_I2S3>;
410	resets = <&tegra_car 101>;
411	reset-names = "i2s";
412	status = "disabled";
413	};
414
415	tegra_i2s4: i2s@70301400 {
416	compatible = "nvidia,tegra124-i2s";
417	reg = <0x70301400 0x100>;
418	nvidia,ahub-cif-ids = <8 8>;
419	clocks = <&tegra_car TEGRA124_CLK_I2S4>;
420	resets = <&tegra_car 102>;
421	reset-names = "i2s";
422	status = "disabled";
423	};
424	};
425
ad03b1a7 JL	426	cpus {
	427	#address-cells = <1>;
	428	#size-cells = <0>;
	429
	430	cpu@0 {
	431	device_type = "cpu";
	432	compatible = "arm,cortex-a15";
	433	reg = <0>;
	434	};
	435
	436	cpu@1 {
	437	device_type = "cpu";
	438	compatible = "arm,cortex-a15";
	439	reg = <1>;
	440	};
	441
	442	cpu@2 {
	443	device_type = "cpu";
	444	compatible = "arm,cortex-a15";
	445	reg = <2>;
	446	};
	447
	448	cpu@3 {
	449	device_type = "cpu";
	450	compatible = "arm,cortex-a15";
	451	reg = <3>;
	452	};
	453	};
	454
	455	timer {
	456	compatible = "arm,armv7-timer";
	457	interrupts = <GIC_PPI 13
	458	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	459	<GIC_PPI 14
	460	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	461	<GIC_PPI 11
	462	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	463	<GIC_PPI 10
	464	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
	465	};
	466	};