Commit | Line | Data |
---|---|---|
1bd0bd49 | 1 | #include "tegra20.dtsi" |
307e28ee TR |
2 | |
3 | / { | |
4 | model = "Avionic Design Tamonten SOM"; | |
5 | compatible = "ad,tamonten", "nvidia,tegra20"; | |
6 | ||
553c0a20 SW |
7 | aliases { |
8 | rtc0 = "/i2c@7000d000/tps6586x@34"; | |
9 | rtc1 = "/rtc@7000e000"; | |
c4574aa0 | 10 | serial0 = &uartd; |
553c0a20 SW |
11 | }; |
12 | ||
f5bbb327 JH |
13 | chosen { |
14 | stdout-path = "serial0:115200n8"; | |
15 | }; | |
16 | ||
307e28ee TR |
17 | memory { |
18 | reg = <0x00000000 0x20000000>; | |
19 | }; | |
20 | ||
58ecb23f SW |
21 | host1x@50000000 { |
22 | hdmi@54280000 { | |
e6f09796 TR |
23 | vdd-supply = <&hdmi_vdd_reg>; |
24 | pll-supply = <&hdmi_pll_reg>; | |
25 | ||
26 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; | |
3325f1bc SW |
27 | nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) |
28 | GPIO_ACTIVE_HIGH>; | |
e6f09796 TR |
29 | }; |
30 | }; | |
31 | ||
58ecb23f | 32 | pinmux@70000014 { |
307e28ee TR |
33 | pinctrl-names = "default"; |
34 | pinctrl-0 = <&state_default>; | |
35 | ||
36 | state_default: pinmux { | |
37 | ata { | |
38 | nvidia,pins = "ata"; | |
39 | nvidia,function = "ide"; | |
40 | }; | |
41 | atb { | |
42 | nvidia,pins = "atb", "gma", "gme"; | |
43 | nvidia,function = "sdio4"; | |
44 | }; | |
45 | atc { | |
46 | nvidia,pins = "atc"; | |
47 | nvidia,function = "nand"; | |
48 | }; | |
49 | atd { | |
50 | nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu", | |
51 | "spia", "spib", "spic"; | |
52 | nvidia,function = "gmi"; | |
53 | }; | |
54 | cdev1 { | |
55 | nvidia,pins = "cdev1"; | |
56 | nvidia,function = "plla_out"; | |
57 | }; | |
58 | cdev2 { | |
59 | nvidia,pins = "cdev2"; | |
60 | nvidia,function = "pllp_out4"; | |
61 | }; | |
62 | crtp { | |
63 | nvidia,pins = "crtp"; | |
64 | nvidia,function = "crt"; | |
65 | }; | |
66 | csus { | |
67 | nvidia,pins = "csus"; | |
68 | nvidia,function = "vi_sensor_clk"; | |
69 | }; | |
70 | dap1 { | |
71 | nvidia,pins = "dap1"; | |
72 | nvidia,function = "dap1"; | |
73 | }; | |
74 | dap2 { | |
75 | nvidia,pins = "dap2"; | |
76 | nvidia,function = "dap2"; | |
77 | }; | |
78 | dap3 { | |
79 | nvidia,pins = "dap3"; | |
80 | nvidia,function = "dap3"; | |
81 | }; | |
82 | dap4 { | |
83 | nvidia,pins = "dap4"; | |
84 | nvidia,function = "dap4"; | |
85 | }; | |
307e28ee TR |
86 | dta { |
87 | nvidia,pins = "dta", "dtd"; | |
88 | nvidia,function = "sdio2"; | |
89 | }; | |
90 | dtb { | |
91 | nvidia,pins = "dtb", "dtc", "dte"; | |
92 | nvidia,function = "rsvd1"; | |
93 | }; | |
94 | dtf { | |
95 | nvidia,pins = "dtf"; | |
96 | nvidia,function = "i2c3"; | |
97 | }; | |
98 | gmc { | |
99 | nvidia,pins = "gmc"; | |
100 | nvidia,function = "uartd"; | |
101 | }; | |
102 | gpu7 { | |
103 | nvidia,pins = "gpu7"; | |
104 | nvidia,function = "rtck"; | |
105 | }; | |
106 | gpv { | |
107 | nvidia,pins = "gpv", "slxa", "slxk"; | |
108 | nvidia,function = "pcie"; | |
109 | }; | |
110 | hdint { | |
ec319903 | 111 | nvidia,pins = "hdint"; |
307e28ee TR |
112 | nvidia,function = "hdmi"; |
113 | }; | |
114 | i2cp { | |
115 | nvidia,pins = "i2cp"; | |
116 | nvidia,function = "i2cp"; | |
117 | }; | |
118 | irrx { | |
119 | nvidia,pins = "irrx", "irtx"; | |
120 | nvidia,function = "uarta"; | |
121 | }; | |
122 | kbca { | |
123 | nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", | |
124 | "kbce", "kbcf"; | |
125 | nvidia,function = "kbc"; | |
126 | }; | |
127 | lcsn { | |
128 | nvidia,pins = "lcsn", "ld0", "ld1", "ld2", | |
129 | "ld3", "ld4", "ld5", "ld6", "ld7", | |
130 | "ld8", "ld9", "ld10", "ld11", "ld12", | |
131 | "ld13", "ld14", "ld15", "ld16", "ld17", | |
132 | "ldc", "ldi", "lhp0", "lhp1", "lhp2", | |
133 | "lhs", "lm0", "lm1", "lpp", "lpw0", | |
134 | "lpw1", "lpw2", "lsc0", "lsc1", "lsck", | |
135 | "lsda", "lsdi", "lspi", "lvp0", "lvp1", | |
136 | "lvs"; | |
137 | nvidia,function = "displaya"; | |
138 | }; | |
139 | owc { | |
140 | nvidia,pins = "owc", "spdi", "spdo", "uac"; | |
141 | nvidia,function = "rsvd2"; | |
142 | }; | |
143 | pmc { | |
144 | nvidia,pins = "pmc"; | |
145 | nvidia,function = "pwr_on"; | |
146 | }; | |
147 | rm { | |
148 | nvidia,pins = "rm"; | |
149 | nvidia,function = "i2c1"; | |
150 | }; | |
151 | sdb { | |
152 | nvidia,pins = "sdb", "sdc", "sdd"; | |
153 | nvidia,function = "pwm"; | |
154 | }; | |
155 | sdio1 { | |
156 | nvidia,pins = "sdio1"; | |
157 | nvidia,function = "sdio1"; | |
158 | }; | |
159 | slxc { | |
160 | nvidia,pins = "slxc", "slxd"; | |
161 | nvidia,function = "spdif"; | |
162 | }; | |
163 | spid { | |
164 | nvidia,pins = "spid", "spie", "spif"; | |
165 | nvidia,function = "spi1"; | |
166 | }; | |
167 | spig { | |
168 | nvidia,pins = "spig", "spih"; | |
169 | nvidia,function = "spi2_alt"; | |
170 | }; | |
171 | uaa { | |
172 | nvidia,pins = "uaa", "uab", "uda"; | |
173 | nvidia,function = "ulpi"; | |
174 | }; | |
175 | uad { | |
176 | nvidia,pins = "uad"; | |
177 | nvidia,function = "irda"; | |
178 | }; | |
179 | uca { | |
180 | nvidia,pins = "uca", "ucb"; | |
181 | nvidia,function = "uartc"; | |
182 | }; | |
183 | conf_ata { | |
184 | nvidia,pins = "ata", "atb", "atc", "atd", "ate", | |
185 | "cdev1", "cdev2", "dap1", "dtb", "gma", | |
186 | "gmb", "gmc", "gmd", "gme", "gpu7", | |
187 | "gpv", "i2cp", "pta", "rm", "slxa", | |
188 | "slxk", "spia", "spib", "uac"; | |
ba4104e7 LD |
189 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
190 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
307e28ee TR |
191 | }; |
192 | conf_ck32 { | |
193 | nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", | |
194 | "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; | |
ba4104e7 | 195 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
307e28ee TR |
196 | }; |
197 | conf_csus { | |
198 | nvidia,pins = "csus", "spid", "spif"; | |
ba4104e7 LD |
199 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
200 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
307e28ee TR |
201 | }; |
202 | conf_crtp { | |
203 | nvidia,pins = "crtp", "dap2", "dap3", "dap4", | |
204 | "dtc", "dte", "dtf", "gpu", "sdio1", | |
205 | "slxc", "slxd", "spdi", "spdo", "spig", | |
206 | "uda"; | |
ba4104e7 LD |
207 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
208 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
307e28ee TR |
209 | }; |
210 | conf_ddc { | |
211 | nvidia,pins = "ddc", "dta", "dtd", "kbca", | |
212 | "kbcb", "kbcc", "kbcd", "kbce", "kbcf", | |
213 | "sdc"; | |
ba4104e7 LD |
214 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
215 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
307e28ee TR |
216 | }; |
217 | conf_hdint { | |
218 | nvidia,pins = "hdint", "lcsn", "ldc", "lm1", | |
219 | "lpw1", "lsc1", "lsck", "lsda", "lsdi", | |
220 | "lvp0", "owc", "sdb"; | |
ba4104e7 | 221 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
307e28ee TR |
222 | }; |
223 | conf_irrx { | |
224 | nvidia,pins = "irrx", "irtx", "sdd", "spic", | |
225 | "spie", "spih", "uaa", "uab", "uad", | |
226 | "uca", "ucb"; | |
ba4104e7 LD |
227 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
228 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
307e28ee TR |
229 | }; |
230 | conf_lc { | |
231 | nvidia,pins = "lc", "ls"; | |
ba4104e7 | 232 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
307e28ee TR |
233 | }; |
234 | conf_ld0 { | |
235 | nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", | |
236 | "ld5", "ld6", "ld7", "ld8", "ld9", | |
237 | "ld10", "ld11", "ld12", "ld13", "ld14", | |
238 | "ld15", "ld16", "ld17", "ldi", "lhp0", | |
239 | "lhp1", "lhp2", "lhs", "lm0", "lpp", | |
240 | "lpw0", "lpw2", "lsc0", "lspi", "lvp1", | |
241 | "lvs", "pmc"; | |
ba4104e7 | 242 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
307e28ee TR |
243 | }; |
244 | conf_ld17_0 { | |
245 | nvidia,pins = "ld17_0", "ld19_18", "ld21_20", | |
246 | "ld23_22"; | |
ba4104e7 | 247 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
307e28ee TR |
248 | }; |
249 | }; | |
ec319903 TR |
250 | |
251 | state_i2cmux_ddc: pinmux_i2cmux_ddc { | |
252 | ddc { | |
253 | nvidia,pins = "ddc"; | |
254 | nvidia,function = "i2c2"; | |
255 | }; | |
256 | pta { | |
257 | nvidia,pins = "pta"; | |
258 | nvidia,function = "rsvd4"; | |
259 | }; | |
260 | }; | |
261 | ||
262 | state_i2cmux_pta: pinmux_i2cmux_pta { | |
263 | ddc { | |
264 | nvidia,pins = "ddc"; | |
265 | nvidia,function = "rsvd4"; | |
266 | }; | |
267 | pta { | |
268 | nvidia,pins = "pta"; | |
269 | nvidia,function = "i2c2"; | |
270 | }; | |
271 | }; | |
272 | ||
273 | state_i2cmux_idle: pinmux_i2cmux_idle { | |
274 | ddc { | |
275 | nvidia,pins = "ddc"; | |
276 | nvidia,function = "rsvd4"; | |
277 | }; | |
278 | pta { | |
279 | nvidia,pins = "pta"; | |
280 | nvidia,function = "rsvd4"; | |
281 | }; | |
282 | }; | |
307e28ee TR |
283 | }; |
284 | ||
285 | i2s@70002800 { | |
286 | status = "okay"; | |
287 | }; | |
288 | ||
289 | serial@70006300 { | |
307e28ee TR |
290 | status = "okay"; |
291 | }; | |
292 | ||
293 | i2c@7000c000 { | |
294 | clock-frequency = <400000>; | |
295 | status = "okay"; | |
296 | }; | |
297 | ||
ec319903 TR |
298 | i2c@7000c400 { |
299 | clock-frequency = <100000>; | |
300 | status = "okay"; | |
301 | }; | |
302 | ||
303 | i2cmux { | |
304 | compatible = "i2c-mux-pinctrl"; | |
305 | #address-cells = <1>; | |
306 | #size-cells = <0>; | |
307 | ||
308 | i2c-parent = <&{/i2c@7000c400}>; | |
309 | ||
310 | pinctrl-names = "ddc", "pta", "idle"; | |
311 | pinctrl-0 = <&state_i2cmux_ddc>; | |
312 | pinctrl-1 = <&state_i2cmux_pta>; | |
313 | pinctrl-2 = <&state_i2cmux_idle>; | |
314 | ||
e6f09796 | 315 | hdmi_ddc: i2c@0 { |
ec319903 TR |
316 | reg = <0>; |
317 | #address-cells = <1>; | |
318 | #size-cells = <0>; | |
319 | }; | |
320 | ||
321 | i2c@1 { | |
322 | reg = <1>; | |
323 | #address-cells = <1>; | |
324 | #size-cells = <0>; | |
325 | }; | |
326 | }; | |
327 | ||
307e28ee TR |
328 | i2c@7000d000 { |
329 | clock-frequency = <400000>; | |
330 | status = "okay"; | |
331 | ||
332 | pmic: tps6586x@34 { | |
333 | compatible = "ti,tps6586x"; | |
334 | reg = <0x34>; | |
6cecf916 | 335 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
307e28ee TR |
336 | |
337 | ti,system-power-controller; | |
338 | ||
339 | #gpio-cells = <2>; | |
340 | gpio-controller; | |
341 | ||
23e63345 | 342 | /* vdd_5v0_reg must be provided by the base board */ |
307e28ee TR |
343 | sys-supply = <&vdd_5v0_reg>; |
344 | vin-sm0-supply = <&sys_reg>; | |
345 | vin-sm1-supply = <&sys_reg>; | |
346 | vin-sm2-supply = <&sys_reg>; | |
347 | vinldo01-supply = <&sm2_reg>; | |
348 | vinldo23-supply = <&sm2_reg>; | |
349 | vinldo4-supply = <&sm2_reg>; | |
350 | vinldo678-supply = <&sm2_reg>; | |
351 | vinldo9-supply = <&sm2_reg>; | |
352 | ||
353 | regulators { | |
b9c665d7 | 354 | sys_reg: sys { |
307e28ee TR |
355 | regulator-name = "vdd_sys"; |
356 | regulator-always-on; | |
357 | }; | |
358 | ||
b9c665d7 | 359 | sm0 { |
307e28ee TR |
360 | regulator-name = "vdd_sys_sm0,vdd_core"; |
361 | regulator-min-microvolt = <1200000>; | |
362 | regulator-max-microvolt = <1200000>; | |
363 | regulator-always-on; | |
364 | }; | |
365 | ||
b9c665d7 | 366 | sm1 { |
307e28ee TR |
367 | regulator-name = "vdd_sys_sm1,vdd_cpu"; |
368 | regulator-min-microvolt = <1000000>; | |
369 | regulator-max-microvolt = <1000000>; | |
370 | regulator-always-on; | |
371 | }; | |
372 | ||
b9c665d7 | 373 | sm2_reg: sm2 { |
307e28ee TR |
374 | regulator-name = "vdd_sys_sm2,vin_ldo*"; |
375 | regulator-min-microvolt = <3700000>; | |
376 | regulator-max-microvolt = <3700000>; | |
377 | regulator-always-on; | |
378 | }; | |
379 | ||
1b2d6b84 | 380 | pci_clk_reg: ldo0 { |
307e28ee TR |
381 | regulator-name = "vdd_ldo0,vddio_pex_clk"; |
382 | regulator-min-microvolt = <3300000>; | |
383 | regulator-max-microvolt = <3300000>; | |
384 | }; | |
385 | ||
b9c665d7 | 386 | ldo1 { |
307e28ee TR |
387 | regulator-name = "vdd_ldo1,avdd_pll*"; |
388 | regulator-min-microvolt = <1100000>; | |
389 | regulator-max-microvolt = <1100000>; | |
390 | regulator-always-on; | |
391 | }; | |
392 | ||
b9c665d7 | 393 | ldo2 { |
307e28ee TR |
394 | regulator-name = "vdd_ldo2,vdd_rtc"; |
395 | regulator-min-microvolt = <1200000>; | |
396 | regulator-max-microvolt = <1200000>; | |
397 | }; | |
398 | ||
b9c665d7 | 399 | ldo3 { |
307e28ee TR |
400 | regulator-name = "vdd_ldo3,avdd_usb*"; |
401 | regulator-min-microvolt = <3300000>; | |
402 | regulator-max-microvolt = <3300000>; | |
403 | regulator-always-on; | |
404 | }; | |
405 | ||
b9c665d7 | 406 | ldo4 { |
307e28ee TR |
407 | regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; |
408 | regulator-min-microvolt = <1800000>; | |
409 | regulator-max-microvolt = <1800000>; | |
410 | regulator-always-on; | |
411 | }; | |
412 | ||
b9c665d7 | 413 | ldo5 { |
307e28ee TR |
414 | regulator-name = "vdd_ldo5,vcore_mmc"; |
415 | regulator-min-microvolt = <2850000>; | |
416 | regulator-max-microvolt = <2850000>; | |
417 | }; | |
418 | ||
b9c665d7 | 419 | ldo6 { |
307e28ee TR |
420 | regulator-name = "vdd_ldo6,avdd_vdac"; |
421 | /* | |
422 | * According to the Tegra 2 Automotive | |
423 | * DataSheet, a typical value for this | |
424 | * would be 2.8V, but the PMIC only | |
425 | * supports 2.85V. | |
426 | */ | |
427 | regulator-min-microvolt = <2850000>; | |
428 | regulator-max-microvolt = <2850000>; | |
429 | }; | |
430 | ||
e6f09796 | 431 | hdmi_vdd_reg: ldo7 { |
307e28ee TR |
432 | regulator-name = "vdd_ldo7,avdd_hdmi"; |
433 | regulator-min-microvolt = <3300000>; | |
434 | regulator-max-microvolt = <3300000>; | |
435 | }; | |
436 | ||
e6f09796 | 437 | hdmi_pll_reg: ldo8 { |
307e28ee TR |
438 | regulator-name = "vdd_ldo8,avdd_hdmi_pll"; |
439 | regulator-min-microvolt = <1800000>; | |
440 | regulator-max-microvolt = <1800000>; | |
441 | }; | |
442 | ||
b9c665d7 | 443 | ldo9 { |
307e28ee TR |
444 | regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam"; |
445 | /* | |
446 | * According to the Tegra 2 Automotive | |
447 | * DataSheet, a typical value for this | |
448 | * would be 2.8V, but the PMIC only | |
449 | * supports 2.85V. | |
450 | */ | |
451 | regulator-min-microvolt = <2850000>; | |
452 | regulator-max-microvolt = <2850000>; | |
453 | regulator-always-on; | |
454 | }; | |
455 | ||
b9c665d7 | 456 | ldo_rtc { |
307e28ee TR |
457 | regulator-name = "vdd_rtc_out"; |
458 | regulator-min-microvolt = <3300000>; | |
459 | regulator-max-microvolt = <3300000>; | |
460 | regulator-always-on; | |
461 | }; | |
462 | }; | |
463 | }; | |
840a4080 TR |
464 | |
465 | temperature-sensor@4c { | |
466 | compatible = "onnn,nct1008"; | |
467 | reg = <0x4c>; | |
468 | }; | |
307e28ee TR |
469 | }; |
470 | ||
58ecb23f | 471 | pmc@7000e400 { |
307e28ee | 472 | nvidia,invert-interrupt; |
47d2d63b | 473 | nvidia,suspend-mode = <1>; |
a44a019d JL |
474 | nvidia,cpu-pwr-good-time = <5000>; |
475 | nvidia,cpu-pwr-off-time = <5000>; | |
476 | nvidia,core-pwr-good-time = <3845 3845>; | |
477 | nvidia,core-pwr-off-time = <3875>; | |
478 | nvidia,sys-clock-req-active-high; | |
307e28ee TR |
479 | }; |
480 | ||
58ecb23f | 481 | pcie-controller@80003000 { |
cca8614d TR |
482 | avdd-pex-supply = <&pci_vdd_reg>; |
483 | vdd-pex-supply = <&pci_vdd_reg>; | |
484 | avdd-pex-pll-supply = <&pci_vdd_reg>; | |
485 | avdd-plle-supply = <&pci_vdd_reg>; | |
486 | vddio-pex-clk-supply = <&pci_clk_reg>; | |
1b2d6b84 TR |
487 | }; |
488 | ||
307e28ee TR |
489 | usb@c5008000 { |
490 | status = "okay"; | |
491 | }; | |
492 | ||
4c94c8b5 VB |
493 | usb-phy@c5008000 { |
494 | status = "okay"; | |
495 | }; | |
496 | ||
307e28ee | 497 | sdhci@c8000600 { |
3325f1bc SW |
498 | cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>; |
499 | wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; | |
307e28ee TR |
500 | bus-width = <4>; |
501 | status = "okay"; | |
502 | }; | |
503 | ||
7021d122 JL |
504 | clocks { |
505 | compatible = "simple-bus"; | |
506 | #address-cells = <1>; | |
507 | #size-cells = <0>; | |
508 | ||
58ecb23f | 509 | clk32k_in: clock@0 { |
7021d122 JL |
510 | compatible = "fixed-clock"; |
511 | reg=<0>; | |
512 | #clock-cells = <0>; | |
513 | clock-frequency = <32768>; | |
514 | }; | |
515 | }; | |
516 | ||
307e28ee TR |
517 | regulators { |
518 | compatible = "simple-bus"; | |
519 | ||
520 | #address-cells = <1>; | |
521 | #size-cells = <0>; | |
522 | ||
1b2d6b84 TR |
523 | pci_vdd_reg: regulator@1 { |
524 | compatible = "regulator-fixed"; | |
525 | reg = <1>; | |
526 | regulator-name = "vdd_1v05"; | |
527 | regulator-min-microvolt = <1050000>; | |
528 | regulator-max-microvolt = <1050000>; | |
529 | gpio = <&pmic 2 0>; | |
530 | enable-active-high; | |
531 | }; | |
307e28ee TR |
532 | }; |
533 | }; |